1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Atmel QSPI Controller
5 * Copyright (C) 2015 Atmel Corporation
6 * Copyright (C) 2018 Cryptera A/S
8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
19 #include <dm/device_compat.h>
20 #include <linux/err.h>
22 #include <linux/iopoll.h>
23 #include <linux/ioport.h>
28 /* QSPI register offsets */
29 #define QSPI_CR 0x0000 /* Control Register */
30 #define QSPI_MR 0x0004 /* Mode Register */
31 #define QSPI_RD 0x0008 /* Receive Data Register */
32 #define QSPI_TD 0x000c /* Transmit Data Register */
33 #define QSPI_SR 0x0010 /* Status Register */
34 #define QSPI_IER 0x0014 /* Interrupt Enable Register */
35 #define QSPI_IDR 0x0018 /* Interrupt Disable Register */
36 #define QSPI_IMR 0x001c /* Interrupt Mask Register */
37 #define QSPI_SCR 0x0020 /* Serial Clock Register */
39 #define QSPI_IAR 0x0030 /* Instruction Address Register */
40 #define QSPI_ICR 0x0034 /* Instruction Code Register */
41 #define QSPI_WICR 0x0034 /* Write Instruction Code Register */
42 #define QSPI_IFR 0x0038 /* Instruction Frame Register */
43 #define QSPI_RICR 0x003C /* Read Instruction Code Register */
45 #define QSPI_SMR 0x0040 /* Scrambling Mode Register */
46 #define QSPI_SKR 0x0044 /* Scrambling Key Register */
48 #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
49 #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
51 #define QSPI_VERSION 0x00FC /* Version Register */
53 /* Bitfields in QSPI_CR (Control Register) */
54 #define QSPI_CR_QSPIEN BIT(0)
55 #define QSPI_CR_QSPIDIS BIT(1)
56 #define QSPI_CR_SWRST BIT(7)
57 #define QSPI_CR_LASTXFER BIT(24)
59 /* Bitfields in QSPI_MR (Mode Register) */
60 #define QSPI_MR_SMM BIT(0)
61 #define QSPI_MR_LLB BIT(1)
62 #define QSPI_MR_WDRBT BIT(2)
63 #define QSPI_MR_SMRM BIT(3)
64 #define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
65 #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
66 #define QSPI_MR_CSMODE_LASTXFER (1 << 4)
67 #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
68 #define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
69 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
70 #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
71 #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
72 #define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
73 #define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
75 /* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
76 #define QSPI_SR_RDRF BIT(0)
77 #define QSPI_SR_TDRE BIT(1)
78 #define QSPI_SR_TXEMPTY BIT(2)
79 #define QSPI_SR_OVRES BIT(3)
80 #define QSPI_SR_CSR BIT(8)
81 #define QSPI_SR_CSS BIT(9)
82 #define QSPI_SR_INSTRE BIT(10)
83 #define QSPI_SR_QSPIENS BIT(24)
85 #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
87 /* Bitfields in QSPI_SCR (Serial Clock Register) */
88 #define QSPI_SCR_CPOL BIT(0)
89 #define QSPI_SCR_CPHA BIT(1)
90 #define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
91 #define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
92 #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
93 #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
95 /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
96 #define QSPI_ICR_INST_MASK GENMASK(7, 0)
97 #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
98 #define QSPI_ICR_OPT_MASK GENMASK(23, 16)
99 #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
101 /* Bitfields in QSPI_IFR (Instruction Frame Register) */
102 #define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
103 #define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
104 #define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
105 #define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
106 #define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
107 #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
108 #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
109 #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
110 #define QSPI_IFR_INSTEN BIT(4)
111 #define QSPI_IFR_ADDREN BIT(5)
112 #define QSPI_IFR_OPTEN BIT(6)
113 #define QSPI_IFR_DATAEN BIT(7)
114 #define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
115 #define QSPI_IFR_OPTL_1BIT (0 << 8)
116 #define QSPI_IFR_OPTL_2BIT (1 << 8)
117 #define QSPI_IFR_OPTL_4BIT (2 << 8)
118 #define QSPI_IFR_OPTL_8BIT (3 << 8)
119 #define QSPI_IFR_ADDRL BIT(10)
120 #define QSPI_IFR_TFRTYP_MEM BIT(12)
121 #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
122 #define QSPI_IFR_CRM BIT(14)
123 #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
124 #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
125 #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
127 /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
128 #define QSPI_SMR_SCREN BIT(0)
129 #define QSPI_SMR_RVDIS BIT(1)
131 /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
132 #define QSPI_WPMR_WPEN BIT(0)
133 #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
134 #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
136 /* Bitfields in QSPI_WPSR (Write Protection Status Register) */
137 #define QSPI_WPSR_WPVS BIT(0)
138 #define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
139 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
141 struct atmel_qspi_caps {
149 resource_size_t mmap_size;
150 const struct atmel_qspi_caps *caps;
156 struct atmel_qspi_mode {
163 static const struct atmel_qspi_mode atmel_qspi_modes[] = {
164 { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
165 { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
166 { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
167 { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
168 { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
169 { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
170 { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
174 static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
214 snprintf(tmp, sz, "0x%02x", offset);
220 #endif /* VERBOSE_DEBUG */
222 static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
224 u32 value = readl(aq->regs + offset);
229 dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
230 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
231 #endif /* VERBOSE_DEBUG */
236 static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
241 dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
242 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
243 #endif /* VERBOSE_DEBUG */
245 writel(value, aq->regs + offset);
248 static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
249 const struct atmel_qspi_mode *mode)
251 if (op->cmd.buswidth != mode->cmd_buswidth)
254 if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
257 if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
263 static int atmel_qspi_find_mode(const struct spi_mem_op *op)
267 for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
268 if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
274 static bool atmel_qspi_supports_op(struct spi_slave *slave,
275 const struct spi_mem_op *op)
277 if (atmel_qspi_find_mode(op) < 0)
280 /* special case not supported by hardware */
281 if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
282 op->dummy.nbytes == 0)
288 static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
289 const struct spi_mem_op *op, u32 *offset)
292 u32 dummy_cycles = 0;
296 icr = QSPI_ICR_INST(op->cmd.opcode);
297 ifr = QSPI_IFR_INSTEN;
299 mode = atmel_qspi_find_mode(op);
302 ifr |= atmel_qspi_modes[mode].config;
304 if (op->dummy.buswidth && op->dummy.nbytes)
305 dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
308 * The controller allows 24 and 32-bit addressing while NAND-flash
309 * requires 16-bit long. Handling 8-bit long addresses is done using
310 * the option field. For the 16-bit addresses, the workaround depends
311 * of the number of requested dummy bits. If there are 8 or more dummy
312 * cycles, the address is shifted and sent with the first dummy byte.
313 * Otherwise opcode is disabled and the first byte of the address
314 * contains the command opcode (works only if the opcode and address
315 * use the same buswidth). The limitation is when the 16-bit address is
316 * used without enough dummy cycles and the opcode is using a different
317 * buswidth than the address.
319 if (op->addr.buswidth) {
320 switch (op->addr.nbytes) {
324 ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
325 icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
328 if (dummy_cycles < 8 / op->addr.buswidth) {
329 ifr &= ~QSPI_IFR_INSTEN;
330 ifr |= QSPI_IFR_ADDREN;
331 iar = (op->cmd.opcode << 16) |
332 (op->addr.val & 0xffff);
334 ifr |= QSPI_IFR_ADDREN;
335 iar = (op->addr.val << 8) & 0xffffff;
336 dummy_cycles -= 8 / op->addr.buswidth;
340 ifr |= QSPI_IFR_ADDREN;
341 iar = op->addr.val & 0xffffff;
344 ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
345 iar = op->addr.val & 0x7ffffff;
352 /* offset of the data access in the QSPI memory space */
355 /* Set number of dummy cycles */
357 ifr |= QSPI_IFR_NBDUM(dummy_cycles);
359 /* Set data enable */
361 ifr |= QSPI_IFR_DATAEN;
364 * If the QSPI controller is set in regular SPI mode, set it in
365 * Serial Memory Mode (SMM).
367 if (aq->mr != QSPI_MR_SMM) {
368 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
369 aq->mr = QSPI_MR_SMM;
372 /* Clear pending interrupts */
373 (void)atmel_qspi_read(aq, QSPI_SR);
375 if (aq->caps->has_ricr) {
376 if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
377 ifr |= QSPI_IFR_APBTFRTYP_READ;
379 /* Set QSPI Instruction Frame registers */
380 atmel_qspi_write(iar, aq, QSPI_IAR);
381 if (op->data.dir == SPI_MEM_DATA_IN)
382 atmel_qspi_write(icr, aq, QSPI_RICR);
384 atmel_qspi_write(icr, aq, QSPI_WICR);
385 atmel_qspi_write(ifr, aq, QSPI_IFR);
387 if (op->data.dir == SPI_MEM_DATA_OUT)
388 ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
390 /* Set QSPI Instruction Frame registers */
391 atmel_qspi_write(iar, aq, QSPI_IAR);
392 atmel_qspi_write(icr, aq, QSPI_ICR);
393 atmel_qspi_write(ifr, aq, QSPI_IFR);
399 static int atmel_qspi_exec_op(struct spi_slave *slave,
400 const struct spi_mem_op *op)
402 struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
407 * Check if the address exceeds the MMIO window size. An improvement
408 * would be to add support for regular SPI mode and fall back to it
409 * when the flash memories overrun the controller's memory space.
411 if (op->addr.val + op->data.nbytes > aq->mmap_size)
414 err = atmel_qspi_set_cfg(aq, op, &offset);
418 /* Skip to the final steps if there is no data */
419 if (op->data.nbytes) {
420 /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
421 (void)atmel_qspi_read(aq, QSPI_IFR);
423 /* Send/Receive data */
424 if (op->data.dir == SPI_MEM_DATA_IN)
425 memcpy_fromio(op->data.buf.in, aq->mem + offset,
428 memcpy_toio(aq->mem + offset, op->data.buf.out,
431 /* Release the chip-select */
432 atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
435 /* Poll INSTruction End and Chip Select Rise flags. */
436 imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
437 return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
441 static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
443 struct atmel_qspi *aq = dev_get_priv(bus);
444 u32 scr, scbr, mask, new_value;
446 /* Compute the QSPI baudrate */
447 scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
451 new_value = QSPI_SCR_SCBR(scbr);
452 mask = QSPI_SCR_SCBR_MASK;
454 scr = atmel_qspi_read(aq, QSPI_SCR);
455 if ((scr & mask) == new_value)
458 scr = (scr & ~mask) | new_value;
459 atmel_qspi_write(scr, aq, QSPI_SCR);
464 static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
466 struct atmel_qspi *aq = dev_get_priv(bus);
467 u32 scr, mask, new_value = 0;
470 new_value = QSPI_SCR_CPOL;
472 new_value = QSPI_SCR_CPHA;
474 mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
476 scr = atmel_qspi_read(aq, QSPI_SCR);
477 if ((scr & mask) == new_value)
480 scr = (scr & ~mask) | new_value;
481 atmel_qspi_write(scr, aq, QSPI_SCR);
486 static int atmel_qspi_enable_clk(struct udevice *dev)
488 struct atmel_qspi *aq = dev_get_priv(dev);
489 struct clk pclk, qspick;
492 ret = clk_get_by_name(dev, "pclk", &pclk);
494 ret = clk_get_by_index(dev, 0, &pclk);
497 dev_err(dev, "Missing QSPI peripheral clock\n");
501 ret = clk_enable(&pclk);
503 dev_err(dev, "Failed to enable QSPI peripheral clock\n");
507 if (aq->caps->has_qspick) {
508 /* Get the QSPI system clock */
509 ret = clk_get_by_name(dev, "qspick", &qspick);
511 dev_err(dev, "Missing QSPI peripheral clock\n");
515 ret = clk_enable(&qspick);
517 dev_err(dev, "Failed to enable QSPI system clock\n");
521 aq->bus_clk_rate = clk_get_rate(&pclk);
522 if (!aq->bus_clk_rate)
531 static void atmel_qspi_init(struct atmel_qspi *aq)
533 /* Reset the QSPI controller */
534 atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
536 /* Set the QSPI controller by default in Serial Memory Mode */
537 atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
538 aq->mr = QSPI_MR_SMM;
540 /* Enable the QSPI controller */
541 atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
544 static int atmel_qspi_probe(struct udevice *dev)
546 struct atmel_qspi *aq = dev_get_priv(dev);
550 aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
552 dev_err(dev, "Could not retrieve QSPI caps\n");
556 /* Map the registers */
557 ret = dev_read_resource_byname(dev, "qspi_base", &res);
559 dev_err(dev, "missing registers\n");
563 aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
564 if (IS_ERR(aq->regs))
565 return PTR_ERR(aq->regs);
567 /* Map the AHB memory */
568 ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
570 dev_err(dev, "missing AHB memory\n");
574 aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
576 return PTR_ERR(aq->mem);
578 aq->mmap_size = resource_size(&res);
580 ret = atmel_qspi_enable_clk(dev);
591 static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
592 .supports_op = atmel_qspi_supports_op,
593 .exec_op = atmel_qspi_exec_op,
596 static const struct dm_spi_ops atmel_qspi_ops = {
597 .set_speed = atmel_qspi_set_speed,
598 .set_mode = atmel_qspi_set_mode,
599 .mem_ops = &atmel_qspi_mem_ops,
602 static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
604 static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
609 static const struct udevice_id atmel_qspi_ids[] = {
611 .compatible = "atmel,sama5d2-qspi",
612 .data = (ulong)&atmel_sama5d2_qspi_caps,
615 .compatible = "microchip,sam9x60-qspi",
616 .data = (ulong)&atmel_sam9x60_qspi_caps,
621 U_BOOT_DRIVER(atmel_qspi) = {
622 .name = "atmel_qspi",
624 .of_match = atmel_qspi_ids,
625 .ops = &atmel_qspi_ops,
626 .priv_auto_alloc_size = sizeof(struct atmel_qspi),
627 .probe = atmel_qspi_probe,