drivers/soundwire/intel.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
   2 // Copyright(c) 2015-17 Intel Corporation.
   3
   4 /*
   5  * Soundwire Intel Master Driver
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/delay.h>
  10 #include <linux/module.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/platform_device.h>
  13 #include <sound/pcm_params.h>
  14 #include <sound/soc.h>
  15 #include <linux/soundwire/sdw_registers.h>
  16 #include <linux/soundwire/sdw.h>
  17 #include <linux/soundwire/sdw_intel.h>
  18 #include "cadence_master.h"
  19 #include "intel.h"
  20
  21 /* Intel SHIM Registers Definition */
  22 #define SDW_SHIM_LCAP                   0x0
  23 #define SDW_SHIM_LCTL                   0x4
  24 #define SDW_SHIM_IPPTR                  0x8
  25 #define SDW_SHIM_SYNC                   0xC
  26
  27 #define SDW_SHIM_CTLSCAP(x)             (0x010 + 0x60 * (x))
  28 #define SDW_SHIM_CTLS0CM(x)             (0x012 + 0x60 * (x))
  29 #define SDW_SHIM_CTLS1CM(x)             (0x014 + 0x60 * (x))
  30 #define SDW_SHIM_CTLS2CM(x)             (0x016 + 0x60 * (x))
  31 #define SDW_SHIM_CTLS3CM(x)             (0x018 + 0x60 * (x))
  32 #define SDW_SHIM_PCMSCAP(x)             (0x020 + 0x60 * (x))
  33
  34 #define SDW_SHIM_PCMSYCHM(x, y)         (0x022 + (0x60 * (x)) + (0x2 * (y)))
  35 #define SDW_SHIM_PCMSYCHC(x, y)         (0x042 + (0x60 * (x)) + (0x2 * (y)))
  36 #define SDW_SHIM_PDMSCAP(x)             (0x062 + 0x60 * (x))
  37 #define SDW_SHIM_IOCTL(x)               (0x06C + 0x60 * (x))
  38 #define SDW_SHIM_CTMCTL(x)              (0x06E + 0x60 * (x))
  39
  40 #define SDW_SHIM_WAKEEN                 0x190
  41 #define SDW_SHIM_WAKESTS                0x192
  42
  43 #define SDW_SHIM_LCTL_SPA               BIT(0)
  44 #define SDW_SHIM_LCTL_CPA               BIT(8)
  45
  46 #define SDW_SHIM_SYNC_SYNCPRD_VAL       0x176F
  47 #define SDW_SHIM_SYNC_SYNCPRD           GENMASK(14, 0)
  48 #define SDW_SHIM_SYNC_SYNCCPU           BIT(15)
  49 #define SDW_SHIM_SYNC_CMDSYNC_MASK      GENMASK(19, 16)
  50 #define SDW_SHIM_SYNC_CMDSYNC           BIT(16)
  51 #define SDW_SHIM_SYNC_SYNCGO            BIT(24)
  52
  53 #define SDW_SHIM_PCMSCAP_ISS            GENMASK(3, 0)
  54 #define SDW_SHIM_PCMSCAP_OSS            GENMASK(7, 4)
  55 #define SDW_SHIM_PCMSCAP_BSS            GENMASK(12, 8)
  56
  57 #define SDW_SHIM_PCMSYCM_LCHN           GENMASK(3, 0)
  58 #define SDW_SHIM_PCMSYCM_HCHN           GENMASK(7, 4)
  59 #define SDW_SHIM_PCMSYCM_STREAM         GENMASK(13, 8)
  60 #define SDW_SHIM_PCMSYCM_DIR            BIT(15)
  61
  62 #define SDW_SHIM_PDMSCAP_ISS            GENMASK(3, 0)
  63 #define SDW_SHIM_PDMSCAP_OSS            GENMASK(7, 4)
  64 #define SDW_SHIM_PDMSCAP_BSS            GENMASK(12, 8)
  65 #define SDW_SHIM_PDMSCAP_CPSS           GENMASK(15, 13)
  66
  67 #define SDW_SHIM_IOCTL_MIF              BIT(0)
  68 #define SDW_SHIM_IOCTL_CO               BIT(1)
  69 #define SDW_SHIM_IOCTL_COE              BIT(2)
  70 #define SDW_SHIM_IOCTL_DO               BIT(3)
  71 #define SDW_SHIM_IOCTL_DOE              BIT(4)
  72 #define SDW_SHIM_IOCTL_BKE              BIT(5)
  73 #define SDW_SHIM_IOCTL_WPDD             BIT(6)
  74 #define SDW_SHIM_IOCTL_CIBD             BIT(8)
  75 #define SDW_SHIM_IOCTL_DIBD             BIT(9)
  76
  77 #define SDW_SHIM_CTMCTL_DACTQE          BIT(0)
  78 #define SDW_SHIM_CTMCTL_DODS            BIT(1)
  79 #define SDW_SHIM_CTMCTL_DOAIS           GENMASK(4, 3)
  80
  81 #define SDW_SHIM_WAKEEN_ENABLE          BIT(0)
  82 #define SDW_SHIM_WAKESTS_STATUS         BIT(0)
  83
  84 /* Intel ALH Register definitions */
  85 #define SDW_ALH_STRMZCFG(x)             (0x000 + (0x4 * (x)))
  86
  87 #define SDW_ALH_STRMZCFG_DMAT_VAL       0x3
  88 #define SDW_ALH_STRMZCFG_DMAT           GENMASK(7, 0)
  89 #define SDW_ALH_STRMZCFG_CHN            GENMASK(19, 16)
  90
  91 enum intel_pdi_type {
  92         INTEL_PDI_IN = 0,
  93         INTEL_PDI_OUT = 1,
  94         INTEL_PDI_BD = 2,
  95 };
  96
  97 struct sdw_intel {
  98         struct sdw_cdns cdns;
  99         int instance;
 100         struct sdw_intel_link_res *res;
 101 };
 102
 103 #define cdns_to_intel(_cdns) container_of(_cdns, struct sdw_intel, cdns)
 104
 105 /*
 106  * Read, write helpers for HW registers
 107  */
 108 static inline int intel_readl(void __iomem *base, int offset)
 109 {
 110         return readl(base + offset);
 111 }
 112
 113 static inline void intel_writel(void __iomem *base, int offset, int value)
 114 {
 115         writel(value, base + offset);
 116 }
 117
 118 static inline u16 intel_readw(void __iomem *base, int offset)
 119 {
 120         return readw(base + offset);
 121 }
 122
 123 static inline void intel_writew(void __iomem *base, int offset, u16 value)
 124 {
 125         writew(value, base + offset);
 126 }
 127
 128 static int intel_clear_bit(void __iomem *base, int offset, u32 value, u32 mask)
 129 {
 130         int timeout = 10;
 131         u32 reg_read;
 132
 133         writel(value, base + offset);
 134         do {
 135                 reg_read = readl(base + offset);
 136                 if (!(reg_read & mask))
 137                         return 0;
 138
 139                 timeout--;
 140                 udelay(50);
 141         } while (timeout != 0);
 142
 143         return -EAGAIN;
 144 }
 145
 146 static int intel_set_bit(void __iomem *base, int offset, u32 value, u32 mask)
 147 {
 148         int timeout = 10;
 149         u32 reg_read;
 150
 151         writel(value, base + offset);
 152         do {
 153                 reg_read = readl(base + offset);
 154                 if (reg_read & mask)
 155                         return 0;
 156
 157                 timeout--;
 158                 udelay(50);
 159         } while (timeout != 0);
 160
 161         return -EAGAIN;
 162 }
 163
 164 /*
 165  * shim ops
 166  */
 167
 168 static int intel_link_power_up(struct sdw_intel *sdw)
 169 {
 170         unsigned int link_id = sdw->instance;
 171         void __iomem *shim = sdw->res->shim;
 172         int spa_mask, cpa_mask;
 173         int link_control, ret;
 174
 175         /* Link power up sequence */
 176         link_control = intel_readl(shim, SDW_SHIM_LCTL);
 177         spa_mask = (SDW_SHIM_LCTL_SPA << link_id);
 178         cpa_mask = (SDW_SHIM_LCTL_CPA << link_id);
 179         link_control |=  spa_mask;
 180
 181         ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);
 182         if (ret < 0)
 183                 return ret;
 184
 185         sdw->cdns.link_up = true;
 186         return 0;
 187 }
 188
 189 static int intel_shim_init(struct sdw_intel *sdw)
 190 {
 191         void __iomem *shim = sdw->res->shim;
 192         unsigned int link_id = sdw->instance;
 193         int sync_reg, ret;
 194         u16 ioctl = 0, act = 0;
 195
 196         /* Initialize Shim */
 197         ioctl |= SDW_SHIM_IOCTL_BKE;
 198         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 199
 200         ioctl |= SDW_SHIM_IOCTL_WPDD;
 201         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 202
 203         ioctl |= SDW_SHIM_IOCTL_DO;
 204         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 205
 206         ioctl |= SDW_SHIM_IOCTL_DOE;
 207         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 208
 209         /* Switch to MIP from Glue logic */
 210         ioctl = intel_readw(shim,  SDW_SHIM_IOCTL(link_id));
 211
 212         ioctl &= ~(SDW_SHIM_IOCTL_DOE);
 213         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 214
 215         ioctl &= ~(SDW_SHIM_IOCTL_DO);
 216         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 217
 218         ioctl |= (SDW_SHIM_IOCTL_MIF);
 219         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 220
 221         ioctl &= ~(SDW_SHIM_IOCTL_BKE);
 222         ioctl &= ~(SDW_SHIM_IOCTL_COE);
 223
 224         intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);
 225
 226         act |= 0x1 << SDW_REG_SHIFT(SDW_SHIM_CTMCTL_DOAIS);
 227         act |= SDW_SHIM_CTMCTL_DACTQE;
 228         act |= SDW_SHIM_CTMCTL_DODS;
 229         intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);
 230
 231         /* Now set SyncPRD period */
 232         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 233         sync_reg |= (SDW_SHIM_SYNC_SYNCPRD_VAL <<
 234                         SDW_REG_SHIFT(SDW_SHIM_SYNC_SYNCPRD));
 235
 236         /* Set SyncCPU bit */
 237         sync_reg |= SDW_SHIM_SYNC_SYNCCPU;
 238         ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
 239                               SDW_SHIM_SYNC_SYNCCPU);
 240         if (ret < 0)
 241                 dev_err(sdw->cdns.dev, "Failed to set sync period: %d\n", ret);
 242
 243         return ret;
 244 }
 245
 246 /*
 247  * PDI routines
 248  */
 249 static void intel_pdi_init(struct sdw_intel *sdw,
 250                            struct sdw_cdns_stream_config *config)
 251 {
 252         void __iomem *shim = sdw->res->shim;
 253         unsigned int link_id = sdw->instance;
 254         int pcm_cap, pdm_cap;
 255
 256         /* PCM Stream Capability */
 257         pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));
 258
 259         config->pcm_bd = (pcm_cap & SDW_SHIM_PCMSCAP_BSS) >>
 260                                         SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_BSS);
 261         config->pcm_in = (pcm_cap & SDW_SHIM_PCMSCAP_ISS) >>
 262                                         SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_ISS);
 263         config->pcm_out = (pcm_cap & SDW_SHIM_PCMSCAP_OSS) >>
 264                                         SDW_REG_SHIFT(SDW_SHIM_PCMSCAP_OSS);
 265
 266         dev_dbg(sdw->cdns.dev, "PCM cap bd:%d in:%d out:%d\n",
 267                 config->pcm_bd, config->pcm_in, config->pcm_out);
 268
 269         /* PDM Stream Capability */
 270         pdm_cap = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
 271
 272         config->pdm_bd = (pdm_cap & SDW_SHIM_PDMSCAP_BSS) >>
 273                                         SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_BSS);
 274         config->pdm_in = (pdm_cap & SDW_SHIM_PDMSCAP_ISS) >>
 275                                         SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_ISS);
 276         config->pdm_out = (pdm_cap & SDW_SHIM_PDMSCAP_OSS) >>
 277                                         SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_OSS);
 278
 279         dev_dbg(sdw->cdns.dev, "PDM cap bd:%d in:%d out:%d\n",
 280                 config->pdm_bd, config->pdm_in, config->pdm_out);
 281 }
 282
 283 static int
 284 intel_pdi_get_ch_cap(struct sdw_intel *sdw, unsigned int pdi_num, bool pcm)
 285 {
 286         void __iomem *shim = sdw->res->shim;
 287         unsigned int link_id = sdw->instance;
 288         int count;
 289
 290         if (pcm) {
 291                 count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));
 292
 293                 /*
 294                  * WORKAROUND: on all existing Intel controllers, pdi
 295                  * number 2 reports channel count as 1 even though it
 296                  * supports 8 channels. Performing hardcoding for pdi
 297                  * number 2.
 298                  */
 299                 if (pdi_num == 2)
 300                         count = 7;
 301
 302         } else {
 303                 count = intel_readw(shim, SDW_SHIM_PDMSCAP(link_id));
 304                 count = ((count & SDW_SHIM_PDMSCAP_CPSS) >>
 305                                         SDW_REG_SHIFT(SDW_SHIM_PDMSCAP_CPSS));
 306         }
 307
 308         /* zero based values for channel count in register */
 309         count++;
 310
 311         return count;
 312 }
 313
 314 static int intel_pdi_get_ch_update(struct sdw_intel *sdw,
 315                                    struct sdw_cdns_pdi *pdi,
 316                                    unsigned int num_pdi,
 317                                    unsigned int *num_ch, bool pcm)
 318 {
 319         int i, ch_count = 0;
 320
 321         for (i = 0; i < num_pdi; i++) {
 322                 pdi->ch_count = intel_pdi_get_ch_cap(sdw, pdi->num, pcm);
 323                 ch_count += pdi->ch_count;
 324                 pdi++;
 325         }
 326
 327         *num_ch = ch_count;
 328         return 0;
 329 }
 330
 331 static int intel_pdi_stream_ch_update(struct sdw_intel *sdw,
 332                                       struct sdw_cdns_streams *stream, bool pcm)
 333 {
 334         intel_pdi_get_ch_update(sdw, stream->bd, stream->num_bd,
 335                                 &stream->num_ch_bd, pcm);
 336
 337         intel_pdi_get_ch_update(sdw, stream->in, stream->num_in,
 338                                 &stream->num_ch_in, pcm);
 339
 340         intel_pdi_get_ch_update(sdw, stream->out, stream->num_out,
 341                                 &stream->num_ch_out, pcm);
 342
 343         return 0;
 344 }
 345
 346 static int intel_pdi_ch_update(struct sdw_intel *sdw)
 347 {
 348         /* First update PCM streams followed by PDM streams */
 349         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pcm, true);
 350         intel_pdi_stream_ch_update(sdw, &sdw->cdns.pdm, false);
 351
 352         return 0;
 353 }
 354
 355 static void
 356 intel_pdi_shim_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 357 {
 358         void __iomem *shim = sdw->res->shim;
 359         unsigned int link_id = sdw->instance;
 360         int pdi_conf = 0;
 361
 362         pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
 363
 364         /*
 365          * Program stream parameters to stream SHIM register
 366          * This is applicable for PCM stream only.
 367          */
 368         if (pdi->type != SDW_STREAM_PCM)
 369                 return;
 370
 371         if (pdi->dir == SDW_DATA_DIR_RX)
 372                 pdi_conf |= SDW_SHIM_PCMSYCM_DIR;
 373         else
 374                 pdi_conf &= ~(SDW_SHIM_PCMSYCM_DIR);
 375
 376         pdi_conf |= (pdi->intel_alh_id <<
 377                         SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_STREAM));
 378         pdi_conf |= (pdi->l_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_LCHN));
 379         pdi_conf |= (pdi->h_ch_num << SDW_REG_SHIFT(SDW_SHIM_PCMSYCM_HCHN));
 380
 381         intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);
 382 }
 383
 384 static void
 385 intel_pdi_alh_configure(struct sdw_intel *sdw, struct sdw_cdns_pdi *pdi)
 386 {
 387         void __iomem *alh = sdw->res->alh;
 388         unsigned int link_id = sdw->instance;
 389         unsigned int conf;
 390
 391         pdi->intel_alh_id = (link_id * 16) + pdi->num + 5;
 392
 393         /* Program Stream config ALH register */
 394         conf = intel_readl(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id));
 395
 396         conf |= (SDW_ALH_STRMZCFG_DMAT_VAL <<
 397                         SDW_REG_SHIFT(SDW_ALH_STRMZCFG_DMAT));
 398
 399         conf |= ((pdi->ch_count - 1) <<
 400                         SDW_REG_SHIFT(SDW_ALH_STRMZCFG_CHN));
 401
 402         intel_writel(alh, SDW_ALH_STRMZCFG(pdi->intel_alh_id), conf);
 403 }
 404
 405 static int intel_config_stream(struct sdw_intel *sdw,
 406                                struct snd_pcm_substream *substream,
 407                                struct snd_soc_dai *dai,
 408                                struct snd_pcm_hw_params *hw_params, int link_id)
 409 {
 410         if (sdw->res->ops && sdw->res->ops->config_stream)
 411                 return sdw->res->ops->config_stream(sdw->res->arg,
 412                                 substream, dai, hw_params, link_id);
 413
 414         return -EIO;
 415 }
 416
 417 /*
 418  * bank switch routines
 419  */
 420
 421 static int intel_pre_bank_switch(struct sdw_bus *bus)
 422 {
 423         struct sdw_cdns *cdns = bus_to_cdns(bus);
 424         struct sdw_intel *sdw = cdns_to_intel(cdns);
 425         void __iomem *shim = sdw->res->shim;
 426         int sync_reg;
 427
 428         /* Write to register only for multi-link */
 429         if (!bus->multi_link)
 430                 return 0;
 431
 432         /* Read SYNC register */
 433         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 434         sync_reg |= SDW_SHIM_SYNC_CMDSYNC << sdw->instance;
 435         intel_writel(shim, SDW_SHIM_SYNC, sync_reg);
 436
 437         return 0;
 438 }
 439
 440 static int intel_post_bank_switch(struct sdw_bus *bus)
 441 {
 442         struct sdw_cdns *cdns = bus_to_cdns(bus);
 443         struct sdw_intel *sdw = cdns_to_intel(cdns);
 444         void __iomem *shim = sdw->res->shim;
 445         int sync_reg, ret;
 446
 447         /* Write to register only for multi-link */
 448         if (!bus->multi_link)
 449                 return 0;
 450
 451         /* Read SYNC register */
 452         sync_reg = intel_readl(shim, SDW_SHIM_SYNC);
 453
 454         /*
 455          * post_bank_switch() ops is called from the bus in loop for
 456          * all the Masters in the steam with the expectation that
 457          * we trigger the bankswitch for the only first Master in the list
 458          * and do nothing for the other Masters
 459          *
 460          * So, set the SYNCGO bit only if CMDSYNC bit is set for any Master.
 461          */
 462         if (!(sync_reg & SDW_SHIM_SYNC_CMDSYNC_MASK))
 463                 return 0;
 464
 465         /*
 466          * Set SyncGO bit to synchronously trigger a bank switch for
 467          * all the masters. A write to SYNCGO bit clears CMDSYNC bit for all
 468          * the Masters.
 469          */
 470         sync_reg |= SDW_SHIM_SYNC_SYNCGO;
 471
 472         ret = intel_clear_bit(shim, SDW_SHIM_SYNC, sync_reg,
 473                               SDW_SHIM_SYNC_SYNCGO);
 474         if (ret < 0)
 475                 dev_err(sdw->cdns.dev, "Post bank switch failed: %d\n", ret);
 476
 477         return ret;
 478 }
 479
 480 /*
 481  * DAI routines
 482  */
 483
 484 static struct sdw_cdns_port *intel_alloc_port(struct sdw_intel *sdw,
 485                                               u32 ch, u32 dir, bool pcm)
 486 {
 487         struct sdw_cdns *cdns = &sdw->cdns;
 488         struct sdw_cdns_port *port = NULL;
 489         int i, ret = 0;
 490
 491         for (i = 0; i < cdns->num_ports; i++) {
 492                 if (cdns->ports[i].assigned)
 493                         continue;
 494
 495                 port = &cdns->ports[i];
 496                 port->assigned = true;
 497                 port->direction = dir;
 498                 port->ch = ch;
 499                 break;
 500         }
 501
 502         if (!port) {
 503                 dev_err(cdns->dev, "Unable to find a free port\n");
 504                 return NULL;
 505         }
 506
 507         if (pcm) {
 508                 ret = sdw_cdns_alloc_stream(cdns, &cdns->pcm, port, ch, dir);
 509                 if (ret)
 510                         goto out;
 511
 512                 intel_pdi_shim_configure(sdw, port->pdi);
 513                 sdw_cdns_config_stream(cdns, port, ch, dir, port->pdi);
 514
 515                 intel_pdi_alh_configure(sdw, port->pdi);
 516
 517         } else {
 518                 ret = sdw_cdns_alloc_stream(cdns, &cdns->pdm, port, ch, dir);
 519         }
 520
 521 out:
 522         if (ret) {
 523                 port->assigned = false;
 524                 port = NULL;
 525         }
 526
 527         return port;
 528 }
 529
 530 static void intel_port_cleanup(struct sdw_cdns_dma_data *dma)
 531 {
 532         int i;
 533
 534         for (i = 0; i < dma->nr_ports; i++) {
 535                 if (dma->port[i]) {
 536                         dma->port[i]->pdi->assigned = false;
 537                         dma->port[i]->pdi = NULL;
 538                         dma->port[i]->assigned = false;
 539                         dma->port[i] = NULL;
 540                 }
 541         }
 542 }
 543
 544 static int intel_hw_params(struct snd_pcm_substream *substream,
 545                            struct snd_pcm_hw_params *params,
 546                            struct snd_soc_dai *dai)
 547 {
 548         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 549         struct sdw_intel *sdw = cdns_to_intel(cdns);
 550         struct sdw_cdns_dma_data *dma;
 551         struct sdw_stream_config sconfig;
 552         struct sdw_port_config *pconfig;
 553         int ret, i, ch, dir;
 554         bool pcm = true;
 555
 556         dma = snd_soc_dai_get_dma_data(dai, substream);
 557         if (!dma)
 558                 return -EIO;
 559
 560         ch = params_channels(params);
 561         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 562                 dir = SDW_DATA_DIR_RX;
 563         else
 564                 dir = SDW_DATA_DIR_TX;
 565
 566         if (dma->stream_type == SDW_STREAM_PDM) {
 567                 /* TODO: Check whether PDM decimator is already in use */
 568                 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pdm, ch, dir);
 569                 pcm = false;
 570         } else {
 571                 dma->nr_ports = sdw_cdns_get_stream(cdns, &cdns->pcm, ch, dir);
 572         }
 573
 574         if (!dma->nr_ports) {
 575                 dev_err(dai->dev, "ports/resources not available\n");
 576                 return -EINVAL;
 577         }
 578
 579         dma->port = kcalloc(dma->nr_ports, sizeof(*dma->port), GFP_KERNEL);
 580         if (!dma->port)
 581                 return -ENOMEM;
 582
 583         for (i = 0; i < dma->nr_ports; i++) {
 584                 dma->port[i] = intel_alloc_port(sdw, ch, dir, pcm);
 585                 if (!dma->port[i]) {
 586                         ret = -EINVAL;
 587                         goto port_error;
 588                 }
 589         }
 590
 591         /* Inform DSP about PDI stream number */
 592         for (i = 0; i < dma->nr_ports; i++) {
 593                 ret = intel_config_stream(sdw, substream, dai, params,
 594                                           dma->port[i]->pdi->intel_alh_id);
 595                 if (ret)
 596                         goto port_error;
 597         }
 598
 599         sconfig.direction = dir;
 600         sconfig.ch_count = ch;
 601         sconfig.frame_rate = params_rate(params);
 602         sconfig.type = dma->stream_type;
 603
 604         if (dma->stream_type == SDW_STREAM_PDM) {
 605                 sconfig.frame_rate *= 50;
 606                 sconfig.bps = 1;
 607         } else {
 608                 sconfig.bps = snd_pcm_format_width(params_format(params));
 609         }
 610
 611         /* Port configuration */
 612         pconfig = kcalloc(dma->nr_ports, sizeof(*pconfig), GFP_KERNEL);
 613         if (!pconfig) {
 614                 ret =  -ENOMEM;
 615                 goto port_error;
 616         }
 617
 618         for (i = 0; i < dma->nr_ports; i++) {
 619                 pconfig[i].num = dma->port[i]->num;
 620                 pconfig[i].ch_mask = (1 << ch) - 1;
 621         }
 622
 623         ret = sdw_stream_add_master(&cdns->bus, &sconfig,
 624                                     pconfig, dma->nr_ports, dma->stream);
 625         if (ret) {
 626                 dev_err(cdns->dev, "add master to stream failed:%d\n", ret);
 627                 goto stream_error;
 628         }
 629
 630         kfree(pconfig);
 631         return ret;
 632
 633 stream_error:
 634         kfree(pconfig);
 635 port_error:
 636         intel_port_cleanup(dma);
 637         kfree(dma->port);
 638         return ret;
 639 }
 640
 641 static int
 642 intel_hw_free(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
 643 {
 644         struct sdw_cdns *cdns = snd_soc_dai_get_drvdata(dai);
 645         struct sdw_cdns_dma_data *dma;
 646         int ret;
 647
 648         dma = snd_soc_dai_get_dma_data(dai, substream);
 649         if (!dma)
 650                 return -EIO;
 651
 652         ret = sdw_stream_remove_master(&cdns->bus, dma->stream);
 653         if (ret < 0)
 654                 dev_err(dai->dev, "remove master from stream %s failed: %d\n",
 655                         dma->stream->name, ret);
 656
 657         intel_port_cleanup(dma);
 658         kfree(dma->port);
 659         return ret;
 660 }
 661
 662 static int intel_pcm_set_sdw_stream(struct snd_soc_dai *dai,
 663                                     void *stream, int direction)
 664 {
 665         return cdns_set_sdw_stream(dai, stream, true, direction);
 666 }
 667
 668 static int intel_pdm_set_sdw_stream(struct snd_soc_dai *dai,
 669                                     void *stream, int direction)
 670 {
 671         return cdns_set_sdw_stream(dai, stream, false, direction);
 672 }
 673
 674 static const struct snd_soc_dai_ops intel_pcm_dai_ops = {
 675         .hw_params = intel_hw_params,
 676         .hw_free = intel_hw_free,
 677         .shutdown = sdw_cdns_shutdown,
 678         .set_sdw_stream = intel_pcm_set_sdw_stream,
 679 };
 680
 681 static const struct snd_soc_dai_ops intel_pdm_dai_ops = {
 682         .hw_params = intel_hw_params,
 683         .hw_free = intel_hw_free,
 684         .shutdown = sdw_cdns_shutdown,
 685         .set_sdw_stream = intel_pdm_set_sdw_stream,
 686 };
 687
 688 static const struct snd_soc_component_driver dai_component = {
 689         .name           = "soundwire",
 690 };
 691
 692 static int intel_create_dai(struct sdw_cdns *cdns,
 693                             struct snd_soc_dai_driver *dais,
 694                             enum intel_pdi_type type,
 695                             u32 num, u32 off, u32 max_ch, bool pcm)
 696 {
 697         int i;
 698
 699         if (num == 0)
 700                 return 0;
 701
 702          /* TODO: Read supported rates/formats from hardware */
 703         for (i = off; i < (off + num); i++) {
 704                 dais[i].name = kasprintf(GFP_KERNEL, "SDW%d Pin%d",
 705                                          cdns->instance, i);
 706                 if (!dais[i].name)
 707                         return -ENOMEM;
 708
 709                 if (type == INTEL_PDI_BD || type == INTEL_PDI_OUT) {
 710                         dais[i].playback.stream_name =
 711                                 kasprintf(GFP_KERNEL, "SDW%d Tx%d",
 712                                           cdns->instance, i);
 713                         if (!dais[i].playback.stream_name) {
 714                                 kfree(dais[i].name);
 715                                 return -ENOMEM;
 716                         }
 717
 718                         dais[i].playback.channels_min = 1;
 719                         dais[i].playback.channels_max = max_ch;
 720                         dais[i].playback.rates = SNDRV_PCM_RATE_48000;
 721                         dais[i].playback.formats = SNDRV_PCM_FMTBIT_S16_LE;
 722                 }
 723
 724                 if (type == INTEL_PDI_BD || type == INTEL_PDI_IN) {
 725                         dais[i].capture.stream_name =
 726                                 kasprintf(GFP_KERNEL, "SDW%d Rx%d",
 727                                           cdns->instance, i);
 728                         if (!dais[i].capture.stream_name) {
 729                                 kfree(dais[i].name);
 730                                 kfree(dais[i].playback.stream_name);
 731                                 return -ENOMEM;
 732                         }
 733
 734                         dais[i].capture.channels_min = 1;
 735                         dais[i].capture.channels_max = max_ch;
 736                         dais[i].capture.rates = SNDRV_PCM_RATE_48000;
 737                         dais[i].capture.formats = SNDRV_PCM_FMTBIT_S16_LE;
 738                 }
 739
 740                 dais[i].id = SDW_DAI_ID_RANGE_START + i;
 741
 742                 if (pcm)
 743                         dais[i].ops = &intel_pcm_dai_ops;
 744                 else
 745                         dais[i].ops = &intel_pdm_dai_ops;
 746         }
 747
 748         return 0;
 749 }
 750
 751 static int intel_register_dai(struct sdw_intel *sdw)
 752 {
 753         struct sdw_cdns *cdns = &sdw->cdns;
 754         struct sdw_cdns_streams *stream;
 755         struct snd_soc_dai_driver *dais;
 756         int num_dai, ret, off = 0;
 757
 758         /* DAIs are created based on total number of PDIs supported */
 759         num_dai = cdns->pcm.num_pdi + cdns->pdm.num_pdi;
 760
 761         dais = devm_kcalloc(cdns->dev, num_dai, sizeof(*dais), GFP_KERNEL);
 762         if (!dais)
 763                 return -ENOMEM;
 764
 765         /* Create PCM DAIs */
 766         stream = &cdns->pcm;
 767
 768         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, stream->num_in,
 769                                off, stream->num_ch_in, true);
 770         if (ret)
 771                 return ret;
 772
 773         off += cdns->pcm.num_in;
 774         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pcm.num_out,
 775                                off, stream->num_ch_out, true);
 776         if (ret)
 777                 return ret;
 778
 779         off += cdns->pcm.num_out;
 780         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pcm.num_bd,
 781                                off, stream->num_ch_bd, true);
 782         if (ret)
 783                 return ret;
 784
 785         /* Create PDM DAIs */
 786         stream = &cdns->pdm;
 787         off += cdns->pcm.num_bd;
 788         ret = intel_create_dai(cdns, dais, INTEL_PDI_IN, cdns->pdm.num_in,
 789                                off, stream->num_ch_in, false);
 790         if (ret)
 791                 return ret;
 792
 793         off += cdns->pdm.num_in;
 794         ret = intel_create_dai(cdns, dais, INTEL_PDI_OUT, cdns->pdm.num_out,
 795                                off, stream->num_ch_out, false);
 796         if (ret)
 797                 return ret;
 798
 799         off += cdns->pdm.num_bd;
 800         ret = intel_create_dai(cdns, dais, INTEL_PDI_BD, cdns->pdm.num_bd,
 801                                off, stream->num_ch_bd, false);
 802         if (ret)
 803                 return ret;
 804
 805         return snd_soc_register_component(cdns->dev, &dai_component,
 806                                           dais, num_dai);
 807 }
 808
 809 static int intel_prop_read(struct sdw_bus *bus)
 810 {
 811         /* Initialize with default handler to read all DisCo properties */
 812         sdw_master_read_prop(bus);
 813
 814         /* BIOS is not giving some values correctly. So, lets override them */
 815         bus->prop.num_clk_freq = 1;
 816         bus->prop.clk_freq = devm_kcalloc(bus->dev, bus->prop.num_clk_freq,
 817                                           sizeof(*bus->prop.clk_freq),
 818                                           GFP_KERNEL);
 819         if (!bus->prop.clk_freq)
 820                 return -ENOMEM;
 821
 822         bus->prop.clk_freq[0] = bus->prop.max_clk_freq;
 823         bus->prop.err_threshold = 5;
 824
 825         return 0;
 826 }
 827
 828 static struct sdw_master_ops sdw_intel_ops = {
 829         .read_prop = sdw_master_read_prop,
 830         .xfer_msg = cdns_xfer_msg,
 831         .xfer_msg_defer = cdns_xfer_msg_defer,
 832         .reset_page_addr = cdns_reset_page_addr,
 833         .set_bus_conf = cdns_bus_conf,
 834         .pre_bank_switch = intel_pre_bank_switch,
 835         .post_bank_switch = intel_post_bank_switch,
 836 };
 837
 838 /*
 839  * probe and init
 840  */
 841 static int intel_probe(struct platform_device *pdev)
 842 {
 843         struct sdw_cdns_stream_config config;
 844         struct sdw_intel *sdw;
 845         int ret;
 846
 847         sdw = devm_kzalloc(&pdev->dev, sizeof(*sdw), GFP_KERNEL);
 848         if (!sdw)
 849                 return -ENOMEM;
 850
 851         sdw->instance = pdev->id;
 852         sdw->res = dev_get_platdata(&pdev->dev);
 853         sdw->cdns.dev = &pdev->dev;
 854         sdw->cdns.registers = sdw->res->registers;
 855         sdw->cdns.instance = sdw->instance;
 856         sdw->cdns.msg_count = 0;
 857         sdw->cdns.bus.dev = &pdev->dev;
 858         sdw->cdns.bus.link_id = pdev->id;
 859
 860         sdw_cdns_probe(&sdw->cdns);
 861
 862         /* Set property read ops */
 863         sdw_intel_ops.read_prop = intel_prop_read;
 864         sdw->cdns.bus.ops = &sdw_intel_ops;
 865
 866         platform_set_drvdata(pdev, sdw);
 867
 868         ret = sdw_add_bus_master(&sdw->cdns.bus);
 869         if (ret) {
 870                 dev_err(&pdev->dev, "sdw_add_bus_master fail: %d\n", ret);
 871                 goto err_master_reg;
 872         }
 873
 874         /* Initialize shim and controller */
 875         intel_link_power_up(sdw);
 876         intel_shim_init(sdw);
 877
 878         ret = sdw_cdns_init(&sdw->cdns);
 879         if (ret)
 880                 goto err_init;
 881
 882         ret = sdw_cdns_enable_interrupt(&sdw->cdns);
 883
 884         /* Read the PDI config and initialize cadence PDI */
 885         intel_pdi_init(sdw, &config);
 886         ret = sdw_cdns_pdi_init(&sdw->cdns, config);
 887         if (ret)
 888                 goto err_init;
 889
 890         intel_pdi_ch_update(sdw);
 891
 892         /* Acquire IRQ */
 893         ret = request_threaded_irq(sdw->res->irq, sdw_cdns_irq, sdw_cdns_thread,
 894                                    IRQF_SHARED, KBUILD_MODNAME, &sdw->cdns);
 895         if (ret < 0) {
 896                 dev_err(sdw->cdns.dev, "unable to grab IRQ %d, disabling device\n",
 897                         sdw->res->irq);
 898                 goto err_init;
 899         }
 900
 901         /* Register DAIs */
 902         ret = intel_register_dai(sdw);
 903         if (ret) {
 904                 dev_err(sdw->cdns.dev, "DAI registration failed: %d\n", ret);
 905                 snd_soc_unregister_component(sdw->cdns.dev);
 906                 goto err_dai;
 907         }
 908
 909         return 0;
 910
 911 err_dai:
 912         free_irq(sdw->res->irq, sdw);
 913 err_init:
 914         sdw_delete_bus_master(&sdw->cdns.bus);
 915 err_master_reg:
 916         return ret;
 917 }
 918
 919 static int intel_remove(struct platform_device *pdev)
 920 {
 921         struct sdw_intel *sdw;
 922
 923         sdw = platform_get_drvdata(pdev);
 924
 925         free_irq(sdw->res->irq, sdw);
 926         snd_soc_unregister_component(sdw->cdns.dev);
 927         sdw_delete_bus_master(&sdw->cdns.bus);
 928
 929         return 0;
 930 }
 931
 932 static struct platform_driver sdw_intel_drv = {
 933         .probe = intel_probe,
 934         .remove = intel_remove,
 935         .driver = {
 936                 .name = "int-sdw",
 937
 938         },
 939 };
 940
 941 module_platform_driver(sdw_intel_drv);
 942
 943 MODULE_LICENSE("Dual BSD/GPL");
 944 MODULE_ALIAS("platform:int-sdw");
 945 MODULE_DESCRIPTION("Intel Soundwire Master Driver");