1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012 Samsung Electronics
4 * R. Chandrasekar <rcsekar@samsung.com>
7 #include <audio_codec.h>
16 #include <asm/arch/clk.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/sound.h>
20 #include "wm8994_registers.h"
22 /* defines for wm8994 system clock selection */
23 #define SEL_MCLK1 0x00
24 #define SEL_MCLK2 0x08
28 /* fll config to configure fll */
29 struct wm8994_fll_config {
31 int in; /* Input frequency in Hz */
32 int out; /* output frequency in Hz */
35 /* codec private data */
37 enum wm8994_type type; /* codec type of wolfson */
38 int revision; /* Revision */
39 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
40 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
41 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
42 struct wm8994_fll_config fll[2]; /* fll config to configure fll */
46 /* wm 8994 supported sampling rate values */
47 static unsigned int src_rate[] = {
48 8000, 11025, 12000, 16000, 22050, 24000,
49 32000, 44100, 48000, 88200, 96000
52 /* op clock divisions */
53 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
55 /* lr clock frame size ratio */
56 static int fs_ratios[] = {
57 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
60 /* bit clock divisors */
61 static int bclk_divs[] = {
62 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
63 640, 880, 960, 1280, 1760, 1920
67 * Writes value to a device register through i2c
69 * @param priv Private data for driver
70 * @param reg reg number to be write
71 * @param data data to be writen to the above registor
73 * @return int value 1 for change, 0 for no change or negative error code.
75 static int wm8994_i2c_write(struct wm8994_priv *priv, unsigned int reg,
80 val[0] = (unsigned char)((data >> 8) & 0xff);
81 val[1] = (unsigned char)(data & 0xff);
82 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
84 return dm_i2c_write(priv->dev, reg, val, 2);
88 * Read a value from a device register through i2c
90 * @param priv Private data for driver
91 * @param reg reg number to be read
92 * @param data address of read data to be stored
94 * @return int value 0 for success, -1 in case of error.
96 static unsigned int wm8994_i2c_read(struct wm8994_priv *priv, unsigned int reg,
102 ret = dm_i2c_read(priv->dev, reg, val, 1);
104 debug("%s: Error while reading register %#04x\n",
117 * update device register bits through i2c
119 * @param priv Private data for driver
120 * @param reg codec register
121 * @param mask register mask
122 * @param value new value
124 * @return int value 1 if change in the register value,
125 * 0 for no change or negative error code.
127 static int wm8994_bic_or(struct wm8994_priv *priv, unsigned int reg,
128 unsigned short mask, unsigned short value)
130 int change , ret = 0;
131 unsigned short old, new;
133 if (wm8994_i2c_read(priv, reg, &old) != 0)
135 new = (old & ~mask) | (value & mask);
136 change = (old != new) ? 1 : 0;
138 ret = wm8994_i2c_write(priv, reg, new);
146 * Sets i2s set format
148 * @param priv wm8994 information
149 * @param aif_id Interface ID
150 * @param fmt i2S format
152 * @return -1 for error and 0 Success.
154 static int wm8994_set_fmt(struct wm8994_priv *priv, int aif_id, uint fmt)
165 ms_reg = WM8994_AIF1_MASTER_SLAVE;
166 aif_reg = WM8994_AIF1_CONTROL_1;
167 aif_clk = WM8994_AIF1_CLOCKING_1;
170 ms_reg = WM8994_AIF2_MASTER_SLAVE;
171 aif_reg = WM8994_AIF2_CONTROL_1;
172 aif_clk = WM8994_AIF2_CLOCKING_1;
175 debug("%s: Invalid audio interface selection\n", __func__);
179 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
180 case SND_SOC_DAIFMT_CBS_CFS:
182 case SND_SOC_DAIFMT_CBM_CFM:
183 ms = WM8994_AIF1_MSTR;
186 debug("%s: Invalid i2s master selection\n", __func__);
190 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
191 case SND_SOC_DAIFMT_DSP_B:
192 aif |= WM8994_AIF1_LRCLK_INV;
193 case SND_SOC_DAIFMT_DSP_A:
196 case SND_SOC_DAIFMT_I2S:
199 case SND_SOC_DAIFMT_RIGHT_J:
201 case SND_SOC_DAIFMT_LEFT_J:
205 debug("%s: Invalid i2s format selection\n", __func__);
209 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
210 case SND_SOC_DAIFMT_DSP_A:
211 case SND_SOC_DAIFMT_DSP_B:
212 /* frame inversion not valid for DSP modes */
213 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
214 case SND_SOC_DAIFMT_NB_NF:
216 case SND_SOC_DAIFMT_IB_NF:
217 aif |= WM8994_AIF1_BCLK_INV;
220 debug("%s: Invalid i2s frame inverse selection\n",
226 case SND_SOC_DAIFMT_I2S:
227 case SND_SOC_DAIFMT_RIGHT_J:
228 case SND_SOC_DAIFMT_LEFT_J:
229 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
230 case SND_SOC_DAIFMT_NB_NF:
232 case SND_SOC_DAIFMT_IB_IF:
233 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
235 case SND_SOC_DAIFMT_IB_NF:
236 aif |= WM8994_AIF1_BCLK_INV;
238 case SND_SOC_DAIFMT_NB_IF:
239 aif |= WM8994_AIF1_LRCLK_INV;
242 debug("%s: Invalid i2s clock polarity selection\n",
248 debug("%s: Invalid i2s format selection\n", __func__);
252 error = wm8994_bic_or(priv, aif_reg, WM8994_AIF1_BCLK_INV |
253 WM8994_AIF1_LRCLK_INV_MASK |
254 WM8994_AIF1_FMT_MASK, aif);
256 error |= wm8994_bic_or(priv, ms_reg, WM8994_AIF1_MSTR_MASK, ms);
257 error |= wm8994_bic_or(priv, aif_clk, WM8994_AIF1CLK_ENA_MASK,
260 debug("%s: codec register access error\n", __func__);
268 * Sets hw params FOR WM8994
270 * @param priv wm8994 information pointer
271 * @param aif_id Audio interface ID
272 * @param sampling_rate Sampling rate
273 * @param bits_per_sample Bits per sample
274 * @param Channels Channels in the given audio input
276 * @return -1 for error and 0 Success.
278 static int wm8994_hw_params(struct wm8994_priv *priv, int aif_id,
279 uint sampling_rate, uint bits_per_sample,
291 int i, cur_val, best_val, bclk_rate, best;
292 unsigned short reg_data;
297 aif1_reg = WM8994_AIF1_CONTROL_1;
298 aif2_reg = WM8994_AIF1_CONTROL_2;
299 bclk_reg = WM8994_AIF1_BCLK;
300 rate_reg = WM8994_AIF1_RATE;
303 aif1_reg = WM8994_AIF2_CONTROL_1;
304 aif2_reg = WM8994_AIF2_CONTROL_2;
305 bclk_reg = WM8994_AIF2_BCLK;
306 rate_reg = WM8994_AIF2_RATE;
312 bclk_rate = sampling_rate * 32;
313 switch (bits_per_sample) {
333 /* Try to find an appropriate sample rate; look for an exact match. */
334 for (i = 0; i < ARRAY_SIZE(src_rate); i++)
335 if (src_rate[i] == sampling_rate)
338 if (i == ARRAY_SIZE(src_rate)) {
339 debug("%s: Could not get the best matching samplingrate\n",
344 rate_val |= i << WM8994_AIF1_SR_SHIFT;
346 /* AIFCLK/fs ratio; look for a close match in either direction */
348 best_val = abs((fs_ratios[0] * sampling_rate) - priv->aifclk[id]);
350 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
351 cur_val = abs(fs_ratios[i] * sampling_rate - priv->aifclk[id]);
352 if (cur_val >= best_val)
361 * We may not get quite the right frequency if using
362 * approximate clocks so look for the closest match that is
363 * higher than the target (we need to ensure that there enough
364 * BCLKs to clock out the samples).
367 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
368 cur_val = (priv->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
369 if (cur_val < 0) /* BCLK table is sorted */
374 if (i == ARRAY_SIZE(bclk_divs)) {
375 debug("%s: Could not get the best matching bclk division\n",
380 bclk_rate = priv->aifclk[id] * 10 / bclk_divs[best];
381 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
383 if (wm8994_i2c_read(priv, aif1_reg, ®_data) != 0) {
384 debug("%s: AIF1 register read Failed\n", __func__);
388 if ((channels == 1) && ((reg_data & 0x18) == 0x18))
389 aif2 |= WM8994_AIF1_MONO;
391 if (priv->aifclk[id] == 0) {
392 debug("%s:Audio interface clock not set\n", __func__);
396 ret = wm8994_bic_or(priv, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
397 ret |= wm8994_bic_or(priv, aif2_reg, WM8994_AIF1_MONO, aif2);
398 ret |= wm8994_bic_or(priv, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK,
400 ret |= wm8994_bic_or(priv, rate_reg, WM8994_AIF1_SR_MASK |
401 WM8994_AIF1CLK_RATE_MASK, rate_val);
403 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
406 debug("%s: codec register access error\n", __func__);
414 * Configures Audio interface Clock
416 * @param priv wm8994 information pointer
417 * @param aif Audio Interface ID
419 * @return -1 for error and 0 Success.
421 static int configure_aif_clock(struct wm8994_priv *priv, int aif)
428 /* AIF(1/0) register adress offset calculated */
434 switch (priv->sysclk[aif - 1]) {
435 case WM8994_SYSCLK_MCLK1:
437 rate = priv->mclk[0];
440 case WM8994_SYSCLK_MCLK2:
442 rate = priv->mclk[1];
445 case WM8994_SYSCLK_FLL1:
447 rate = priv->fll[0].out;
450 case WM8994_SYSCLK_FLL2:
452 rate = priv->fll[1].out;
456 debug("%s: Invalid input clock selection [%d]\n",
457 __func__, priv->sysclk[aif - 1]);
461 /* if input clock frequenct is more than 135Mhz then divide */
462 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
464 reg1 |= WM8994_AIF1CLK_DIV;
467 priv->aifclk[aif - 1] = rate;
469 ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_1 + offset,
470 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
473 if (aif == WM8994_AIF1)
474 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
475 WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
476 WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
477 else if (aif == WM8994_AIF2)
478 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
479 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
480 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
481 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
484 debug("%s: codec register access error\n", __func__);
492 * Configures Audio interface for the given frequency
494 * @param priv wm8994 information
495 * @param aif_id Audio Interface
496 * @param clk_id Input Clock ID
497 * @param freq Sampling frequency in Hz
499 * @return -1 for error and 0 success.
501 static int wm8994_set_sysclk(struct wm8994_priv *priv, int aif_id, int clk_id,
507 priv->sysclk[aif_id - 1] = clk_id;
510 case WM8994_SYSCLK_MCLK1:
511 priv->mclk[0] = freq;
513 ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_2,
514 WM8994_AIF2DAC_DIV_MASK, 0);
518 case WM8994_SYSCLK_MCLK2:
519 /* TODO: Set GPIO AF */
520 priv->mclk[1] = freq;
523 case WM8994_SYSCLK_FLL1:
524 case WM8994_SYSCLK_FLL2:
527 case WM8994_SYSCLK_OPCLK:
529 * Special case - a division (times 10) is given and
530 * no effect on main clocking.
533 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
534 if (opclk_divs[i] == freq)
536 if (i == ARRAY_SIZE(opclk_divs)) {
537 debug("%s frequency divisor not found\n",
541 ret = wm8994_bic_or(priv, WM8994_CLOCKING_2,
542 WM8994_OPCLK_DIV_MASK, i);
543 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
547 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
548 WM8994_OPCLK_ENA, 0);
552 debug("%s Invalid input clock selection [%d]\n",
557 ret |= configure_aif_clock(priv, aif_id);
560 debug("%s: codec register access error\n", __func__);
568 * Initializes Volume for AIF2 to HP path
570 * @param priv wm8994 information
571 * @returns -1 for error and 0 Success.
574 static int wm8994_init_volume_aif2_dac1(struct wm8994_priv *priv)
579 ret = wm8994_bic_or(priv, WM8994_AIF2_DAC_FILTERS_1,
580 WM8994_AIF2DAC_MUTE_MASK, 0);
583 ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_LEFT_VOLUME,
584 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
585 WM8994_AIF2DAC_VU | 0xff);
587 ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_RIGHT_VOLUME,
588 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
589 WM8994_AIF2DAC_VU | 0xff);
592 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
593 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
594 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
596 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
597 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
598 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
599 /* Head Phone Volume */
600 ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
601 ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
604 debug("%s: codec register access error\n", __func__);
612 * Initializes Volume for AIF1 to HP path
614 * @param priv wm8994 information
615 * @returns -1 for error and 0 Success.
618 static int wm8994_init_volume_aif1_dac1(struct wm8994_priv *priv)
623 ret |= wm8994_i2c_write(priv, WM8994_AIF1_DAC_FILTERS_1, 0x0000);
625 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
626 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
627 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
629 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
630 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
631 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
632 /* Head Phone Volume */
633 ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
634 ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
637 debug("%s: codec register access error\n", __func__);
645 * Intialise wm8994 codec device
647 * @param priv wm8994 information
649 * @returns -1 for error and 0 Success.
651 static int wm8994_device_init(struct wm8994_priv *priv)
654 unsigned short reg_data;
657 wm8994_i2c_write(priv, WM8994_SOFTWARE_RESET, WM8994_SW_RESET);
659 ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, ®_data);
661 debug("Failed to read ID register\n");
665 if (reg_data == WM8994_ID) {
667 debug("Device registered as type %d\n", priv->type);
670 debug("Device is not a WM8994, ID is %x\n", ret);
674 ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, ®_data);
676 debug("Failed to read revision register: %d\n", ret);
679 priv->revision = reg_data;
680 debug("%s revision %c\n", devname, 'A' + priv->revision);
685 static int wm8994_setup_interface(struct wm8994_priv *priv,
686 enum en_audio_interface aif_id)
691 ret = wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
692 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
694 /* Charge Pump Enable */
695 ret |= wm8994_bic_or(priv, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
698 /* Head Phone Power Enable */
699 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
700 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
702 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
703 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
705 if (aif_id == WM8994_AIF1) {
706 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_2,
707 WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
708 WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
711 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_4,
712 WM8994_ADCL_ENA | WM8994_ADCR_ENA |
713 WM8994_AIF1ADC1R_ENA |
714 WM8994_AIF1ADC1L_ENA);
716 /* Power enable for AIF1 and DAC1 */
717 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_5,
718 WM8994_AIF1DACL_ENA |
719 WM8994_AIF1DACR_ENA |
720 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
721 } else if (aif_id == WM8994_AIF2) {
722 /* Power enable for AIF2 and DAC1 */
723 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_5,
724 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
725 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
726 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
727 WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
729 /* Head Phone Initialisation */
730 ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
731 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
732 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
734 ret |= wm8994_bic_or(priv, WM8994_DC_SERVO_1,
735 WM8994_DCS_ENA_CHAN_0_MASK |
736 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
737 WM8994_DCS_ENA_CHAN_1);
739 ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
740 WM8994_HPOUT1L_DLY_MASK |
741 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
742 WM8994_HPOUT1R_OUTP_MASK |
743 WM8994_HPOUT1L_RMV_SHORT_MASK |
744 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
745 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
746 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
747 WM8994_HPOUT1R_RMV_SHORT);
749 /* MIXER Config DAC1 to HP */
750 ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_1,
751 WM8994_DAC1L_TO_HPOUT1L_MASK,
752 WM8994_DAC1L_TO_HPOUT1L);
754 ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_2,
755 WM8994_DAC1R_TO_HPOUT1R_MASK,
756 WM8994_DAC1R_TO_HPOUT1R);
758 if (aif_id == WM8994_AIF1) {
759 /* Routing AIF1 to DAC1 */
760 ret |= wm8994_i2c_write(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
761 WM8994_AIF1DAC1L_TO_DAC1L);
763 ret |= wm8994_i2c_write(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
764 WM8994_AIF1DAC1R_TO_DAC1R);
766 /* GPIO Settings for AIF1 */
767 ret |= wm8994_i2c_write(priv, WM8994_GPIO_1,
768 WM8994_GPIO_DIR_OUTPUT |
769 WM8994_GPIO_FUNCTION_I2S_CLK |
770 WM8994_GPIO_INPUT_DEBOUNCE);
772 ret |= wm8994_init_volume_aif1_dac1(priv);
773 } else if (aif_id == WM8994_AIF2) {
774 /* Routing AIF2 to DAC1 */
775 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
776 WM8994_AIF2DACL_TO_DAC1L_MASK,
777 WM8994_AIF2DACL_TO_DAC1L);
779 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
780 WM8994_AIF2DACR_TO_DAC1R_MASK,
781 WM8994_AIF2DACR_TO_DAC1R);
783 /* GPIO Settings for AIF2 */
785 ret |= wm8994_bic_or(priv, WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
786 WM8994_GPIO_FUNCTION_MASK,
787 WM8994_GPIO_DIR_OUTPUT);
790 ret |= wm8994_bic_or(priv, WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
791 WM8994_GPIO_FUNCTION_MASK,
792 WM8994_GPIO_DIR_OUTPUT);
795 ret |= wm8994_bic_or(priv, WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
796 WM8994_GPIO_FUNCTION_MASK,
797 WM8994_GPIO_DIR_OUTPUT);
799 ret |= wm8994_init_volume_aif2_dac1(priv);
805 debug("%s: Codec chip setup ok\n", __func__);
808 debug("%s: Codec chip setup error\n", __func__);
812 static int _wm8994_init(struct wm8994_priv *priv,
813 enum en_audio_interface aif_id, int sampling_rate,
814 int mclk_freq, int bits_per_sample,
815 unsigned int channels)
819 ret = wm8994_setup_interface(priv, aif_id);
821 debug("%s: wm8994 codec chip init failed\n", __func__);
825 ret = wm8994_set_sysclk(priv, aif_id, WM8994_SYSCLK_MCLK1, mclk_freq);
827 debug("%s: wm8994 codec set sys clock failed\n", __func__);
831 ret = wm8994_hw_params(priv, aif_id, sampling_rate, bits_per_sample,
835 ret = wm8994_set_fmt(priv, aif_id, SND_SOC_DAIFMT_I2S |
836 SND_SOC_DAIFMT_NB_NF |
837 SND_SOC_DAIFMT_CBS_CFS);
843 static int wm8994_set_params(struct udevice *dev, int interface, int rate,
844 int mclk_freq, int bits_per_sample, uint channels)
846 struct wm8994_priv *priv = dev_get_priv(dev);
848 return _wm8994_init(priv, interface, rate, mclk_freq, bits_per_sample,
852 static int wm8994_probe(struct udevice *dev)
854 struct wm8994_priv *priv = dev_get_priv(dev);
857 return wm8994_device_init(priv);
860 static const struct audio_codec_ops wm8994_ops = {
861 .set_params = wm8994_set_params,
864 static const struct udevice_id wm8994_ids[] = {
865 { .compatible = "wolfson,wm8994" },
869 U_BOOT_DRIVER(wm8994) = {
871 .id = UCLASS_AUDIO_CODEC,
872 .of_match = wm8994_ids,
873 .probe = wm8994_probe,
875 .priv_auto_alloc_size = sizeof(struct wm8994_priv),