2 * Copyright (C) 2012 Samsung Electronics
3 * R. Chandrasekar <rcsekar@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <asm/arch/clk.h>
24 #include <asm/arch/cpu.h>
33 #include <asm/arch/sound.h>
35 #include "wm8994_registers.h"
37 /* defines for wm8994 system clock selection */
38 #define SEL_MCLK1 0x00
39 #define SEL_MCLK2 0x08
43 /* fll config to configure fll */
44 struct wm8994_fll_config {
46 int in; /* Input frequency in Hz */
47 int out; /* output frequency in Hz */
50 /* codec private data */
52 enum wm8994_type type; /* codec type of wolfson */
53 int revision; /* Revision */
54 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
55 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
56 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
57 struct wm8994_fll_config fll[2]; /* fll config to configure fll */
60 /* wm 8994 supported sampling rate values */
61 static unsigned int src_rate[] = {
62 8000, 11025, 12000, 16000, 22050, 24000,
63 32000, 44100, 48000, 88200, 96000
66 /* op clock divisions */
67 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
69 /* lr clock frame size ratio */
70 static int fs_ratios[] = {
71 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
74 /* bit clock divisors */
75 static int bclk_divs[] = {
76 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
77 640, 880, 960, 1280, 1760, 1920
80 static struct wm8994_priv g_wm8994_info;
81 static unsigned char g_wm8994_i2c_dev_addr;
82 static struct sound_codec_info g_codec_info;
85 * Initialise I2C for wm 8994
87 * @param bus no i2c bus number in which wm8994 is connected
89 static void wm8994_i2c_init(int bus_no)
91 i2c_set_bus_num(bus_no);
95 * Writes value to a device register through i2c
97 * @param reg reg number to be write
98 * @param data data to be writen to the above registor
100 * @return int value 1 for change, 0 for no change or negative error code.
102 static int wm8994_i2c_write(unsigned int reg, unsigned short data)
104 unsigned char val[2];
106 val[0] = (unsigned char)((data >> 8) & 0xff);
107 val[1] = (unsigned char)(data & 0xff);
108 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
110 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
114 * Read a value from a device register through i2c
116 * @param reg reg number to be read
117 * @param data address of read data to be stored
119 * @return int value 0 for success, -1 in case of error.
121 static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data)
123 unsigned char val[2];
126 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
128 debug("%s: Error while reading register %#04x\n",
141 * update device register bits through i2c
143 * @param reg codec register
144 * @param mask register mask
145 * @param value new value
147 * @return int value 1 if change in the register value,
148 * 0 for no change or negative error code.
150 static int wm8994_update_bits(unsigned int reg, unsigned short mask,
151 unsigned short value)
153 int change , ret = 0;
154 unsigned short old, new;
156 if (wm8994_i2c_read(reg, &old) != 0)
158 new = (old & ~mask) | (value & mask);
159 change = (old != new) ? 1 : 0;
161 ret = wm8994_i2c_write(reg, new);
169 * Sets i2s set format
171 * @param aif_id Interface ID
172 * @param fmt i2S format
174 * @return -1 for error and 0 Success.
176 int wm8994_set_fmt(int aif_id, unsigned int fmt)
187 ms_reg = WM8994_AIF1_MASTER_SLAVE;
188 aif_reg = WM8994_AIF1_CONTROL_1;
189 aif_clk = WM8994_AIF1_CLOCKING_1;
192 ms_reg = WM8994_AIF2_MASTER_SLAVE;
193 aif_reg = WM8994_AIF2_CONTROL_1;
194 aif_clk = WM8994_AIF2_CLOCKING_1;
197 debug("%s: Invalid audio interface selection\n", __func__);
201 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
202 case SND_SOC_DAIFMT_CBS_CFS:
204 case SND_SOC_DAIFMT_CBM_CFM:
205 ms = WM8994_AIF1_MSTR;
208 debug("%s: Invalid i2s master selection\n", __func__);
212 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
213 case SND_SOC_DAIFMT_DSP_B:
214 aif |= WM8994_AIF1_LRCLK_INV;
215 case SND_SOC_DAIFMT_DSP_A:
218 case SND_SOC_DAIFMT_I2S:
221 case SND_SOC_DAIFMT_RIGHT_J:
223 case SND_SOC_DAIFMT_LEFT_J:
227 debug("%s: Invalid i2s format selection\n", __func__);
231 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
232 case SND_SOC_DAIFMT_DSP_A:
233 case SND_SOC_DAIFMT_DSP_B:
234 /* frame inversion not valid for DSP modes */
235 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
236 case SND_SOC_DAIFMT_NB_NF:
238 case SND_SOC_DAIFMT_IB_NF:
239 aif |= WM8994_AIF1_BCLK_INV;
242 debug("%s: Invalid i2s frame inverse selection\n",
248 case SND_SOC_DAIFMT_I2S:
249 case SND_SOC_DAIFMT_RIGHT_J:
250 case SND_SOC_DAIFMT_LEFT_J:
251 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
252 case SND_SOC_DAIFMT_NB_NF:
254 case SND_SOC_DAIFMT_IB_IF:
255 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
257 case SND_SOC_DAIFMT_IB_NF:
258 aif |= WM8994_AIF1_BCLK_INV;
260 case SND_SOC_DAIFMT_NB_IF:
261 aif |= WM8994_AIF1_LRCLK_INV;
264 debug("%s: Invalid i2s clock polarity selection\n",
270 debug("%s: Invalid i2s format selection\n", __func__);
274 error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV |
275 WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif);
277 error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms);
278 error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK,
281 debug("%s: codec register access error\n", __func__);
289 * Sets hw params FOR WM8994
291 * @param wm8994 wm8994 information pointer
292 * @param aif_id Audio interface ID
293 * @param sampling_rate Sampling rate
294 * @param bits_per_sample Bits per sample
295 * @param Channels Channels in the given audio input
297 * @return -1 for error and 0 Success.
299 static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id,
300 unsigned int sampling_rate, unsigned int bits_per_sample,
301 unsigned int channels)
312 int i, cur_val, best_val, bclk_rate, best;
313 unsigned short reg_data;
318 aif1_reg = WM8994_AIF1_CONTROL_1;
319 aif2_reg = WM8994_AIF1_CONTROL_2;
320 bclk_reg = WM8994_AIF1_BCLK;
321 rate_reg = WM8994_AIF1_RATE;
324 aif1_reg = WM8994_AIF2_CONTROL_1;
325 aif2_reg = WM8994_AIF2_CONTROL_2;
326 bclk_reg = WM8994_AIF2_BCLK;
327 rate_reg = WM8994_AIF2_RATE;
333 bclk_rate = sampling_rate * 32;
334 switch (bits_per_sample) {
354 /* Try to find an appropriate sample rate; look for an exact match. */
355 for (i = 0; i < ARRAY_SIZE(src_rate); i++)
356 if (src_rate[i] == sampling_rate)
359 if (i == ARRAY_SIZE(src_rate)) {
360 debug("%s: Could not get the best matching samplingrate\n",
365 rate_val |= i << WM8994_AIF1_SR_SHIFT;
367 /* AIFCLK/fs ratio; look for a close match in either direction */
369 best_val = abs((fs_ratios[0] * sampling_rate)
370 - wm8994->aifclk[id]);
372 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
373 cur_val = abs((fs_ratios[i] * sampling_rate)
374 - wm8994->aifclk[id]);
375 if (cur_val >= best_val)
384 * We may not get quite the right frequency if using
385 * approximate clocks so look for the closest match that is
386 * higher than the target (we need to ensure that there enough
387 * BCLKs to clock out the samples).
390 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
391 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
392 if (cur_val < 0) /* BCLK table is sorted */
397 if (i == ARRAY_SIZE(bclk_divs)) {
398 debug("%s: Could not get the best matching bclk division\n",
403 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
404 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
406 if (wm8994_i2c_read(aif1_reg, ®_data) != 0) {
407 debug("%s: AIF1 register read Failed\n", __func__);
411 if ((channels == 1) && ((reg_data & 0x18) == 0x18))
412 aif2 |= WM8994_AIF1_MONO;
414 if (wm8994->aifclk[id] == 0) {
415 debug("%s:Audio interface clock not set\n", __func__);
419 ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1);
420 ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2);
421 ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
422 ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK |
423 WM8994_AIF1CLK_RATE_MASK, rate_val);
425 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
428 debug("%s: codec register access error\n", __func__);
436 * Configures Audio interface Clock
438 * @param wm8994 wm8994 information pointer
439 * @param aif Audio Interface ID
441 * @return -1 for error and 0 Success.
443 static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
450 /* AIF(1/0) register adress offset calculated */
456 switch (wm8994->sysclk[aif]) {
457 case WM8994_SYSCLK_MCLK1:
459 rate = wm8994->mclk[0];
462 case WM8994_SYSCLK_MCLK2:
464 rate = wm8994->mclk[1];
467 case WM8994_SYSCLK_FLL1:
469 rate = wm8994->fll[0].out;
472 case WM8994_SYSCLK_FLL2:
474 rate = wm8994->fll[1].out;
478 debug("%s: Invalid input clock selection [%d]\n",
479 __func__, wm8994->sysclk[aif]);
483 /* if input clock frequenct is more than 135Mhz then divide */
484 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
486 reg1 |= WM8994_AIF1CLK_DIV;
489 wm8994->aifclk[aif] = rate;
491 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
492 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
495 ret |= wm8994_update_bits(WM8994_CLOCKING_1,
496 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
497 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
498 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
501 debug("%s: codec register access error\n", __func__);
509 * Configures Audio interface for the given frequency
511 * @param wm8994 wm8994 information
512 * @param aif_id Audio Interface
513 * @param clk_id Input Clock ID
514 * @param freq Sampling frequency in Hz
516 * @return -1 for error and 0 success.
518 static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
519 int clk_id, unsigned int freq)
524 wm8994->sysclk[aif_id - 1] = clk_id;
527 case WM8994_SYSCLK_MCLK1:
528 wm8994->mclk[0] = freq;
530 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 ,
531 WM8994_AIF2DAC_DIV_MASK , 0);
535 case WM8994_SYSCLK_MCLK2:
536 /* TODO: Set GPIO AF */
537 wm8994->mclk[1] = freq;
540 case WM8994_SYSCLK_FLL1:
541 case WM8994_SYSCLK_FLL2:
544 case WM8994_SYSCLK_OPCLK:
546 * Special case - a division (times 10) is given and
547 * no effect on main clocking.
550 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
551 if (opclk_divs[i] == freq)
553 if (i == ARRAY_SIZE(opclk_divs)) {
554 debug("%s frequency divisor not found\n",
558 ret = wm8994_update_bits(WM8994_CLOCKING_2,
559 WM8994_OPCLK_DIV_MASK, i);
560 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
561 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
563 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
564 WM8994_OPCLK_ENA, 0);
568 debug("%s Invalid input clock selection [%d]\n",
573 ret |= configure_aif_clock(wm8994, aif_id - 1);
576 debug("%s: codec register access error\n", __func__);
584 * Initializes Volume for AIF2 to HP path
586 * @returns -1 for error and 0 Success.
589 static int wm8994_init_volume_aif2_dac1(void)
594 ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1,
595 WM8994_AIF2DAC_MUTE_MASK, 0);
598 ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME,
599 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
600 WM8994_AIF2DAC_VU | 0xff);
602 ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME,
603 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
604 WM8994_AIF2DAC_VU | 0xff);
607 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
608 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
609 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
611 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
612 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
613 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
614 /* Head Phone Volume */
615 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
616 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
619 debug("%s: codec register access error\n", __func__);
627 * Intialise wm8994 codec device
629 * @param wm8994 wm8994 information
631 * @returns -1 for error and 0 Success.
633 static int wm8994_device_init(struct wm8994_priv *wm8994)
636 unsigned short reg_data;
639 wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */
641 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data);
643 debug("Failed to read ID register\n");
647 if (reg_data == WM8994_ID) {
649 debug("Device registered as type %d\n", wm8994->type);
650 wm8994->type = WM8994;
652 debug("Device is not a WM8994, ID is %x\n", ret);
657 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data);
659 debug("Failed to read revision register: %d\n", ret);
662 wm8994->revision = reg_data;
663 debug("%s revision %c\n", devname, 'A' + wm8994->revision);
666 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
667 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
669 /* Charge Pump Enable */
670 ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
673 /* Head Phone Power Enable */
674 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
675 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
677 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
678 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
680 /* Power enable for AIF2 and DAC1 */
681 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
682 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
683 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
684 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
687 /* Head Phone Initialisation */
688 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
689 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
690 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
692 ret |= wm8994_update_bits(WM8994_DC_SERVO_1,
693 WM8994_DCS_ENA_CHAN_0_MASK |
694 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
695 WM8994_DCS_ENA_CHAN_1);
697 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
698 WM8994_HPOUT1L_DLY_MASK |
699 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
700 WM8994_HPOUT1R_OUTP_MASK |
701 WM8994_HPOUT1L_RMV_SHORT_MASK |
702 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
703 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
704 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
705 WM8994_HPOUT1R_RMV_SHORT);
707 /* MIXER Config DAC1 to HP */
708 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1,
709 WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L);
711 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
712 WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
714 /* Routing AIF2 to DAC1 */
715 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
716 WM8994_AIF2DACL_TO_DAC1L_MASK,
717 WM8994_AIF2DACL_TO_DAC1L);
719 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
720 WM8994_AIF2DACR_TO_DAC1R_MASK,
721 WM8994_AIF2DACR_TO_DAC1R);
723 /* GPIO Settings for AIF2 */
725 ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
726 WM8994_GPIO_FUNCTION_MASK ,
727 WM8994_GPIO_DIR_OUTPUT |
728 WM8994_GPIO_FUNCTION_I2S_CLK);
731 ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
732 WM8994_GPIO_FUNCTION_MASK,
733 WM8994_GPIO_DIR_OUTPUT |
734 WM8994_GPIO_FUNCTION_I2S_CLK);
737 ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
738 WM8994_GPIO_FUNCTION_MASK,
739 WM8994_GPIO_DIR_OUTPUT |
740 WM8994_GPIO_FUNCTION_I2S_CLK);
742 ret |= wm8994_init_volume_aif2_dac1();
746 debug("%s: Codec chip init ok\n", __func__);
749 debug("%s: Codec chip init error\n", __func__);
754 * Gets fdt values for wm8994 config parameters
756 * @param pcodec_info codec information structure
757 * @param blob FDT blob
758 * @return int value, 0 for success
760 static int get_codec_values(struct sound_codec_info *pcodec_info,
764 #ifdef CONFIG_OF_CONTROL
765 enum fdt_compat_id compat;
769 /* Get the node from FDT for codec */
770 node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
772 debug("EXYNOS_SOUND: No node for codec in device tree\n");
773 debug("node = %d\n", node);
777 parent = fdt_parent_offset(blob, node);
779 debug("%s: Cannot find node parent\n", __func__);
783 compat = fdtdec_lookup(blob, parent);
785 case COMPAT_SAMSUNG_S3C2440_I2C:
786 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
787 error |= pcodec_info->i2c_bus;
788 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
789 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
791 error |= pcodec_info->i2c_dev_addr;
792 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
795 debug("%s: Unknown compat id %d\n", __func__, compat);
799 pcodec_info->i2c_bus = AUDIO_I2C_BUS;
800 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
801 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
804 pcodec_info->codec_type = CODEC_WM_8994;
807 debug("fail to get wm8994 codec node properties\n");
814 /*wm8994 Device Initialisation */
815 int wm8994_init(const void *blob, enum en_audio_interface aif_id,
816 int sampling_rate, int mclk_freq,
817 int bits_per_sample, unsigned int channels)
820 struct sound_codec_info *pcodec_info = &g_codec_info;
822 /* Get the codec Values */
823 if (get_codec_values(pcodec_info, blob) < 0) {
824 debug("FDT Codec values failed\n");
828 /* shift the device address by 1 for 7 bit addressing */
829 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
830 wm8994_i2c_init(pcodec_info->i2c_bus);
832 if (pcodec_info->codec_type == CODEC_WM_8994)
833 g_wm8994_info.type = WM8994;
835 debug("%s: Codec id [%d] not defined\n", __func__,
836 pcodec_info->codec_type);
840 ret = wm8994_device_init(&g_wm8994_info);
842 debug("%s: wm8994 codec chip init failed\n", __func__);
846 ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1,
849 debug("%s: wm8994 codec set sys clock failed\n", __func__);
853 ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate,
854 bits_per_sample, channels);
857 ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S |
858 SND_SOC_DAIFMT_NB_NF |
859 SND_SOC_DAIFMT_CBS_CFS);