2 * Copyright (C) 2012 Samsung Electronics
3 * R. Chandrasekar <rcsekar@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 #include <asm/arch/clk.h>
8 #include <asm/arch/cpu.h>
17 #include <asm/arch/sound.h>
19 #include "wm8994_registers.h"
21 /* defines for wm8994 system clock selection */
22 #define SEL_MCLK1 0x00
23 #define SEL_MCLK2 0x08
27 /* fll config to configure fll */
28 struct wm8994_fll_config {
30 int in; /* Input frequency in Hz */
31 int out; /* output frequency in Hz */
34 /* codec private data */
36 enum wm8994_type type; /* codec type of wolfson */
37 int revision; /* Revision */
38 int sysclk[WM8994_MAX_AIF]; /* System clock frequency in Hz */
39 int mclk[WM8994_MAX_AIF]; /* master clock frequency in Hz */
40 int aifclk[WM8994_MAX_AIF]; /* audio interface clock in Hz */
41 struct wm8994_fll_config fll[2]; /* fll config to configure fll */
44 /* wm 8994 supported sampling rate values */
45 static unsigned int src_rate[] = {
46 8000, 11025, 12000, 16000, 22050, 24000,
47 32000, 44100, 48000, 88200, 96000
50 /* op clock divisions */
51 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
53 /* lr clock frame size ratio */
54 static int fs_ratios[] = {
55 64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
58 /* bit clock divisors */
59 static int bclk_divs[] = {
60 10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
61 640, 880, 960, 1280, 1760, 1920
64 static struct wm8994_priv g_wm8994_info;
65 static unsigned char g_wm8994_i2c_dev_addr;
66 static struct sound_codec_info g_codec_info;
69 * Initialise I2C for wm 8994
71 * @param bus no i2c bus number in which wm8994 is connected
73 static void wm8994_i2c_init(int bus_no)
75 i2c_set_bus_num(bus_no);
79 * Writes value to a device register through i2c
81 * @param reg reg number to be write
82 * @param data data to be writen to the above registor
84 * @return int value 1 for change, 0 for no change or negative error code.
86 static int wm8994_i2c_write(unsigned int reg, unsigned short data)
90 val[0] = (unsigned char)((data >> 8) & 0xff);
91 val[1] = (unsigned char)(data & 0xff);
92 debug("Write Addr : 0x%04X, Data : 0x%04X\n", reg, data);
94 return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
98 * Read a value from a device register through i2c
100 * @param reg reg number to be read
101 * @param data address of read data to be stored
103 * @return int value 0 for success, -1 in case of error.
105 static unsigned int wm8994_i2c_read(unsigned int reg , unsigned short *data)
107 unsigned char val[2];
110 ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
112 debug("%s: Error while reading register %#04x\n",
125 * update device register bits through i2c
127 * @param reg codec register
128 * @param mask register mask
129 * @param value new value
131 * @return int value 1 if change in the register value,
132 * 0 for no change or negative error code.
134 static int wm8994_update_bits(unsigned int reg, unsigned short mask,
135 unsigned short value)
137 int change , ret = 0;
138 unsigned short old, new;
140 if (wm8994_i2c_read(reg, &old) != 0)
142 new = (old & ~mask) | (value & mask);
143 change = (old != new) ? 1 : 0;
145 ret = wm8994_i2c_write(reg, new);
153 * Sets i2s set format
155 * @param aif_id Interface ID
156 * @param fmt i2S format
158 * @return -1 for error and 0 Success.
160 int wm8994_set_fmt(int aif_id, unsigned int fmt)
171 ms_reg = WM8994_AIF1_MASTER_SLAVE;
172 aif_reg = WM8994_AIF1_CONTROL_1;
173 aif_clk = WM8994_AIF1_CLOCKING_1;
176 ms_reg = WM8994_AIF2_MASTER_SLAVE;
177 aif_reg = WM8994_AIF2_CONTROL_1;
178 aif_clk = WM8994_AIF2_CLOCKING_1;
181 debug("%s: Invalid audio interface selection\n", __func__);
185 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
186 case SND_SOC_DAIFMT_CBS_CFS:
188 case SND_SOC_DAIFMT_CBM_CFM:
189 ms = WM8994_AIF1_MSTR;
192 debug("%s: Invalid i2s master selection\n", __func__);
196 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
197 case SND_SOC_DAIFMT_DSP_B:
198 aif |= WM8994_AIF1_LRCLK_INV;
199 case SND_SOC_DAIFMT_DSP_A:
202 case SND_SOC_DAIFMT_I2S:
205 case SND_SOC_DAIFMT_RIGHT_J:
207 case SND_SOC_DAIFMT_LEFT_J:
211 debug("%s: Invalid i2s format selection\n", __func__);
215 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
216 case SND_SOC_DAIFMT_DSP_A:
217 case SND_SOC_DAIFMT_DSP_B:
218 /* frame inversion not valid for DSP modes */
219 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
220 case SND_SOC_DAIFMT_NB_NF:
222 case SND_SOC_DAIFMT_IB_NF:
223 aif |= WM8994_AIF1_BCLK_INV;
226 debug("%s: Invalid i2s frame inverse selection\n",
232 case SND_SOC_DAIFMT_I2S:
233 case SND_SOC_DAIFMT_RIGHT_J:
234 case SND_SOC_DAIFMT_LEFT_J:
235 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
236 case SND_SOC_DAIFMT_NB_NF:
238 case SND_SOC_DAIFMT_IB_IF:
239 aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
241 case SND_SOC_DAIFMT_IB_NF:
242 aif |= WM8994_AIF1_BCLK_INV;
244 case SND_SOC_DAIFMT_NB_IF:
245 aif |= WM8994_AIF1_LRCLK_INV;
248 debug("%s: Invalid i2s clock polarity selection\n",
254 debug("%s: Invalid i2s format selection\n", __func__);
258 error = wm8994_update_bits(aif_reg, WM8994_AIF1_BCLK_INV |
259 WM8994_AIF1_LRCLK_INV_MASK | WM8994_AIF1_FMT_MASK, aif);
261 error |= wm8994_update_bits(ms_reg, WM8994_AIF1_MSTR_MASK, ms);
262 error |= wm8994_update_bits(aif_clk, WM8994_AIF1CLK_ENA_MASK,
265 debug("%s: codec register access error\n", __func__);
273 * Sets hw params FOR WM8994
275 * @param wm8994 wm8994 information pointer
276 * @param aif_id Audio interface ID
277 * @param sampling_rate Sampling rate
278 * @param bits_per_sample Bits per sample
279 * @param Channels Channels in the given audio input
281 * @return -1 for error and 0 Success.
283 static int wm8994_hw_params(struct wm8994_priv *wm8994, int aif_id,
284 unsigned int sampling_rate, unsigned int bits_per_sample,
285 unsigned int channels)
296 int i, cur_val, best_val, bclk_rate, best;
297 unsigned short reg_data;
302 aif1_reg = WM8994_AIF1_CONTROL_1;
303 aif2_reg = WM8994_AIF1_CONTROL_2;
304 bclk_reg = WM8994_AIF1_BCLK;
305 rate_reg = WM8994_AIF1_RATE;
308 aif1_reg = WM8994_AIF2_CONTROL_1;
309 aif2_reg = WM8994_AIF2_CONTROL_2;
310 bclk_reg = WM8994_AIF2_BCLK;
311 rate_reg = WM8994_AIF2_RATE;
317 bclk_rate = sampling_rate * 32;
318 switch (bits_per_sample) {
338 /* Try to find an appropriate sample rate; look for an exact match. */
339 for (i = 0; i < ARRAY_SIZE(src_rate); i++)
340 if (src_rate[i] == sampling_rate)
343 if (i == ARRAY_SIZE(src_rate)) {
344 debug("%s: Could not get the best matching samplingrate\n",
349 rate_val |= i << WM8994_AIF1_SR_SHIFT;
351 /* AIFCLK/fs ratio; look for a close match in either direction */
353 best_val = abs((fs_ratios[0] * sampling_rate)
354 - wm8994->aifclk[id]);
356 for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
357 cur_val = abs((fs_ratios[i] * sampling_rate)
358 - wm8994->aifclk[id]);
359 if (cur_val >= best_val)
368 * We may not get quite the right frequency if using
369 * approximate clocks so look for the closest match that is
370 * higher than the target (we need to ensure that there enough
371 * BCLKs to clock out the samples).
374 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
375 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
376 if (cur_val < 0) /* BCLK table is sorted */
381 if (i == ARRAY_SIZE(bclk_divs)) {
382 debug("%s: Could not get the best matching bclk division\n",
387 bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
388 bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
390 if (wm8994_i2c_read(aif1_reg, ®_data) != 0) {
391 debug("%s: AIF1 register read Failed\n", __func__);
395 if ((channels == 1) && ((reg_data & 0x18) == 0x18))
396 aif2 |= WM8994_AIF1_MONO;
398 if (wm8994->aifclk[id] == 0) {
399 debug("%s:Audio interface clock not set\n", __func__);
403 ret = wm8994_update_bits(aif1_reg, WM8994_AIF1_WL_MASK, aif1);
404 ret |= wm8994_update_bits(aif2_reg, WM8994_AIF1_MONO, aif2);
405 ret |= wm8994_update_bits(bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
406 ret |= wm8994_update_bits(rate_reg, WM8994_AIF1_SR_MASK |
407 WM8994_AIF1CLK_RATE_MASK, rate_val);
409 debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
412 debug("%s: codec register access error\n", __func__);
420 * Configures Audio interface Clock
422 * @param wm8994 wm8994 information pointer
423 * @param aif Audio Interface ID
425 * @return -1 for error and 0 Success.
427 static int configure_aif_clock(struct wm8994_priv *wm8994, int aif)
434 /* AIF(1/0) register adress offset calculated */
440 switch (wm8994->sysclk[aif]) {
441 case WM8994_SYSCLK_MCLK1:
443 rate = wm8994->mclk[0];
446 case WM8994_SYSCLK_MCLK2:
448 rate = wm8994->mclk[1];
451 case WM8994_SYSCLK_FLL1:
453 rate = wm8994->fll[0].out;
456 case WM8994_SYSCLK_FLL2:
458 rate = wm8994->fll[1].out;
462 debug("%s: Invalid input clock selection [%d]\n",
463 __func__, wm8994->sysclk[aif]);
467 /* if input clock frequenct is more than 135Mhz then divide */
468 if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
470 reg1 |= WM8994_AIF1CLK_DIV;
473 wm8994->aifclk[aif] = rate;
475 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_1 + offset,
476 WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
479 ret |= wm8994_update_bits(WM8994_CLOCKING_1,
480 WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
481 WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
482 WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
485 debug("%s: codec register access error\n", __func__);
493 * Configures Audio interface for the given frequency
495 * @param wm8994 wm8994 information
496 * @param aif_id Audio Interface
497 * @param clk_id Input Clock ID
498 * @param freq Sampling frequency in Hz
500 * @return -1 for error and 0 success.
502 static int wm8994_set_sysclk(struct wm8994_priv *wm8994, int aif_id,
503 int clk_id, unsigned int freq)
508 wm8994->sysclk[aif_id - 1] = clk_id;
511 case WM8994_SYSCLK_MCLK1:
512 wm8994->mclk[0] = freq;
514 ret = wm8994_update_bits(WM8994_AIF1_CLOCKING_2 ,
515 WM8994_AIF2DAC_DIV_MASK , 0);
519 case WM8994_SYSCLK_MCLK2:
520 /* TODO: Set GPIO AF */
521 wm8994->mclk[1] = freq;
524 case WM8994_SYSCLK_FLL1:
525 case WM8994_SYSCLK_FLL2:
528 case WM8994_SYSCLK_OPCLK:
530 * Special case - a division (times 10) is given and
531 * no effect on main clocking.
534 for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
535 if (opclk_divs[i] == freq)
537 if (i == ARRAY_SIZE(opclk_divs)) {
538 debug("%s frequency divisor not found\n",
542 ret = wm8994_update_bits(WM8994_CLOCKING_2,
543 WM8994_OPCLK_DIV_MASK, i);
544 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
545 WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
547 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_2,
548 WM8994_OPCLK_ENA, 0);
552 debug("%s Invalid input clock selection [%d]\n",
557 ret |= configure_aif_clock(wm8994, aif_id - 1);
560 debug("%s: codec register access error\n", __func__);
568 * Initializes Volume for AIF2 to HP path
570 * @returns -1 for error and 0 Success.
573 static int wm8994_init_volume_aif2_dac1(void)
578 ret = wm8994_update_bits(WM8994_AIF2_DAC_FILTERS_1,
579 WM8994_AIF2DAC_MUTE_MASK, 0);
582 ret |= wm8994_update_bits(WM8994_AIF2_DAC_LEFT_VOLUME,
583 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
584 WM8994_AIF2DAC_VU | 0xff);
586 ret |= wm8994_update_bits(WM8994_AIF2_DAC_RIGHT_VOLUME,
587 WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
588 WM8994_AIF2DAC_VU | 0xff);
591 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_VOLUME,
592 WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
593 WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
595 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_VOLUME,
596 WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
597 WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
598 /* Head Phone Volume */
599 ret |= wm8994_i2c_write(WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
600 ret |= wm8994_i2c_write(WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
603 debug("%s: codec register access error\n", __func__);
611 * Intialise wm8994 codec device
613 * @param wm8994 wm8994 information
615 * @returns -1 for error and 0 Success.
617 static int wm8994_device_init(struct wm8994_priv *wm8994)
620 unsigned short reg_data;
623 wm8994_i2c_write(WM8994_SOFTWARE_RESET, WM8994_SW_RESET);/* Reset */
625 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, ®_data);
627 debug("Failed to read ID register\n");
631 if (reg_data == WM8994_ID) {
633 debug("Device registered as type %d\n", wm8994->type);
634 wm8994->type = WM8994;
636 debug("Device is not a WM8994, ID is %x\n", ret);
641 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, ®_data);
643 debug("Failed to read revision register: %d\n", ret);
646 wm8994->revision = reg_data;
647 debug("%s revision %c\n", devname, 'A' + wm8994->revision);
650 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
651 WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
653 /* Charge Pump Enable */
654 ret |= wm8994_update_bits(WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
657 /* Head Phone Power Enable */
658 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
659 WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
661 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_1,
662 WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
664 /* Power enable for AIF2 and DAC1 */
665 ret |= wm8994_update_bits(WM8994_POWER_MANAGEMENT_5,
666 WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
667 WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
668 WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA | WM8994_DAC1L_ENA |
671 /* Head Phone Initialisation */
672 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
673 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
674 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
676 ret |= wm8994_update_bits(WM8994_DC_SERVO_1,
677 WM8994_DCS_ENA_CHAN_0_MASK |
678 WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
679 WM8994_DCS_ENA_CHAN_1);
681 ret |= wm8994_update_bits(WM8994_ANALOGUE_HP_1,
682 WM8994_HPOUT1L_DLY_MASK |
683 WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
684 WM8994_HPOUT1R_OUTP_MASK |
685 WM8994_HPOUT1L_RMV_SHORT_MASK |
686 WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
687 WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
688 WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
689 WM8994_HPOUT1R_RMV_SHORT);
691 /* MIXER Config DAC1 to HP */
692 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_1,
693 WM8994_DAC1L_TO_HPOUT1L_MASK, WM8994_DAC1L_TO_HPOUT1L);
695 ret |= wm8994_update_bits(WM8994_OUTPUT_MIXER_2,
696 WM8994_DAC1R_TO_HPOUT1R_MASK, WM8994_DAC1R_TO_HPOUT1R);
698 /* Routing AIF2 to DAC1 */
699 ret |= wm8994_update_bits(WM8994_DAC1_LEFT_MIXER_ROUTING,
700 WM8994_AIF2DACL_TO_DAC1L_MASK,
701 WM8994_AIF2DACL_TO_DAC1L);
703 ret |= wm8994_update_bits(WM8994_DAC1_RIGHT_MIXER_ROUTING,
704 WM8994_AIF2DACR_TO_DAC1R_MASK,
705 WM8994_AIF2DACR_TO_DAC1R);
707 /* GPIO Settings for AIF2 */
709 ret |= wm8994_update_bits(WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
710 WM8994_GPIO_FUNCTION_MASK ,
711 WM8994_GPIO_DIR_OUTPUT |
712 WM8994_GPIO_FUNCTION_I2S_CLK);
715 ret |= wm8994_update_bits(WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
716 WM8994_GPIO_FUNCTION_MASK,
717 WM8994_GPIO_DIR_OUTPUT |
718 WM8994_GPIO_FUNCTION_I2S_CLK);
721 ret |= wm8994_update_bits(WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
722 WM8994_GPIO_FUNCTION_MASK,
723 WM8994_GPIO_DIR_OUTPUT |
724 WM8994_GPIO_FUNCTION_I2S_CLK);
726 ret |= wm8994_init_volume_aif2_dac1();
730 debug("%s: Codec chip init ok\n", __func__);
733 debug("%s: Codec chip init error\n", __func__);
738 * Gets fdt values for wm8994 config parameters
740 * @param pcodec_info codec information structure
741 * @param blob FDT blob
742 * @return int value, 0 for success
744 static int get_codec_values(struct sound_codec_info *pcodec_info,
748 #ifdef CONFIG_OF_CONTROL
749 enum fdt_compat_id compat;
753 /* Get the node from FDT for codec */
754 node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
756 debug("EXYNOS_SOUND: No node for codec in device tree\n");
757 debug("node = %d\n", node);
761 parent = fdt_parent_offset(blob, node);
763 debug("%s: Cannot find node parent\n", __func__);
767 compat = fdtdec_lookup(blob, parent);
769 case COMPAT_SAMSUNG_S3C2440_I2C:
770 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
771 error |= pcodec_info->i2c_bus;
772 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
773 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
775 error |= pcodec_info->i2c_dev_addr;
776 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
779 debug("%s: Unknown compat id %d\n", __func__, compat);
783 pcodec_info->i2c_bus = AUDIO_I2C_BUS;
784 pcodec_info->i2c_dev_addr = AUDIO_I2C_REG;
785 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
788 pcodec_info->codec_type = CODEC_WM_8994;
791 debug("fail to get wm8994 codec node properties\n");
798 /*wm8994 Device Initialisation */
799 int wm8994_init(const void *blob, enum en_audio_interface aif_id,
800 int sampling_rate, int mclk_freq,
801 int bits_per_sample, unsigned int channels)
804 struct sound_codec_info *pcodec_info = &g_codec_info;
806 /* Get the codec Values */
807 if (get_codec_values(pcodec_info, blob) < 0) {
808 debug("FDT Codec values failed\n");
812 /* shift the device address by 1 for 7 bit addressing */
813 g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
814 wm8994_i2c_init(pcodec_info->i2c_bus);
816 if (pcodec_info->codec_type == CODEC_WM_8994)
817 g_wm8994_info.type = WM8994;
819 debug("%s: Codec id [%d] not defined\n", __func__,
820 pcodec_info->codec_type);
824 ret = wm8994_device_init(&g_wm8994_info);
826 debug("%s: wm8994 codec chip init failed\n", __func__);
830 ret = wm8994_set_sysclk(&g_wm8994_info, aif_id, WM8994_SYSCLK_MCLK1,
833 debug("%s: wm8994 codec set sys clock failed\n", __func__);
837 ret = wm8994_hw_params(&g_wm8994_info, aif_id, sampling_rate,
838 bits_per_sample, channels);
841 ret = wm8994_set_fmt(aif_id, SND_SOC_DAIFMT_I2S |
842 SND_SOC_DAIFMT_NB_NF |
843 SND_SOC_DAIFMT_CBS_CFS);