drivers/sound/wm8994.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2012 Samsung Electronics
   4  * R. Chandrasekar <rcsekar@samsung.com>
   5  */
   6 #include <common.h>
   7 #include <asm/arch/clk.h>
   8 #include <asm/arch/cpu.h>
   9 #include <asm/gpio.h>
  10 #include <asm/io.h>
  11 #include <div64.h>
  12 #include <fdtdec.h>
  13 #include <i2c.h>
  14 #include <i2s.h>
  15 #include <sound.h>
  16 #include <asm/arch/sound.h>
  17 #include "wm8994.h"
  18 #include "wm8994_registers.h"
  19
  20 /* defines for wm8994 system clock selection */
  21 #define SEL_MCLK1       0x00
  22 #define SEL_MCLK2       0x08
  23 #define SEL_FLL1        0x10
  24 #define SEL_FLL2        0x18
  25
  26 /* fll config to configure fll */
  27 struct wm8994_fll_config {
  28         int src;        /* Source */
  29         int in;         /* Input frequency in Hz */
  30         int out;        /* output frequency in Hz */
  31 };
  32
  33 /* codec private data */
  34 struct wm8994_priv {
  35         enum wm8994_type type;          /* codec type of wolfson */
  36         int revision;                   /* Revision */
  37         int sysclk[WM8994_MAX_AIF];     /* System clock frequency in Hz  */
  38         int mclk[WM8994_MAX_AIF];       /* master clock frequency in Hz */
  39         int aifclk[WM8994_MAX_AIF];     /* audio interface clock in Hz   */
  40         struct wm8994_fll_config fll[2]; /* fll config to configure fll */
  41 };
  42
  43 /* wm 8994 supported sampling rate values */
  44 static unsigned int src_rate[] = {
  45                          8000, 11025, 12000, 16000, 22050, 24000,
  46                          32000, 44100, 48000, 88200, 96000
  47 };
  48
  49 /* op clock divisions */
  50 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
  51
  52 /* lr clock frame size ratio */
  53 static int fs_ratios[] = {
  54         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
  55 };
  56
  57 /* bit clock divisors */
  58 static int bclk_divs[] = {
  59         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
  60         640, 880, 960, 1280, 1760, 1920
  61 };
  62
  63 static struct wm8994_priv g_wm8994_info;
  64 static unsigned char g_wm8994_i2c_dev_addr;
  65 static struct sound_codec_info g_codec_info;
  66
  67 /*
  68  * Initialise I2C for wm 8994
  69  *
  70  * @param bus no        i2c bus number in which wm8994 is connected
  71  */
  72 static void wm8994_i2c_init(int bus_no)
  73 {
  74         i2c_set_bus_num(bus_no);
  75 }
  76
  77 /*
  78  * Writes value to a device register through i2c
  79  *
  80  * @param priv  Private data for driver
  81  * @param reg   reg number to be write
  82  * @param data  data to be writen to the above registor
  83  *
  84  * @return      int value 1 for change, 0 for no change or negative error code.
  85  */
  86 static int wm8994_i2c_write(struct wm8994_priv *priv, unsigned int reg,
  87                             unsigned short data)
  88 {
  89         unsigned char val[2];
  90
  91         val[0] = (unsigned char)((data >> 8) & 0xff);
  92         val[1] = (unsigned char)(data & 0xff);
  93         debug("Write Addr : 0x%04X, Data :  0x%04X\n", reg, data);
  94
  95         return i2c_write(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
  96 }
  97
  98 /*
  99  * Read a value from a device register through i2c
 100  *
 101  * @param priv  Private data for driver
 102  * @param reg   reg number to be read
 103  * @param data  address of read data to be stored
 104  *
 105  * @return      int value 0 for success, -1 in case of error.
 106  */
 107 static unsigned int wm8994_i2c_read(struct wm8994_priv *priv, unsigned int reg,
 108                                     unsigned short *data)
 109 {
 110         unsigned char val[2];
 111         int ret;
 112
 113         ret = i2c_read(g_wm8994_i2c_dev_addr, reg, 2, val, 2);
 114         if (ret != 0) {
 115                 debug("%s: Error while reading register %#04x\n",
 116                       __func__, reg);
 117                 return -1;
 118         }
 119
 120         *data = val[0];
 121         *data <<= 8;
 122         *data |= val[1];
 123
 124         return 0;
 125 }
 126
 127 /*
 128  * update device register bits through i2c
 129  *
 130  * @param priv  Private data for driver
 131  * @param reg   codec register
 132  * @param mask  register mask
 133  * @param value new value
 134  *
 135  * @return int value 1 if change in the register value,
 136  * 0 for no change or negative error code.
 137  */
 138 static int wm8994_bic_or(struct wm8994_priv *priv, unsigned int reg,
 139                          unsigned short mask, unsigned short value)
 140 {
 141         int change , ret = 0;
 142         unsigned short old, new;
 143
 144         if (wm8994_i2c_read(priv, reg, &old) != 0)
 145                 return -1;
 146         new = (old & ~mask) | (value & mask);
 147         change  = (old != new) ? 1 : 0;
 148         if (change)
 149                 ret = wm8994_i2c_write(priv, reg, new);
 150         if (ret < 0)
 151                 return ret;
 152
 153         return change;
 154 }
 155
 156 /*
 157  * Sets i2s set format
 158  *
 159  * @param priv          wm8994 information
 160  * @param aif_id        Interface ID
 161  * @param fmt           i2S format
 162  *
 163  * @return -1 for error and 0  Success.
 164  */
 165 static int wm8994_set_fmt(struct wm8994_priv *priv, int aif_id, uint fmt)
 166 {
 167         int ms_reg;
 168         int aif_reg;
 169         int ms = 0;
 170         int aif = 0;
 171         int aif_clk = 0;
 172         int error = 0;
 173
 174         switch (aif_id) {
 175         case 1:
 176                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
 177                 aif_reg = WM8994_AIF1_CONTROL_1;
 178                 aif_clk = WM8994_AIF1_CLOCKING_1;
 179                 break;
 180         case 2:
 181                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
 182                 aif_reg = WM8994_AIF2_CONTROL_1;
 183                 aif_clk = WM8994_AIF2_CLOCKING_1;
 184                 break;
 185         default:
 186                 debug("%s: Invalid audio interface selection\n", __func__);
 187                 return -1;
 188         }
 189
 190         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 191         case SND_SOC_DAIFMT_CBS_CFS:
 192                 break;
 193         case SND_SOC_DAIFMT_CBM_CFM:
 194                 ms = WM8994_AIF1_MSTR;
 195                 break;
 196         default:
 197                 debug("%s: Invalid i2s master selection\n", __func__);
 198                 return -1;
 199         }
 200
 201         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 202         case SND_SOC_DAIFMT_DSP_B:
 203                 aif |= WM8994_AIF1_LRCLK_INV;
 204         case SND_SOC_DAIFMT_DSP_A:
 205                 aif |= 0x18;
 206                 break;
 207         case SND_SOC_DAIFMT_I2S:
 208                 aif |= 0x10;
 209                 break;
 210         case SND_SOC_DAIFMT_RIGHT_J:
 211                 break;
 212         case SND_SOC_DAIFMT_LEFT_J:
 213                 aif |= 0x8;
 214                 break;
 215         default:
 216                 debug("%s: Invalid i2s format selection\n", __func__);
 217                 return -1;
 218         }
 219
 220         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 221         case SND_SOC_DAIFMT_DSP_A:
 222         case SND_SOC_DAIFMT_DSP_B:
 223                 /* frame inversion not valid for DSP modes */
 224                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 225                 case SND_SOC_DAIFMT_NB_NF:
 226                         break;
 227                 case SND_SOC_DAIFMT_IB_NF:
 228                         aif |= WM8994_AIF1_BCLK_INV;
 229                         break;
 230                 default:
 231                         debug("%s: Invalid i2s frame inverse selection\n",
 232                               __func__);
 233                         return -1;
 234                 }
 235                 break;
 236
 237         case SND_SOC_DAIFMT_I2S:
 238         case SND_SOC_DAIFMT_RIGHT_J:
 239         case SND_SOC_DAIFMT_LEFT_J:
 240                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 241                 case SND_SOC_DAIFMT_NB_NF:
 242                         break;
 243                 case SND_SOC_DAIFMT_IB_IF:
 244                         aif |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
 245                         break;
 246                 case SND_SOC_DAIFMT_IB_NF:
 247                         aif |= WM8994_AIF1_BCLK_INV;
 248                         break;
 249                 case SND_SOC_DAIFMT_NB_IF:
 250                         aif |= WM8994_AIF1_LRCLK_INV;
 251                         break;
 252                 default:
 253                         debug("%s: Invalid i2s clock polarity selection\n",
 254                               __func__);
 255                         return -1;
 256                 }
 257                 break;
 258         default:
 259                 debug("%s: Invalid i2s format selection\n", __func__);
 260                 return -1;
 261         }
 262
 263         error = wm8994_bic_or(priv, aif_reg, WM8994_AIF1_BCLK_INV |
 264                               WM8994_AIF1_LRCLK_INV_MASK |
 265                                WM8994_AIF1_FMT_MASK, aif);
 266
 267         error |= wm8994_bic_or(priv, ms_reg, WM8994_AIF1_MSTR_MASK, ms);
 268         error |= wm8994_bic_or(priv, aif_clk, WM8994_AIF1CLK_ENA_MASK,
 269                                WM8994_AIF1CLK_ENA);
 270         if (error < 0) {
 271                 debug("%s: codec register access error\n", __func__);
 272                 return -1;
 273         }
 274
 275         return 0;
 276 }
 277
 278 /*
 279  * Sets hw params FOR WM8994
 280  *
 281  * @param priv                  wm8994 information pointer
 282  * @param aif_id                Audio interface ID
 283  * @param sampling_rate         Sampling rate
 284  * @param bits_per_sample       Bits per sample
 285  * @param Channels              Channels in the given audio input
 286  *
 287  * @return -1 for error  and 0  Success.
 288  */
 289 static int wm8994_hw_params(struct wm8994_priv *priv, int aif_id,
 290                             uint sampling_rate, uint bits_per_sample,
 291                             uint channels)
 292 {
 293         int aif1_reg;
 294         int aif2_reg;
 295         int bclk_reg;
 296         int bclk = 0;
 297         int rate_reg;
 298         int aif1 = 0;
 299         int aif2 = 0;
 300         int rate_val = 0;
 301         int id = aif_id - 1;
 302         int i, cur_val, best_val, bclk_rate, best;
 303         unsigned short reg_data;
 304         int ret = 0;
 305
 306         switch (aif_id) {
 307         case 1:
 308                 aif1_reg = WM8994_AIF1_CONTROL_1;
 309                 aif2_reg = WM8994_AIF1_CONTROL_2;
 310                 bclk_reg = WM8994_AIF1_BCLK;
 311                 rate_reg = WM8994_AIF1_RATE;
 312                 break;
 313         case 2:
 314                 aif1_reg = WM8994_AIF2_CONTROL_1;
 315                 aif2_reg = WM8994_AIF2_CONTROL_2;
 316                 bclk_reg = WM8994_AIF2_BCLK;
 317                 rate_reg = WM8994_AIF2_RATE;
 318                 break;
 319         default:
 320                 return -1;
 321         }
 322
 323         bclk_rate = sampling_rate * 32;
 324         switch (bits_per_sample) {
 325         case 16:
 326                 bclk_rate *= 16;
 327                 break;
 328         case 20:
 329                 bclk_rate *= 20;
 330                 aif1 |= 0x20;
 331                 break;
 332         case 24:
 333                 bclk_rate *= 24;
 334                 aif1 |= 0x40;
 335                 break;
 336         case 32:
 337                 bclk_rate *= 32;
 338                 aif1 |= 0x60;
 339                 break;
 340         default:
 341                 return -1;
 342         }
 343
 344         /* Try to find an appropriate sample rate; look for an exact match. */
 345         for (i = 0; i < ARRAY_SIZE(src_rate); i++)
 346                 if (src_rate[i] == sampling_rate)
 347                         break;
 348
 349         if (i == ARRAY_SIZE(src_rate)) {
 350                 debug("%s: Could not get the best matching samplingrate\n",
 351                       __func__);
 352                 return -1;
 353         }
 354
 355         rate_val |= i << WM8994_AIF1_SR_SHIFT;
 356
 357         /* AIFCLK/fs ratio; look for a close match in either direction */
 358         best = 0;
 359         best_val = abs((fs_ratios[0] * sampling_rate) - priv->aifclk[id]);
 360
 361         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
 362                 cur_val = abs(fs_ratios[i] * sampling_rate - priv->aifclk[id]);
 363                 if (cur_val >= best_val)
 364                         continue;
 365                 best = i;
 366                 best_val = cur_val;
 367         }
 368
 369         rate_val |= best;
 370
 371         /*
 372          * We may not get quite the right frequency if using
 373          * approximate clocks so look for the closest match that is
 374          * higher than the target (we need to ensure that there enough
 375          * BCLKs to clock out the samples).
 376          */
 377         best = 0;
 378         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
 379                 cur_val = (priv->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
 380                 if (cur_val < 0) /* BCLK table is sorted */
 381                         break;
 382                 best = i;
 383         }
 384
 385         if (i ==  ARRAY_SIZE(bclk_divs)) {
 386                 debug("%s: Could not get the best matching bclk division\n",
 387                       __func__);
 388                 return -1;
 389         }
 390
 391         bclk_rate = priv->aifclk[id] * 10 / bclk_divs[best];
 392         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
 393
 394         if (wm8994_i2c_read(priv, aif1_reg, &reg_data) != 0) {
 395                 debug("%s: AIF1 register read Failed\n", __func__);
 396                 return -1;
 397         }
 398
 399         if ((channels == 1) && ((reg_data & 0x18) == 0x18))
 400                 aif2 |= WM8994_AIF1_MONO;
 401
 402         if (priv->aifclk[id] == 0) {
 403                 debug("%s:Audio interface clock not set\n", __func__);
 404                 return -1;
 405         }
 406
 407         ret = wm8994_bic_or(priv, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
 408         ret |= wm8994_bic_or(priv, aif2_reg, WM8994_AIF1_MONO, aif2);
 409         ret |= wm8994_bic_or(priv, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK,
 410                                   bclk);
 411         ret |= wm8994_bic_or(priv, rate_reg, WM8994_AIF1_SR_MASK |
 412                                   WM8994_AIF1CLK_RATE_MASK, rate_val);
 413
 414         debug("rate vale = %x , bclk val= %x\n", rate_val, bclk);
 415
 416         if (ret < 0) {
 417                 debug("%s: codec register access error\n", __func__);
 418                 return -1;
 419         }
 420
 421         return 0;
 422 }
 423
 424 /*
 425  * Configures Audio interface Clock
 426  *
 427  * @param priv          wm8994 information pointer
 428  * @param aif           Audio Interface ID
 429  *
 430  * @return -1 for error  and 0  Success.
 431  */
 432 static int configure_aif_clock(struct wm8994_priv *priv, int aif)
 433 {
 434         int rate;
 435         int reg1 = 0;
 436         int offset;
 437         int ret;
 438
 439         /* AIF(1/0) register adress offset calculated */
 440         if (aif-1)
 441                 offset = 4;
 442         else
 443                 offset = 0;
 444
 445         switch (priv->sysclk[aif - 1]) {
 446         case WM8994_SYSCLK_MCLK1:
 447                 reg1 |= SEL_MCLK1;
 448                 rate = priv->mclk[0];
 449                 break;
 450
 451         case WM8994_SYSCLK_MCLK2:
 452                 reg1 |= SEL_MCLK2;
 453                 rate = priv->mclk[1];
 454                 break;
 455
 456         case WM8994_SYSCLK_FLL1:
 457                 reg1 |= SEL_FLL1;
 458                 rate = priv->fll[0].out;
 459                 break;
 460
 461         case WM8994_SYSCLK_FLL2:
 462                 reg1 |= SEL_FLL2;
 463                 rate = priv->fll[1].out;
 464                 break;
 465
 466         default:
 467                 debug("%s: Invalid input clock selection [%d]\n",
 468                       __func__, priv->sysclk[aif - 1]);
 469                 return -1;
 470         }
 471
 472         /* if input clock frequenct is more than 135Mhz then divide */
 473         if (rate >= WM8994_MAX_INPUT_CLK_FREQ) {
 474                 rate /= 2;
 475                 reg1 |= WM8994_AIF1CLK_DIV;
 476         }
 477
 478         priv->aifclk[aif - 1] = rate;
 479
 480         ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_1 + offset,
 481                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 482                             reg1);
 483
 484         if (aif == WM8994_AIF1)
 485                 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
 486                         WM8994_AIF1DSPCLK_ENA_MASK | WM8994_SYSDSPCLK_ENA_MASK,
 487                         WM8994_AIF1DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
 488         else if (aif == WM8994_AIF2)
 489                 ret |= wm8994_bic_or(priv, WM8994_CLOCKING_1,
 490                         WM8994_SYSCLK_SRC | WM8994_AIF2DSPCLK_ENA_MASK |
 491                         WM8994_SYSDSPCLK_ENA_MASK, WM8994_SYSCLK_SRC |
 492                         WM8994_AIF2DSPCLK_ENA | WM8994_SYSDSPCLK_ENA);
 493
 494         if (ret < 0) {
 495                 debug("%s: codec register access error\n", __func__);
 496                 return -1;
 497         }
 498
 499         return 0;
 500 }
 501
 502 /*
 503  * Configures Audio interface  for the given frequency
 504  *
 505  * @param priv          wm8994 information
 506  * @param aif_id        Audio Interface
 507  * @param clk_id        Input Clock ID
 508  * @param freq          Sampling frequency in Hz
 509  *
 510  * @return -1 for error and 0 success.
 511  */
 512 static int wm8994_set_sysclk(struct wm8994_priv *priv, int aif_id, int clk_id,
 513                              unsigned int freq)
 514 {
 515         int i;
 516         int ret = 0;
 517
 518         priv->sysclk[aif_id - 1] = clk_id;
 519
 520         switch (clk_id) {
 521         case WM8994_SYSCLK_MCLK1:
 522                 priv->mclk[0] = freq;
 523                 if (aif_id == 2) {
 524                         ret = wm8994_bic_or(priv, WM8994_AIF1_CLOCKING_2,
 525                                             WM8994_AIF2DAC_DIV_MASK, 0);
 526                 }
 527                 break;
 528
 529         case WM8994_SYSCLK_MCLK2:
 530                 /* TODO: Set GPIO AF */
 531                 priv->mclk[1] = freq;
 532                 break;
 533
 534         case WM8994_SYSCLK_FLL1:
 535         case WM8994_SYSCLK_FLL2:
 536                 break;
 537
 538         case WM8994_SYSCLK_OPCLK:
 539                 /*
 540                  * Special case - a division (times 10) is given and
 541                  * no effect on main clocking.
 542                  */
 543                 if (freq) {
 544                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
 545                                 if (opclk_divs[i] == freq)
 546                                         break;
 547                         if (i == ARRAY_SIZE(opclk_divs)) {
 548                                 debug("%s frequency divisor not found\n",
 549                                       __func__);
 550                                 return -1;
 551                         }
 552                         ret = wm8994_bic_or(priv, WM8994_CLOCKING_2,
 553                                             WM8994_OPCLK_DIV_MASK, i);
 554                         ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
 555                                              WM8994_OPCLK_ENA,
 556                                              WM8994_OPCLK_ENA);
 557                 } else {
 558                         ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_2,
 559                                              WM8994_OPCLK_ENA, 0);
 560                 }
 561
 562         default:
 563                 debug("%s Invalid input clock selection [%d]\n",
 564                       __func__, clk_id);
 565                 return -1;
 566         }
 567
 568         ret |= configure_aif_clock(priv, aif_id);
 569
 570         if (ret < 0) {
 571                 debug("%s: codec register access error\n", __func__);
 572                 return -1;
 573         }
 574
 575         return 0;
 576 }
 577
 578 /*
 579  * Initializes Volume for AIF2 to HP path
 580  *
 581  * @param priv          wm8994 information
 582  * @returns -1 for error  and 0 Success.
 583  *
 584  */
 585 static int wm8994_init_volume_aif2_dac1(struct wm8994_priv *priv)
 586 {
 587         int ret;
 588
 589         /* Unmute AIF2DAC */
 590         ret = wm8994_bic_or(priv, WM8994_AIF2_DAC_FILTERS_1,
 591                             WM8994_AIF2DAC_MUTE_MASK, 0);
 592
 593
 594         ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_LEFT_VOLUME,
 595                              WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACL_VOL_MASK,
 596                              WM8994_AIF2DAC_VU | 0xff);
 597
 598         ret |= wm8994_bic_or(priv, WM8994_AIF2_DAC_RIGHT_VOLUME,
 599                              WM8994_AIF2DAC_VU_MASK | WM8994_AIF2DACR_VOL_MASK,
 600                              WM8994_AIF2DAC_VU | 0xff);
 601
 602
 603         ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
 604                              WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
 605                              WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
 606
 607         ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
 608                              WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
 609                              WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
 610         /* Head Phone Volume */
 611         ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
 612         ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
 613
 614         if (ret < 0) {
 615                 debug("%s: codec register access error\n", __func__);
 616                 return -1;
 617         }
 618
 619         return 0;
 620 }
 621
 622 /*
 623  * Initializes Volume for AIF1 to HP path
 624  *
 625  * @param priv          wm8994 information
 626  * @returns -1 for error  and 0 Success.
 627  *
 628  */
 629 static int wm8994_init_volume_aif1_dac1(struct wm8994_priv *priv)
 630 {
 631         int ret = 0;
 632
 633         /* Unmute AIF1DAC */
 634         ret |= wm8994_i2c_write(priv, WM8994_AIF1_DAC_FILTERS_1, 0x0000);
 635
 636         ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_VOLUME,
 637                              WM8994_DAC1_VU_MASK | WM8994_DAC1L_VOL_MASK |
 638                              WM8994_DAC1L_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
 639
 640         ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_VOLUME,
 641                              WM8994_DAC1_VU_MASK | WM8994_DAC1R_VOL_MASK |
 642                              WM8994_DAC1R_MUTE_MASK, WM8994_DAC1_VU | 0xc0);
 643         /* Head Phone Volume */
 644         ret |= wm8994_i2c_write(priv, WM8994_LEFT_OUTPUT_VOLUME, 0x12D);
 645         ret |= wm8994_i2c_write(priv, WM8994_RIGHT_OUTPUT_VOLUME, 0x12D);
 646
 647         if (ret < 0) {
 648                 debug("%s: codec register access error\n", __func__);
 649                 return -1;
 650         }
 651
 652         return 0;
 653 }
 654
 655 /*
 656  * Intialise wm8994 codec device
 657  *
 658  * @param priv          wm8994 information
 659  *
 660  * @returns -1 for error  and 0 Success.
 661  */
 662 static int wm8994_device_init(struct wm8994_priv *priv)
 663 {
 664         const char *devname;
 665         unsigned short reg_data;
 666         int ret;
 667
 668         wm8994_i2c_write(priv, WM8994_SOFTWARE_RESET, WM8994_SW_RESET);
 669
 670         ret = wm8994_i2c_read(priv, WM8994_SOFTWARE_RESET, &reg_data);
 671         if (ret < 0) {
 672                 debug("Failed to read ID register\n");
 673                 return ret;
 674         }
 675
 676         if (reg_data == WM8994_ID) {
 677                 devname = "WM8994";
 678                 debug("Device registered as type %d\n", priv->type);
 679                 priv->type = WM8994;
 680         } else {
 681                 debug("Device is not a WM8994, ID is %x\n", ret);
 682                 return -ENXIO;
 683         }
 684
 685         ret = wm8994_i2c_read(priv, WM8994_CHIP_REVISION, &reg_data);
 686         if (ret < 0) {
 687                 debug("Failed to read revision register: %d\n", ret);
 688                 return ret;
 689         }
 690         priv->revision = reg_data;
 691         debug("%s revision %c\n", devname, 'A' + priv->revision);
 692
 693         return 0;
 694 }
 695
 696 static int wm8994_setup_interface(struct wm8994_priv *priv,
 697                                   enum en_audio_interface aif_id)
 698 {
 699         int ret;
 700
 701         /* VMID Selection */
 702         ret = wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
 703                             WM8994_VMID_SEL_MASK | WM8994_BIAS_ENA_MASK, 0x3);
 704
 705         /* Charge Pump Enable */
 706         ret |= wm8994_bic_or(priv, WM8994_CHARGE_PUMP_1, WM8994_CP_ENA_MASK,
 707                              WM8994_CP_ENA);
 708
 709         /* Head Phone Power Enable */
 710         ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
 711                              WM8994_HPOUT1L_ENA_MASK, WM8994_HPOUT1L_ENA);
 712
 713         ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_1,
 714                              WM8994_HPOUT1R_ENA_MASK, WM8994_HPOUT1R_ENA);
 715
 716         if (aif_id == WM8994_AIF1) {
 717                 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_2,
 718                                         WM8994_TSHUT_ENA | WM8994_MIXINL_ENA |
 719                                         WM8994_MIXINR_ENA | WM8994_IN2L_ENA |
 720                                         WM8994_IN2R_ENA);
 721
 722                 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_4,
 723                                         WM8994_ADCL_ENA | WM8994_ADCR_ENA |
 724                                         WM8994_AIF1ADC1R_ENA |
 725                                         WM8994_AIF1ADC1L_ENA);
 726
 727                 /* Power enable for AIF1 and DAC1 */
 728                 ret |= wm8994_i2c_write(priv, WM8994_POWER_MANAGEMENT_5,
 729                                         WM8994_AIF1DACL_ENA |
 730                                         WM8994_AIF1DACR_ENA |
 731                                         WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
 732         } else if (aif_id == WM8994_AIF2) {
 733                 /* Power enable for AIF2 and DAC1 */
 734                 ret |= wm8994_bic_or(priv, WM8994_POWER_MANAGEMENT_5,
 735                         WM8994_AIF2DACL_ENA_MASK | WM8994_AIF2DACR_ENA_MASK |
 736                         WM8994_DAC1L_ENA_MASK | WM8994_DAC1R_ENA_MASK,
 737                         WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA |
 738                         WM8994_DAC1L_ENA | WM8994_DAC1R_ENA);
 739         }
 740         /* Head Phone Initialisation */
 741         ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
 742                 WM8994_HPOUT1L_DLY_MASK | WM8994_HPOUT1R_DLY_MASK,
 743                 WM8994_HPOUT1L_DLY | WM8994_HPOUT1R_DLY);
 744
 745         ret |= wm8994_bic_or(priv, WM8994_DC_SERVO_1,
 746                         WM8994_DCS_ENA_CHAN_0_MASK |
 747                         WM8994_DCS_ENA_CHAN_1_MASK , WM8994_DCS_ENA_CHAN_0 |
 748                         WM8994_DCS_ENA_CHAN_1);
 749
 750         ret |= wm8994_bic_or(priv, WM8994_ANALOGUE_HP_1,
 751                         WM8994_HPOUT1L_DLY_MASK |
 752                         WM8994_HPOUT1R_DLY_MASK | WM8994_HPOUT1L_OUTP_MASK |
 753                         WM8994_HPOUT1R_OUTP_MASK |
 754                         WM8994_HPOUT1L_RMV_SHORT_MASK |
 755                         WM8994_HPOUT1R_RMV_SHORT_MASK, WM8994_HPOUT1L_DLY |
 756                         WM8994_HPOUT1R_DLY | WM8994_HPOUT1L_OUTP |
 757                         WM8994_HPOUT1R_OUTP | WM8994_HPOUT1L_RMV_SHORT |
 758                         WM8994_HPOUT1R_RMV_SHORT);
 759
 760         /* MIXER Config DAC1 to HP */
 761         ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_1,
 762                              WM8994_DAC1L_TO_HPOUT1L_MASK,
 763                              WM8994_DAC1L_TO_HPOUT1L);
 764
 765         ret |= wm8994_bic_or(priv, WM8994_OUTPUT_MIXER_2,
 766                              WM8994_DAC1R_TO_HPOUT1R_MASK,
 767                              WM8994_DAC1R_TO_HPOUT1R);
 768
 769         if (aif_id == WM8994_AIF1) {
 770                 /* Routing AIF1 to DAC1 */
 771                 ret |= wm8994_i2c_write(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
 772                                         WM8994_AIF1DAC1L_TO_DAC1L);
 773
 774                 ret |= wm8994_i2c_write(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
 775                                         WM8994_AIF1DAC1R_TO_DAC1R);
 776
 777                 /* GPIO Settings for AIF1 */
 778                 ret |=  wm8994_i2c_write(priv, WM8994_GPIO_1,
 779                                          WM8994_GPIO_DIR_OUTPUT |
 780                                          WM8994_GPIO_FUNCTION_I2S_CLK |
 781                                          WM8994_GPIO_INPUT_DEBOUNCE);
 782
 783                 ret |= wm8994_init_volume_aif1_dac1(priv);
 784         } else if (aif_id == WM8994_AIF2) {
 785                 /* Routing AIF2 to DAC1 */
 786                 ret |= wm8994_bic_or(priv, WM8994_DAC1_LEFT_MIXER_ROUTING,
 787                                      WM8994_AIF2DACL_TO_DAC1L_MASK,
 788                                      WM8994_AIF2DACL_TO_DAC1L);
 789
 790                 ret |= wm8994_bic_or(priv, WM8994_DAC1_RIGHT_MIXER_ROUTING,
 791                                      WM8994_AIF2DACR_TO_DAC1R_MASK,
 792                                      WM8994_AIF2DACR_TO_DAC1R);
 793
 794                 /* GPIO Settings for AIF2 */
 795                 /* B CLK */
 796                 ret |= wm8994_bic_or(priv, WM8994_GPIO_3, WM8994_GPIO_DIR_MASK |
 797                                      WM8994_GPIO_FUNCTION_MASK,
 798                                      WM8994_GPIO_DIR_OUTPUT);
 799
 800                 /* LR CLK */
 801                 ret |= wm8994_bic_or(priv, WM8994_GPIO_4, WM8994_GPIO_DIR_MASK |
 802                                      WM8994_GPIO_FUNCTION_MASK,
 803                                      WM8994_GPIO_DIR_OUTPUT);
 804
 805                 /* DATA */
 806                 ret |= wm8994_bic_or(priv, WM8994_GPIO_5, WM8994_GPIO_DIR_MASK |
 807                                      WM8994_GPIO_FUNCTION_MASK,
 808                                      WM8994_GPIO_DIR_OUTPUT);
 809
 810                 ret |= wm8994_init_volume_aif2_dac1(priv);
 811         }
 812
 813         if (ret < 0)
 814                 goto err;
 815
 816         debug("%s: Codec chip setup ok\n", __func__);
 817         return 0;
 818 err:
 819         debug("%s: Codec chip setup error\n", __func__);
 820         return -1;
 821 }
 822
 823 /*
 824  * Gets fdt values for wm8994 config parameters
 825  *
 826  * @param pcodec_info   codec information structure
 827  * @param blob          FDT blob
 828  * @return              int value, 0 for success
 829  */
 830 static int get_codec_values(struct sound_codec_info *pcodec_info,
 831                             const void *blob)
 832 {
 833         int error = 0;
 834         enum fdt_compat_id compat;
 835         int node;
 836         int parent;
 837
 838         /* Get the node from FDT for codec */
 839         node = fdtdec_next_compatible(blob, 0, COMPAT_WOLFSON_WM8994_CODEC);
 840         if (node <= 0) {
 841                 debug("EXYNOS_SOUND: No node for codec in device tree\n");
 842                 debug("node = %d\n", node);
 843                 return -1;
 844         }
 845
 846         parent = fdt_parent_offset(blob, node);
 847         if (parent < 0) {
 848                 debug("%s: Cannot find node parent\n", __func__);
 849                 return -1;
 850         }
 851
 852         compat = fdtdec_lookup(blob, parent);
 853         switch (compat) {
 854         case COMPAT_SAMSUNG_S3C2440_I2C:
 855                 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
 856                 error |= pcodec_info->i2c_bus;
 857                 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
 858                 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
 859                                                         "reg", 0);
 860                 error |= pcodec_info->i2c_dev_addr;
 861                 debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr);
 862                 break;
 863         default:
 864                 debug("%s: Unknown compat id %d\n", __func__, compat);
 865                 return -1;
 866         }
 867
 868         if (error == -1) {
 869                 debug("fail to get wm8994 codec node properties\n");
 870                 return -1;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int _wm8994_init(struct wm8994_priv *priv,
 877                         enum en_audio_interface aif_id, int sampling_rate,
 878                         int mclk_freq, int bits_per_sample,
 879                         unsigned int channels)
 880 {
 881         int ret;
 882
 883         ret = wm8994_setup_interface(priv, aif_id);
 884         if (ret < 0) {
 885                 debug("%s: wm8994 codec chip init failed\n", __func__);
 886                 return ret;
 887         }
 888
 889         ret =  wm8994_set_sysclk(priv, aif_id, WM8994_SYSCLK_MCLK1, mclk_freq);
 890         if (ret < 0) {
 891                 debug("%s: wm8994 codec set sys clock failed\n", __func__);
 892                 return ret;
 893         }
 894
 895         ret = wm8994_hw_params(priv, aif_id, sampling_rate, bits_per_sample,
 896                                channels);
 897
 898         if (ret == 0) {
 899                 ret = wm8994_set_fmt(priv, aif_id, SND_SOC_DAIFMT_I2S |
 900                                      SND_SOC_DAIFMT_NB_NF |
 901                                      SND_SOC_DAIFMT_CBS_CFS);
 902         }
 903
 904         return ret;
 905 }
 906
 907 /* WM8994 Device Initialisation */
 908 int wm8994_init(const void *blob, enum en_audio_interface aif_id,
 909                 int sampling_rate, int mclk_freq, int bits_per_sample,
 910                 unsigned int channels)
 911 {
 912         struct sound_codec_info *pcodec_info = &g_codec_info;
 913         int ret;
 914
 915         /* Get the codec Values */
 916         if (get_codec_values(pcodec_info, blob) < 0) {
 917                 debug("FDT Codec values failed\n");
 918                 return -1;
 919         }
 920
 921         /* shift the device address by 1 for 7 bit addressing */
 922         g_wm8994_i2c_dev_addr = pcodec_info->i2c_dev_addr;
 923         wm8994_i2c_init(pcodec_info->i2c_bus);
 924         ret = wm8994_device_init(&g_wm8994_info);
 925         if (ret < 0) {
 926                 debug("%s: wm8994 codec chip init failed\n", __func__);
 927                 return ret;
 928         }
 929
 930         return _wm8994_init(&g_wm8994_info, aif_id, sampling_rate, mclk_freq,
 931                             bits_per_sample, channels);
 932 }