2 * max98095.c -- MAX98095 ALSA SoC Audio driver
4 * Copyright 2011 Maxim Integrated Products
6 * Modified for uboot by R. Chandrasekar (rcsekar@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <asm/arch/clk.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/power.h>
27 struct max98095_priv {
33 static struct sound_codec_info g_codec_info;
34 struct max98095_priv g_max98095_info;
35 unsigned int g_max98095_i2c_dev_addr;
37 /* Index 0 is reserved. */
38 int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
42 * Writes value to a device register through i2c
44 * @param reg reg number to be write
45 * @param data data to be writen to the above registor
47 * @return int value 1 for change, 0 for no change or negative error code.
49 static int max98095_i2c_write(unsigned int reg, unsigned char data)
51 debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n",
53 return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1);
57 * Read a value from a device register through i2c
59 * @param reg reg number to be read
60 * @param data address of read data to be stored
62 * @return int value 0 for success, -1 in case of error.
64 static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data)
68 ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1);
70 debug("%s: Error while reading register %#04x\n",
79 * update device register bits through i2c
81 * @param reg codec register
82 * @param mask register mask
83 * @param value new value
85 * @return int value 0 for success, non-zero error code.
87 static int max98095_update_bits(unsigned int reg, unsigned char mask,
91 unsigned char old, new;
93 if (max98095_i2c_read(reg, &old) != 0)
95 new = (old & ~mask) | (value & mask);
96 change = (old != new) ? 1 : 0;
98 ret = max98095_i2c_write(reg, new);
106 * codec mclk clock divider coefficients based on sampling rate
108 * @param rate sampling rate
109 * @param value address of indexvalue to be stored
111 * @return 0 for success or negative error code.
113 static int rate_value(int rate, u8 *value)
117 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
118 if (rate_table[i] >= rate) {
129 * Sets hw params for max98095
131 * @param max98095 max98095 information pointer
132 * @param rate Sampling rate
133 * @param bits_per_sample Bits per sample
135 * @return -1 for error and 0 Success.
137 static int max98095_hw_params(struct max98095_priv *max98095,
138 enum en_max_audio_interface aif_id,
139 unsigned int rate, unsigned int bits_per_sample)
143 unsigned short M98095_DAI_CLKMODE;
144 unsigned short M98095_DAI_FORMAT;
145 unsigned short M98095_DAI_FILTERS;
147 if (aif_id == AIF1) {
148 M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
149 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
150 M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
152 M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
153 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
154 M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
157 switch (bits_per_sample) {
159 error = max98095_update_bits(M98095_DAI_FORMAT,
163 error = max98095_update_bits(M98095_DAI_FORMAT,
164 M98095_DAI_WS, M98095_DAI_WS);
167 debug("%s: Illegal bits per sample %d.\n",
168 __func__, bits_per_sample);
172 if (rate_value(rate, ®val)) {
173 debug("%s: Failed to set sample rate to %d.\n",
177 max98095->rate = rate;
179 error |= max98095_update_bits(M98095_DAI_CLKMODE,
180 M98095_CLKMODE_MASK, regval);
182 /* Update sample rate mode */
184 error |= max98095_update_bits(M98095_DAI_FILTERS,
187 error |= max98095_update_bits(M98095_DAI_FILTERS,
188 M98095_DAI_DHF, M98095_DAI_DHF);
191 debug("%s: Error setting hardware params.\n", __func__);
199 * Configures Audio interface system clock for the given frequency
201 * @param max98095 max98095 information
202 * @param freq Sampling frequency in Hz
204 * @return -1 for error and 0 success.
206 static int max98095_set_sysclk(struct max98095_priv *max98095,
211 /* Requested clock frequency is already setup */
212 if (freq == max98095->sysclk)
215 /* Setup clocks for slave mode, and using the PLL
216 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
217 * 0x02 (when master clk is 20MHz to 40MHz)..
218 * 0x03 (when master clk is 40MHz to 60MHz)..
220 if ((freq >= 10000000) && (freq < 20000000)) {
221 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x10);
222 } else if ((freq >= 20000000) && (freq < 40000000)) {
223 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x20);
224 } else if ((freq >= 40000000) && (freq < 60000000)) {
225 error = max98095_i2c_write(M98095_026_SYS_CLK, 0x30);
227 debug("%s: Invalid master clock frequency\n", __func__);
231 debug("%s: Clock at %uHz\n", __func__, freq);
236 max98095->sysclk = freq;
241 * Sets Max98095 I2S format
243 * @param max98095 max98095 information
244 * @param fmt i2S format - supports a subset of the options defined
247 * @return -1 for error and 0 Success.
249 static int max98095_set_fmt(struct max98095_priv *max98095, int fmt,
250 enum en_max_audio_interface aif_id)
254 unsigned short M98095_DAI_CLKCFG_HI;
255 unsigned short M98095_DAI_CLKCFG_LO;
256 unsigned short M98095_DAI_FORMAT;
257 unsigned short M98095_DAI_CLOCK;
259 if (fmt == max98095->fmt)
264 if (aif_id == AIF1) {
265 M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
266 M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
267 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
268 M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
270 M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
271 M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
272 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
273 M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
276 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
277 case SND_SOC_DAIFMT_CBS_CFS:
279 error |= max98095_i2c_write(M98095_DAI_CLKCFG_HI,
281 error |= max98095_i2c_write(M98095_DAI_CLKCFG_LO,
284 case SND_SOC_DAIFMT_CBM_CFM:
285 /* Set to master mode */
286 regval |= M98095_DAI_MAS;
288 case SND_SOC_DAIFMT_CBS_CFM:
289 case SND_SOC_DAIFMT_CBM_CFS:
291 debug("%s: Clock mode unsupported\n", __func__);
295 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
296 case SND_SOC_DAIFMT_I2S:
297 regval |= M98095_DAI_DLY;
299 case SND_SOC_DAIFMT_LEFT_J:
302 debug("%s: Unrecognized format.\n", __func__);
306 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
307 case SND_SOC_DAIFMT_NB_NF:
309 case SND_SOC_DAIFMT_NB_IF:
310 regval |= M98095_DAI_WCI;
312 case SND_SOC_DAIFMT_IB_NF:
313 regval |= M98095_DAI_BCI;
315 case SND_SOC_DAIFMT_IB_IF:
316 regval |= M98095_DAI_BCI | M98095_DAI_WCI;
319 debug("%s: Unrecognized inversion settings.\n", __func__);
323 error |= max98095_update_bits(M98095_DAI_FORMAT,
324 M98095_DAI_MAS | M98095_DAI_DLY |
325 M98095_DAI_BCI | M98095_DAI_WCI,
328 error |= max98095_i2c_write(M98095_DAI_CLOCK,
332 debug("%s: Error setting i2s format.\n", __func__);
340 * resets the audio codec
342 * @return -1 for error and 0 success.
344 static int max98095_reset(void)
349 * Gracefully reset the DSP core and the codec hardware in a proper
352 ret = max98095_i2c_write(M98095_00F_HOST_CFG, 0);
354 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
358 ret = max98095_i2c_write(M98095_097_PWR_SYS, 0);
360 debug("%s: Failed to reset codec: %d\n", __func__, ret);
365 * Reset to hardware default for registers, as there is not a soft
366 * reset hardware control register.
368 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
369 ret = max98095_i2c_write(i, 0);
371 debug("%s: Failed to reset: %d\n", __func__, ret);
380 * Intialise max98095 codec device
382 * @param max98095 max98095 information
384 * @returns -1 for error and 0 Success.
386 static int max98095_device_init(struct max98095_priv *max98095,
387 enum en_max_audio_interface aif_id)
392 /* reset the codec, the DSP core, and disable all interrupts */
393 error = max98095_reset();
399 /* initialize private data */
400 max98095->sysclk = -1U;
401 max98095->rate = -1U;
404 error = max98095_i2c_read(M98095_0FF_REV_ID, &id);
406 debug("%s: Failure reading hardware revision: %d\n",
410 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
412 error |= max98095_i2c_write(M98095_097_PWR_SYS, M98095_PWRSV);
415 * initialize registers to hardware default configuring audio
419 error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
420 M98095_DAI1L_TO_DACL |
421 M98095_DAI1R_TO_DACR);
423 error |= max98095_i2c_write(M98095_048_MIX_DAC_LR,
424 M98095_DAI2M_TO_DACL |
425 M98095_DAI2M_TO_DACR);
427 error |= max98095_i2c_write(M98095_092_PWR_EN_OUT,
428 M98095_SPK_SPREADSPECTRUM);
429 error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL);
431 error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG,
432 M98095_S1NORMAL | M98095_SDATA);
434 error |= max98095_i2c_write(M98095_036_DAI2_IOCFG,
435 M98095_S2NORMAL | M98095_SDATA);
437 /* take the codec out of the shut down */
438 error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN,
440 /* route DACL and DACR output to HO and Spekers */
441 error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */
442 error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */
443 error |= max98095_i2c_write(M98095_04C_MIX_HP_LEFT, 0x01); /* DACL */
444 error |= max98095_i2c_write(M98095_04D_MIX_HP_RIGHT, 0x01); /* DACR */
447 error |= max98095_i2c_write(M98095_091_PWR_EN_OUT, 0xF3);
450 error |= max98095_i2c_write(M98095_064_LVL_HP_L, 15);
451 error |= max98095_i2c_write(M98095_065_LVL_HP_R, 15);
452 error |= max98095_i2c_write(M98095_067_LVL_SPK_L, 16);
453 error |= max98095_i2c_write(M98095_068_LVL_SPK_R, 16);
456 error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30);
458 error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x01);
460 error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07);
469 static int max98095_do_init(struct sound_codec_info *pcodec_info,
470 enum en_max_audio_interface aif_id,
471 int sampling_rate, int mclk_freq,
476 /* Enable codec clock */
479 /* shift the device address by 1 for 7 bit addressing */
480 g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1;
482 ret = max98095_device_init(&g_max98095_info, aif_id);
484 debug("%s: max98095 codec chip init failed\n", __func__);
488 ret = max98095_set_sysclk(&g_max98095_info, mclk_freq);
490 debug("%s: max98095 codec set sys clock failed\n", __func__);
494 ret = max98095_hw_params(&g_max98095_info, aif_id, sampling_rate,
498 ret = max98095_set_fmt(&g_max98095_info,
500 SND_SOC_DAIFMT_NB_NF |
501 SND_SOC_DAIFMT_CBS_CFS,
508 static int get_max98095_codec_values(struct sound_codec_info *pcodec_info,
512 enum fdt_compat_id compat;
516 /* Get the node from FDT for codec */
517 node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC);
519 debug("EXYNOS_SOUND: No node for codec in device tree\n");
520 debug("node = %d\n", node);
524 parent = fdt_parent_offset(blob, node);
526 debug("%s: Cannot find node parent\n", __func__);
530 compat = fdtdec_lookup(blob, parent);
532 case COMPAT_SAMSUNG_S3C2440_I2C:
533 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
534 error |= pcodec_info->i2c_bus;
535 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
536 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
538 error |= pcodec_info->i2c_dev_addr;
539 debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr);
542 debug("%s: Unknown compat id %d\n", __func__, compat);
546 debug("fail to get max98095 codec node properties\n");
553 /* max98095 Device Initialisation */
554 int max98095_init(const void *blob, enum en_max_audio_interface aif_id,
555 int sampling_rate, int mclk_freq,
559 int old_bus = i2c_get_bus_num();
560 struct sound_codec_info *pcodec_info = &g_codec_info;
562 if (get_max98095_codec_values(pcodec_info, blob) < 0) {
563 debug("FDT Codec values failed\n");
567 i2c_set_bus_num(pcodec_info->i2c_bus);
568 ret = max98095_do_init(pcodec_info, aif_id, sampling_rate, mclk_freq,
570 i2c_set_bus_num(old_bus);