2 * max98095.c -- MAX98095 ALSA SoC Audio driver
4 * Copyright 2011 Maxim Integrated Products
6 * Modified for uboot by R. Chandrasekar (rcsekar@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <audio_codec.h>
22 #include <asm/arch/clk.h>
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/power.h>
28 /* Index 0 is reserved. */
29 int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
33 * codec mclk clock divider coefficients based on sampling rate
35 * @param rate sampling rate
36 * @param value address of indexvalue to be stored
38 * @return 0 for success or negative error code.
40 static int rate_value(int rate, u8 *value)
44 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
45 if (rate_table[i] >= rate) {
56 * Sets hw params for max98095
58 * @param priv max98095 information pointer
59 * @param rate Sampling rate
60 * @param bits_per_sample Bits per sample
62 * @return -1 for error and 0 Success.
64 static int max98095_hw_params(struct maxim_priv *priv,
65 enum en_max_audio_interface aif_id,
66 unsigned int rate, unsigned int bits_per_sample)
70 unsigned short M98095_DAI_CLKMODE;
71 unsigned short M98095_DAI_FORMAT;
72 unsigned short M98095_DAI_FILTERS;
75 M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
76 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
77 M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
79 M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
80 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
81 M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
84 switch (bits_per_sample) {
86 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 0);
89 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS,
93 debug("%s: Illegal bits per sample %d.\n",
94 __func__, bits_per_sample);
98 if (rate_value(rate, ®val)) {
99 debug("%s: Failed to set sample rate to %d.\n",
105 error |= maxim_bic_or(priv, M98095_DAI_CLKMODE, M98095_CLKMODE_MASK,
108 /* Update sample rate mode */
110 error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
113 error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
114 M98095_DAI_DHF, M98095_DAI_DHF);
117 debug("%s: Error setting hardware params.\n", __func__);
125 * Configures Audio interface system clock for the given frequency
127 * @param priv max98095 information
128 * @param freq Sampling frequency in Hz
130 * @return -1 for error and 0 success.
132 static int max98095_set_sysclk(struct maxim_priv *priv, unsigned int freq)
136 /* Requested clock frequency is already setup */
137 if (freq == priv->sysclk)
140 /* Setup clocks for slave mode, and using the PLL
141 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
142 * 0x02 (when master clk is 20MHz to 40MHz)..
143 * 0x03 (when master clk is 40MHz to 60MHz)..
145 if ((freq >= 10000000) && (freq < 20000000)) {
146 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x10);
147 } else if ((freq >= 20000000) && (freq < 40000000)) {
148 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x20);
149 } else if ((freq >= 40000000) && (freq < 60000000)) {
150 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x30);
152 debug("%s: Invalid master clock frequency\n", __func__);
156 debug("%s: Clock at %uHz\n", __func__, freq);
166 * Sets Max98095 I2S format
168 * @param priv max98095 information
169 * @param fmt i2S format - supports a subset of the options defined
172 * @return -1 for error and 0 Success.
174 static int max98095_set_fmt(struct maxim_priv *priv, int fmt,
175 enum en_max_audio_interface aif_id)
179 unsigned short M98095_DAI_CLKCFG_HI;
180 unsigned short M98095_DAI_CLKCFG_LO;
181 unsigned short M98095_DAI_FORMAT;
182 unsigned short M98095_DAI_CLOCK;
184 if (fmt == priv->fmt)
189 if (aif_id == AIF1) {
190 M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
191 M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
192 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
193 M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
195 M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
196 M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
197 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
198 M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
201 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
202 case SND_SOC_DAIFMT_CBS_CFS:
204 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_HI, 0x80);
205 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_LO, 0x00);
207 case SND_SOC_DAIFMT_CBM_CFM:
208 /* Set to master mode */
209 regval |= M98095_DAI_MAS;
211 case SND_SOC_DAIFMT_CBS_CFM:
212 case SND_SOC_DAIFMT_CBM_CFS:
214 debug("%s: Clock mode unsupported\n", __func__);
218 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
219 case SND_SOC_DAIFMT_I2S:
220 regval |= M98095_DAI_DLY;
222 case SND_SOC_DAIFMT_LEFT_J:
225 debug("%s: Unrecognized format.\n", __func__);
229 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
230 case SND_SOC_DAIFMT_NB_NF:
232 case SND_SOC_DAIFMT_NB_IF:
233 regval |= M98095_DAI_WCI;
235 case SND_SOC_DAIFMT_IB_NF:
236 regval |= M98095_DAI_BCI;
238 case SND_SOC_DAIFMT_IB_IF:
239 regval |= M98095_DAI_BCI | M98095_DAI_WCI;
242 debug("%s: Unrecognized inversion settings.\n", __func__);
246 error |= maxim_bic_or(priv, M98095_DAI_FORMAT,
247 M98095_DAI_MAS | M98095_DAI_DLY |
248 M98095_DAI_BCI | M98095_DAI_WCI, regval);
250 error |= maxim_i2c_write(priv, M98095_DAI_CLOCK, M98095_DAI_BSEL64);
253 debug("%s: Error setting i2s format.\n", __func__);
261 * resets the audio codec
263 * @param priv Private data for driver
264 * @return -1 for error and 0 success.
266 static int max98095_reset(struct maxim_priv *priv)
271 * Gracefully reset the DSP core and the codec hardware in a proper
274 ret = maxim_i2c_write(priv, M98095_00F_HOST_CFG, 0);
276 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
280 ret = maxim_i2c_write(priv, M98095_097_PWR_SYS, 0);
282 debug("%s: Failed to reset codec: %d\n", __func__, ret);
287 * Reset to hardware default for registers, as there is not a soft
288 * reset hardware control register.
290 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
291 ret = maxim_i2c_write(priv, i, 0);
293 debug("%s: Failed to reset: %d\n", __func__, ret);
302 * Intialise max98095 codec device
304 * @param priv max98095 information
306 * @returns -1 for error and 0 Success.
308 static int max98095_device_init(struct maxim_priv *priv)
313 /* Enable codec clock */
316 /* reset the codec, the DSP core, and disable all interrupts */
317 error = max98095_reset(priv);
323 /* initialize private data */
328 error = maxim_i2c_read(priv, M98095_0FF_REV_ID, &id);
330 debug("%s: Failure reading hardware revision: %d\n",
334 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
339 static int max98095_setup_interface(struct maxim_priv *priv,
340 enum en_max_audio_interface aif_id)
344 error = maxim_i2c_write(priv, M98095_097_PWR_SYS, M98095_PWRSV);
347 * initialize registers to hardware default configuring audio
351 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
352 M98095_DAI1L_TO_DACL |
353 M98095_DAI1R_TO_DACR);
355 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
356 M98095_DAI2M_TO_DACL |
357 M98095_DAI2M_TO_DACR);
359 error |= maxim_i2c_write(priv, M98095_092_PWR_EN_OUT,
360 M98095_SPK_SPREADSPECTRUM);
361 error |= maxim_i2c_write(priv, M98095_04E_CFG_HP, M98095_HPNORMAL);
363 error |= maxim_i2c_write(priv, M98095_02C_DAI1_IOCFG,
364 M98095_S1NORMAL | M98095_SDATA);
366 error |= maxim_i2c_write(priv, M98095_036_DAI2_IOCFG,
367 M98095_S2NORMAL | M98095_SDATA);
369 /* take the codec out of the shut down */
370 error |= maxim_bic_or(priv, M98095_097_PWR_SYS, M98095_SHDNRUN,
373 * route DACL and DACR output to HO and Speakers
374 * Ordering: DACL, DACR, DACL, DACR
376 error |= maxim_i2c_write(priv, M98095_050_MIX_SPK_LEFT, 0x01);
377 error |= maxim_i2c_write(priv, M98095_051_MIX_SPK_RIGHT, 0x01);
378 error |= maxim_i2c_write(priv, M98095_04C_MIX_HP_LEFT, 0x01);
379 error |= maxim_i2c_write(priv, M98095_04D_MIX_HP_RIGHT, 0x01);
382 error |= maxim_i2c_write(priv, M98095_091_PWR_EN_OUT, 0xF3);
385 error |= maxim_i2c_write(priv, M98095_064_LVL_HP_L, 15);
386 error |= maxim_i2c_write(priv, M98095_065_LVL_HP_R, 15);
387 error |= maxim_i2c_write(priv, M98095_067_LVL_SPK_L, 16);
388 error |= maxim_i2c_write(priv, M98095_068_LVL_SPK_R, 16);
391 error |= maxim_i2c_write(priv, M98095_093_BIAS_CTRL, 0x30);
393 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x01);
395 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x07);
403 static int max98095_do_init(struct maxim_priv *priv,
404 enum en_max_audio_interface aif_id,
405 int sampling_rate, int mclk_freq,
410 ret = max98095_setup_interface(priv, aif_id);
412 debug("%s: max98095 setup interface failed\n", __func__);
416 ret = max98095_set_sysclk(priv, mclk_freq);
418 debug("%s: max98095 codec set sys clock failed\n", __func__);
422 ret = max98095_hw_params(priv, aif_id, sampling_rate,
426 ret = max98095_set_fmt(priv, SND_SOC_DAIFMT_I2S |
427 SND_SOC_DAIFMT_NB_NF |
428 SND_SOC_DAIFMT_CBS_CFS,
435 #ifndef CONFIG_DM_SOUND
436 static int get_max98095_codec_values(struct sound_codec_info *pcodec_info,
440 enum fdt_compat_id compat;
444 /* Get the node from FDT for codec */
445 node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC);
447 debug("EXYNOS_SOUND: No node for codec in device tree\n");
448 debug("node = %d\n", node);
452 parent = fdt_parent_offset(blob, node);
454 debug("%s: Cannot find node parent\n", __func__);
458 compat = fdtdec_lookup(blob, parent);
460 case COMPAT_SAMSUNG_S3C2440_I2C:
461 pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent);
462 error |= pcodec_info->i2c_bus;
463 debug("i2c bus = %d\n", pcodec_info->i2c_bus);
464 pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node,
466 error |= pcodec_info->i2c_dev_addr;
467 debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr);
470 debug("%s: Unknown compat id %d\n", __func__, compat);
474 debug("fail to get max98095 codec node properties\n");
481 /* max98095 Device Initialisation */
482 int max98095_init(const void *blob, enum en_max_audio_interface aif_id,
483 int sampling_rate, int mclk_freq,
487 int old_bus = i2c_get_bus_num();
488 struct sound_codec_info pcodec_info;
489 struct max98095_priv max98095_info;
491 if (get_max98095_codec_values(&pcodec_info, blob) < 0) {
492 debug("FDT Codec values failed\n");
496 i2c_set_bus_num(pcodec_info.i2c_bus);
498 max98095_info.i2c_addr = pcodec_info.i2c_dev_addr;
499 ret = max98095_device_init(&max98095_info);
501 debug("%s: max98095 codec chip init failed\n", __func__);
505 ret = max98095_do_init(&max98095_info, aif_id, sampling_rate, mclk_freq,
507 i2c_set_bus_num(old_bus);
513 static int max98095_set_params(struct udevice *dev, int interface, int rate,
514 int mclk_freq, int bits_per_sample,
517 struct maxim_priv *priv = dev_get_priv(dev);
519 return max98095_do_init(priv, interface, rate, mclk_freq,
523 static int max98095_probe(struct udevice *dev)
525 struct maxim_priv *priv = dev_get_priv(dev);
529 ret = max98095_device_init(priv);
531 debug("%s: max98095 codec chip init failed\n", __func__);
538 static const struct audio_codec_ops max98095_ops = {
539 .set_params = max98095_set_params,
542 static const struct udevice_id max98095_ids[] = {
543 { .compatible = "maxim,max98095" },
547 U_BOOT_DRIVER(max98095) = {
549 .id = UCLASS_AUDIO_CODEC,
550 .of_match = max98095_ids,
551 .probe = max98095_probe,
552 .ops = &max98095_ops,
553 .priv_auto_alloc_size = sizeof(struct maxim_priv),