1 // SPDX-License-Identifier: GPL-2.0+
3 * max98095.c -- MAX98095 ALSA SoC Audio driver
5 * Copyright 2011 Maxim Integrated Products
7 * Modified for U-Boot by R. Chandrasekar (rcsekar@samsung.com)
11 #include <audio_codec.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/power.h>
25 /* Index 0 is reserved. */
26 int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
30 * codec mclk clock divider coefficients based on sampling rate
32 * @param rate sampling rate
33 * @param value address of indexvalue to be stored
35 * @return 0 for success or negative error code.
37 static int rate_value(int rate, u8 *value)
41 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
42 if (rate_table[i] >= rate) {
53 * Sets hw params for max98095
55 * @param priv max98095 information pointer
56 * @param rate Sampling rate
57 * @param bits_per_sample Bits per sample
59 * @return -1 for error and 0 Success.
61 static int max98095_hw_params(struct maxim_priv *priv,
62 enum en_max_audio_interface aif_id,
63 unsigned int rate, unsigned int bits_per_sample)
67 unsigned short M98095_DAI_CLKMODE;
68 unsigned short M98095_DAI_FORMAT;
69 unsigned short M98095_DAI_FILTERS;
72 M98095_DAI_CLKMODE = M98095_027_DAI1_CLKMODE;
73 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
74 M98095_DAI_FILTERS = M98095_02E_DAI1_FILTERS;
76 M98095_DAI_CLKMODE = M98095_031_DAI2_CLKMODE;
77 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
78 M98095_DAI_FILTERS = M98095_038_DAI2_FILTERS;
81 switch (bits_per_sample) {
83 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS, 0);
86 error = maxim_bic_or(priv, M98095_DAI_FORMAT, M98095_DAI_WS,
90 debug("%s: Illegal bits per sample %d.\n",
91 __func__, bits_per_sample);
95 if (rate_value(rate, ®val)) {
96 debug("%s: Failed to set sample rate to %d.\n",
102 error |= maxim_bic_or(priv, M98095_DAI_CLKMODE, M98095_CLKMODE_MASK,
105 /* Update sample rate mode */
107 error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
110 error |= maxim_bic_or(priv, M98095_DAI_FILTERS,
111 M98095_DAI_DHF, M98095_DAI_DHF);
114 debug("%s: Error setting hardware params.\n", __func__);
122 * Configures Audio interface system clock for the given frequency
124 * @param priv max98095 information
125 * @param freq Sampling frequency in Hz
127 * @return -1 for error and 0 success.
129 static int max98095_set_sysclk(struct maxim_priv *priv, unsigned int freq)
133 /* Requested clock frequency is already setup */
134 if (freq == priv->sysclk)
137 /* Setup clocks for slave mode, and using the PLL
138 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
139 * 0x02 (when master clk is 20MHz to 40MHz)..
140 * 0x03 (when master clk is 40MHz to 60MHz)..
142 if ((freq >= 10000000) && (freq < 20000000)) {
143 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x10);
144 } else if ((freq >= 20000000) && (freq < 40000000)) {
145 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x20);
146 } else if ((freq >= 40000000) && (freq < 60000000)) {
147 error = maxim_i2c_write(priv, M98095_026_SYS_CLK, 0x30);
149 debug("%s: Invalid master clock frequency\n", __func__);
153 debug("%s: Clock at %uHz\n", __func__, freq);
163 * Sets Max98095 I2S format
165 * @param priv max98095 information
166 * @param fmt i2S format - supports a subset of the options defined
169 * @return -1 for error and 0 Success.
171 static int max98095_set_fmt(struct maxim_priv *priv, int fmt,
172 enum en_max_audio_interface aif_id)
176 unsigned short M98095_DAI_CLKCFG_HI;
177 unsigned short M98095_DAI_CLKCFG_LO;
178 unsigned short M98095_DAI_FORMAT;
179 unsigned short M98095_DAI_CLOCK;
181 if (fmt == priv->fmt)
186 if (aif_id == AIF1) {
187 M98095_DAI_CLKCFG_HI = M98095_028_DAI1_CLKCFG_HI;
188 M98095_DAI_CLKCFG_LO = M98095_029_DAI1_CLKCFG_LO;
189 M98095_DAI_FORMAT = M98095_02A_DAI1_FORMAT;
190 M98095_DAI_CLOCK = M98095_02B_DAI1_CLOCK;
192 M98095_DAI_CLKCFG_HI = M98095_032_DAI2_CLKCFG_HI;
193 M98095_DAI_CLKCFG_LO = M98095_033_DAI2_CLKCFG_LO;
194 M98095_DAI_FORMAT = M98095_034_DAI2_FORMAT;
195 M98095_DAI_CLOCK = M98095_035_DAI2_CLOCK;
198 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
199 case SND_SOC_DAIFMT_CBS_CFS:
201 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_HI, 0x80);
202 error |= maxim_i2c_write(priv, M98095_DAI_CLKCFG_LO, 0x00);
204 case SND_SOC_DAIFMT_CBM_CFM:
205 /* Set to master mode */
206 regval |= M98095_DAI_MAS;
208 case SND_SOC_DAIFMT_CBS_CFM:
209 case SND_SOC_DAIFMT_CBM_CFS:
211 debug("%s: Clock mode unsupported\n", __func__);
215 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
216 case SND_SOC_DAIFMT_I2S:
217 regval |= M98095_DAI_DLY;
219 case SND_SOC_DAIFMT_LEFT_J:
222 debug("%s: Unrecognized format.\n", __func__);
226 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
227 case SND_SOC_DAIFMT_NB_NF:
229 case SND_SOC_DAIFMT_NB_IF:
230 regval |= M98095_DAI_WCI;
232 case SND_SOC_DAIFMT_IB_NF:
233 regval |= M98095_DAI_BCI;
235 case SND_SOC_DAIFMT_IB_IF:
236 regval |= M98095_DAI_BCI | M98095_DAI_WCI;
239 debug("%s: Unrecognized inversion settings.\n", __func__);
243 error |= maxim_bic_or(priv, M98095_DAI_FORMAT,
244 M98095_DAI_MAS | M98095_DAI_DLY |
245 M98095_DAI_BCI | M98095_DAI_WCI, regval);
247 error |= maxim_i2c_write(priv, M98095_DAI_CLOCK, M98095_DAI_BSEL64);
250 debug("%s: Error setting i2s format.\n", __func__);
258 * resets the audio codec
260 * @param priv Private data for driver
261 * @return -1 for error and 0 success.
263 static int max98095_reset(struct maxim_priv *priv)
268 * Gracefully reset the DSP core and the codec hardware in a proper
271 ret = maxim_i2c_write(priv, M98095_00F_HOST_CFG, 0);
273 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
277 ret = maxim_i2c_write(priv, M98095_097_PWR_SYS, 0);
279 debug("%s: Failed to reset codec: %d\n", __func__, ret);
284 * Reset to hardware default for registers, as there is not a soft
285 * reset hardware control register.
287 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) {
288 ret = maxim_i2c_write(priv, i, 0);
290 debug("%s: Failed to reset: %d\n", __func__, ret);
299 * Intialise max98095 codec device
301 * @param priv max98095 information
303 * @returns -1 for error and 0 Success.
305 static int max98095_device_init(struct maxim_priv *priv)
310 /* Enable codec clock */
313 /* reset the codec, the DSP core, and disable all interrupts */
314 error = max98095_reset(priv);
320 /* initialize private data */
325 error = maxim_i2c_read(priv, M98095_0FF_REV_ID, &id);
327 debug("%s: Failure reading hardware revision: %d\n",
331 debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A');
336 static int max98095_setup_interface(struct maxim_priv *priv,
337 enum en_max_audio_interface aif_id)
341 error = maxim_i2c_write(priv, M98095_097_PWR_SYS, M98095_PWRSV);
344 * initialize registers to hardware default configuring audio
348 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
349 M98095_DAI1L_TO_DACL |
350 M98095_DAI1R_TO_DACR);
352 error |= maxim_i2c_write(priv, M98095_048_MIX_DAC_LR,
353 M98095_DAI2M_TO_DACL |
354 M98095_DAI2M_TO_DACR);
356 error |= maxim_i2c_write(priv, M98095_092_PWR_EN_OUT,
357 M98095_SPK_SPREADSPECTRUM);
358 error |= maxim_i2c_write(priv, M98095_04E_CFG_HP, M98095_HPNORMAL);
360 error |= maxim_i2c_write(priv, M98095_02C_DAI1_IOCFG,
361 M98095_S1NORMAL | M98095_SDATA);
363 error |= maxim_i2c_write(priv, M98095_036_DAI2_IOCFG,
364 M98095_S2NORMAL | M98095_SDATA);
366 /* take the codec out of the shut down */
367 error |= maxim_bic_or(priv, M98095_097_PWR_SYS, M98095_SHDNRUN,
370 * route DACL and DACR output to HO and Speakers
371 * Ordering: DACL, DACR, DACL, DACR
373 error |= maxim_i2c_write(priv, M98095_050_MIX_SPK_LEFT, 0x01);
374 error |= maxim_i2c_write(priv, M98095_051_MIX_SPK_RIGHT, 0x01);
375 error |= maxim_i2c_write(priv, M98095_04C_MIX_HP_LEFT, 0x01);
376 error |= maxim_i2c_write(priv, M98095_04D_MIX_HP_RIGHT, 0x01);
379 error |= maxim_i2c_write(priv, M98095_091_PWR_EN_OUT, 0xF3);
382 error |= maxim_i2c_write(priv, M98095_064_LVL_HP_L, 15);
383 error |= maxim_i2c_write(priv, M98095_065_LVL_HP_R, 15);
384 error |= maxim_i2c_write(priv, M98095_067_LVL_SPK_L, 16);
385 error |= maxim_i2c_write(priv, M98095_068_LVL_SPK_R, 16);
388 error |= maxim_i2c_write(priv, M98095_093_BIAS_CTRL, 0x30);
390 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x01);
392 error |= maxim_i2c_write(priv, M98095_096_PWR_DAC_CK, 0x07);
400 static int max98095_do_init(struct maxim_priv *priv,
401 enum en_max_audio_interface aif_id,
402 int sampling_rate, int mclk_freq,
407 ret = max98095_setup_interface(priv, aif_id);
409 debug("%s: max98095 setup interface failed\n", __func__);
413 ret = max98095_set_sysclk(priv, mclk_freq);
415 debug("%s: max98095 codec set sys clock failed\n", __func__);
419 ret = max98095_hw_params(priv, aif_id, sampling_rate,
423 ret = max98095_set_fmt(priv, SND_SOC_DAIFMT_I2S |
424 SND_SOC_DAIFMT_NB_NF |
425 SND_SOC_DAIFMT_CBS_CFS,
432 static int max98095_set_params(struct udevice *dev, int interface, int rate,
433 int mclk_freq, int bits_per_sample,
436 struct maxim_priv *priv = dev_get_priv(dev);
438 return max98095_do_init(priv, interface, rate, mclk_freq,
442 static int max98095_probe(struct udevice *dev)
444 struct maxim_priv *priv = dev_get_priv(dev);
448 ret = max98095_device_init(priv);
450 debug("%s: max98095 codec chip init failed\n", __func__);
457 static const struct audio_codec_ops max98095_ops = {
458 .set_params = max98095_set_params,
461 static const struct udevice_id max98095_ids[] = {
462 { .compatible = "maxim,max98095" },
466 U_BOOT_DRIVER(max98095) = {
468 .id = UCLASS_AUDIO_CODEC,
469 .of_match = max98095_ids,
470 .probe = max98095_probe,
471 .ops = &max98095_ops,
472 .priv_auto_alloc_size = sizeof(struct maxim_priv),