1 // SPDX-License-Identifier: GPL-2.0+
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011 Maxim Integrated Products
9 #include <audio_codec.h>
16 #include "maxim_codec.h"
20 * Sets hw params for max98090
22 * @priv: max98090 information pointer
23 * @rate: Sampling rate
24 * @bits_per_sample: Bits per sample
26 * @return -EIO for error, 0 for success.
28 int max98090_hw_params(struct maxim_priv *priv, unsigned int rate,
29 unsigned int bits_per_sample)
34 switch (bits_per_sample) {
36 maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
37 error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT,
39 maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
42 debug("%s: Illegal bits per sample %d.\n",
43 __func__, bits_per_sample);
47 /* Update filter mode */
49 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
52 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
53 M98090_MODE_MASK, M98090_MODE_MASK);
55 /* Update sample rate mode */
57 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
60 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
61 M98090_DHF_MASK, M98090_DHF_MASK);
64 debug("%s: Error setting hardware params.\n", __func__);
73 * Configures Audio interface system clock for the given frequency
75 * @priv: max98090 information
76 * @freq: Sampling frequency in Hz
78 * @return -EIO for error, 0 for success.
80 int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq)
84 /* Requested clock frequency is already setup */
85 if (freq == priv->sysclk)
88 /* Setup clocks for slave mode, and using the PLL
89 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
90 * 0x02 (when master clk is 20MHz to 40MHz)..
91 * 0x03 (when master clk is 40MHz to 60MHz)..
93 if (freq >= 10000000 && freq < 20000000) {
94 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
96 } else if (freq >= 20000000 && freq < 40000000) {
97 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
99 } else if (freq >= 40000000 && freq < 60000000) {
100 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
103 debug("%s: Invalid master clock frequency\n", __func__);
107 debug("%s: Clock at %uHz\n", __func__, freq);
118 * Sets Max98090 I2S format
120 * @priv: max98090 information
121 * @fmt: i2S format - supports a subset of the options defined in i2s.h.
123 * @return -EIO for error, 0 for success.
125 int max98090_set_fmt(struct maxim_priv *priv, int fmt)
130 if (fmt == priv->fmt)
135 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
136 case SND_SOC_DAIFMT_CBS_CFS:
137 /* Set to slave mode PLL - MAS mode off */
138 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB,
140 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB,
142 error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE,
143 M98090_USE_M1_MASK, 0);
145 case SND_SOC_DAIFMT_CBM_CFM:
146 /* Set to master mode */
147 debug("Master mode not supported\n");
149 case SND_SOC_DAIFMT_CBS_CFM:
150 case SND_SOC_DAIFMT_CBM_CFS:
152 debug("%s: Clock mode unsupported\n", __func__);
156 error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval);
159 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
160 case SND_SOC_DAIFMT_I2S:
161 regval |= M98090_DLY_MASK;
163 case SND_SOC_DAIFMT_LEFT_J:
165 case SND_SOC_DAIFMT_RIGHT_J:
166 regval |= M98090_RJ_MASK;
168 case SND_SOC_DAIFMT_DSP_A:
169 /* Not supported mode */
171 debug("%s: Unrecognized format.\n", __func__);
175 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
176 case SND_SOC_DAIFMT_NB_NF:
178 case SND_SOC_DAIFMT_NB_IF:
179 regval |= M98090_WCI_MASK;
181 case SND_SOC_DAIFMT_IB_NF:
182 regval |= M98090_BCI_MASK;
184 case SND_SOC_DAIFMT_IB_IF:
185 regval |= M98090_BCI_MASK | M98090_WCI_MASK;
188 debug("%s: Unrecognized inversion settings.\n", __func__);
192 error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval);
195 debug("%s: Error setting i2s format.\n", __func__);
203 * resets the audio codec
205 * @priv: max98090 information
206 * @return -EIO for error, 0 for success.
208 static int max98090_reset(struct maxim_priv *priv)
213 * Gracefully reset the DSP core and the codec hardware in a proper
216 ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET,
217 M98090_SWRESET_MASK);
219 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
228 * Initialise max98090 codec device
230 * @priv: max98090 information
232 * @return -EIO for error, 0 for success.
234 int max98090_device_init(struct maxim_priv *priv)
239 /* reset the codec, the DSP core, and disable all interrupts */
240 error = max98090_reset(priv);
246 /* initialize private data */
251 error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id);
253 debug("%s: Failure reading hardware revision: %d\n",
257 debug("%s: Hardware revision: %d\n", __func__, id);
262 static int max98090_setup_interface(struct maxim_priv *priv)
267 /* Reading interrupt status to clear them */
268 error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id);
270 error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL,
272 error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL,
273 M98090_VCM_MODE_MASK);
275 error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1);
276 error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2);
278 error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25);
279 error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25);
281 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0);
282 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0);
283 error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0);
284 error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0);
285 error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
287 error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN,
289 error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE,
290 M98090_HPREN_MASK | M98090_HPLEN_MASK |
291 M98090_SPREN_MASK | M98090_SPLEN_MASK |
292 M98090_DAREN_MASK | M98090_DALEN_MASK);
293 error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
294 M98090_SDOEN_MASK | M98090_SDIEN_MASK);
302 static int max98090_do_init(struct maxim_priv *priv, int sampling_rate,
303 int mclk_freq, int bits_per_sample)
307 ret = max98090_setup_interface(priv);
309 debug("%s: max98090 setup interface failed\n", __func__);
313 ret = max98090_set_sysclk(priv, mclk_freq);
315 debug("%s: max98090 codec set sys clock failed\n", __func__);
319 ret = max98090_hw_params(priv, sampling_rate, bits_per_sample);
322 ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S |
323 SND_SOC_DAIFMT_NB_NF |
324 SND_SOC_DAIFMT_CBS_CFS);
330 static int max98090_set_params(struct udevice *dev, int interface, int rate,
331 int mclk_freq, int bits_per_sample,
334 struct maxim_priv *priv = dev_get_priv(dev);
336 return max98090_do_init(priv, rate, mclk_freq, bits_per_sample);
339 static int max98090_probe(struct udevice *dev)
341 struct maxim_priv *priv = dev_get_priv(dev);
345 ret = max98090_device_init(priv);
347 debug("%s: max98090 codec chip init failed\n", __func__);
354 static const struct audio_codec_ops max98090_ops = {
355 .set_params = max98090_set_params,
358 static const struct udevice_id max98090_ids[] = {
359 { .compatible = "maxim,max98090" },
363 U_BOOT_DRIVER(max98090) = {
365 .id = UCLASS_AUDIO_CODEC,
366 .of_match = max98090_ids,
367 .probe = max98090_probe,
368 .ops = &max98090_ops,
369 .priv_auto_alloc_size = sizeof(struct maxim_priv),