1 // SPDX-License-Identifier: GPL-2.0+
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011 Maxim Integrated Products
9 #include <audio_codec.h>
17 #include <asm/arch/clk.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/power.h>
20 #include "maxim_codec.h"
24 * Sets hw params for max98090
26 * @priv: max98090 information pointer
27 * @rate: Sampling rate
28 * @bits_per_sample: Bits per sample
30 * @return -EIO for error, 0 for success.
32 int max98090_hw_params(struct maxim_priv *priv, unsigned int rate,
33 unsigned int bits_per_sample)
38 switch (bits_per_sample) {
40 maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
41 error = maxim_bic_or(priv, M98090_REG_INTERFACE_FORMAT,
43 maxim_i2c_read(priv, M98090_REG_INTERFACE_FORMAT, &value);
46 debug("%s: Illegal bits per sample %d.\n",
47 __func__, bits_per_sample);
51 /* Update filter mode */
53 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
56 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
57 M98090_MODE_MASK, M98090_MODE_MASK);
59 /* Update sample rate mode */
61 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
64 error |= maxim_bic_or(priv, M98090_REG_FILTER_CONFIG,
65 M98090_DHF_MASK, M98090_DHF_MASK);
68 debug("%s: Error setting hardware params.\n", __func__);
77 * Configures Audio interface system clock for the given frequency
79 * @priv: max98090 information
80 * @freq: Sampling frequency in Hz
82 * @return -EIO for error, 0 for success.
84 int max98090_set_sysclk(struct maxim_priv *priv, unsigned int freq)
88 /* Requested clock frequency is already setup */
89 if (freq == priv->sysclk)
92 /* Setup clocks for slave mode, and using the PLL
93 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
94 * 0x02 (when master clk is 20MHz to 40MHz)..
95 * 0x03 (when master clk is 40MHz to 60MHz)..
97 if (freq >= 10000000 && freq < 20000000) {
98 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
100 } else if (freq >= 20000000 && freq < 40000000) {
101 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
103 } else if (freq >= 40000000 && freq < 60000000) {
104 error = maxim_i2c_write(priv, M98090_REG_SYSTEM_CLOCK,
107 debug("%s: Invalid master clock frequency\n", __func__);
111 debug("%s: Clock at %uHz\n", __func__, freq);
122 * Sets Max98090 I2S format
124 * @priv: max98090 information
125 * @fmt: i2S format - supports a subset of the options defined in i2s.h.
127 * @return -EIO for error, 0 for success.
129 int max98090_set_fmt(struct maxim_priv *priv, int fmt)
134 if (fmt == priv->fmt)
139 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
140 case SND_SOC_DAIFMT_CBS_CFS:
141 /* Set to slave mode PLL - MAS mode off */
142 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB,
144 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB,
146 error |= maxim_bic_or(priv, M98090_REG_CLOCK_MODE,
147 M98090_USE_M1_MASK, 0);
149 case SND_SOC_DAIFMT_CBM_CFM:
150 /* Set to master mode */
151 debug("Master mode not supported\n");
153 case SND_SOC_DAIFMT_CBS_CFM:
154 case SND_SOC_DAIFMT_CBM_CFS:
156 debug("%s: Clock mode unsupported\n", __func__);
160 error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, regval);
163 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
164 case SND_SOC_DAIFMT_I2S:
165 regval |= M98090_DLY_MASK;
167 case SND_SOC_DAIFMT_LEFT_J:
169 case SND_SOC_DAIFMT_RIGHT_J:
170 regval |= M98090_RJ_MASK;
172 case SND_SOC_DAIFMT_DSP_A:
173 /* Not supported mode */
175 debug("%s: Unrecognized format.\n", __func__);
179 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
180 case SND_SOC_DAIFMT_NB_NF:
182 case SND_SOC_DAIFMT_NB_IF:
183 regval |= M98090_WCI_MASK;
185 case SND_SOC_DAIFMT_IB_NF:
186 regval |= M98090_BCI_MASK;
188 case SND_SOC_DAIFMT_IB_IF:
189 regval |= M98090_BCI_MASK | M98090_WCI_MASK;
192 debug("%s: Unrecognized inversion settings.\n", __func__);
196 error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, regval);
199 debug("%s: Error setting i2s format.\n", __func__);
207 * resets the audio codec
209 * @priv: max98090 information
210 * @return -EIO for error, 0 for success.
212 static int max98090_reset(struct maxim_priv *priv)
217 * Gracefully reset the DSP core and the codec hardware in a proper
220 ret = maxim_i2c_write(priv, M98090_REG_SOFTWARE_RESET,
221 M98090_SWRESET_MASK);
223 debug("%s: Failed to reset DSP: %d\n", __func__, ret);
232 * Initialise max98090 codec device
234 * @priv: max98090 information
236 * @return -EIO for error, 0 for success.
238 int max98090_device_init(struct maxim_priv *priv)
243 /* Enable codec clock */
246 /* reset the codec, the DSP core, and disable all interrupts */
247 error = max98090_reset(priv);
253 /* initialize private data */
258 error = maxim_i2c_read(priv, M98090_REG_REVISION_ID, &id);
260 debug("%s: Failure reading hardware revision: %d\n",
264 debug("%s: Hardware revision: %d\n", __func__, id);
269 static int max98090_setup_interface(struct maxim_priv *priv)
274 /* Reading interrupt status to clear them */
275 error = maxim_i2c_read(priv, M98090_REG_DEVICE_STATUS, &id);
277 error |= maxim_i2c_write(priv, M98090_REG_DAC_CONTROL,
279 error |= maxim_i2c_write(priv, M98090_REG_BIAS_CONTROL,
280 M98090_VCM_MODE_MASK);
282 error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_MIXER, 0x1);
283 error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_MIXER, 0x2);
285 error |= maxim_i2c_write(priv, M98090_REG_LEFT_SPK_VOLUME, 0x25);
286 error |= maxim_i2c_write(priv, M98090_REG_RIGHT_SPK_VOLUME, 0x25);
288 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_MSB, 0x0);
289 error |= maxim_i2c_write(priv, M98090_REG_CLOCK_RATIO_NI_LSB, 0x0);
290 error |= maxim_i2c_write(priv, M98090_REG_MASTER_MODE, 0x0);
291 error |= maxim_i2c_write(priv, M98090_REG_INTERFACE_FORMAT, 0x0);
292 error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
294 error |= maxim_i2c_write(priv, M98090_REG_DEVICE_SHUTDOWN,
296 error |= maxim_i2c_write(priv, M98090_REG_OUTPUT_ENABLE,
297 M98090_HPREN_MASK | M98090_HPLEN_MASK |
298 M98090_SPREN_MASK | M98090_SPLEN_MASK |
299 M98090_DAREN_MASK | M98090_DALEN_MASK);
300 error |= maxim_i2c_write(priv, M98090_REG_IO_CONFIGURATION,
301 M98090_SDOEN_MASK | M98090_SDIEN_MASK);
309 static int max98090_do_init(struct maxim_priv *priv, int sampling_rate,
310 int mclk_freq, int bits_per_sample)
314 ret = max98090_setup_interface(priv);
316 debug("%s: max98090 setup interface failed\n", __func__);
320 ret = max98090_set_sysclk(priv, mclk_freq);
322 debug("%s: max98090 codec set sys clock failed\n", __func__);
326 ret = max98090_hw_params(priv, sampling_rate, bits_per_sample);
329 ret = max98090_set_fmt(priv, SND_SOC_DAIFMT_I2S |
330 SND_SOC_DAIFMT_NB_NF |
331 SND_SOC_DAIFMT_CBS_CFS);
337 static int max98090_set_params(struct udevice *dev, int interface, int rate,
338 int mclk_freq, int bits_per_sample,
341 struct maxim_priv *priv = dev_get_priv(dev);
343 return max98090_do_init(priv, rate, mclk_freq, bits_per_sample);
346 static int max98090_probe(struct udevice *dev)
348 struct maxim_priv *priv = dev_get_priv(dev);
352 ret = max98090_device_init(priv);
354 debug("%s: max98090 codec chip init failed\n", __func__);
361 static const struct audio_codec_ops max98090_ops = {
362 .set_params = max98090_set_params,
365 static const struct udevice_id max98090_ids[] = {
366 { .compatible = "maxim,max98090" },
370 U_BOOT_DRIVER(max98090) = {
372 .id = UCLASS_AUDIO_CODEC,
373 .of_match = max98090_ids,
374 .probe = max98090_probe,
375 .ops = &max98090_ops,
376 .priv_auto_alloc_size = sizeof(struct maxim_priv),