1 // SPDX-License-Identifier: GPL-2.0+
3 * max98088.c -- MAX98088 ALSA SoC Audio driver
5 * Copyright 2010 Maxim Integrated Products
7 * Modified for U-Boot by Chih-Chung Chang (chihchung@chromium.org),
8 * following the changes made in max98095.c
12 #include <audio_codec.h>
19 #include "maxim_codec.h"
22 /* codec mclk clock divider coefficients. Index 0 is reserved. */
23 static const int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000,
24 44100, 48000, 88200, 96000};
27 * codec mclk clock divider coefficients based on sampling rate
29 * @param rate sampling rate
30 * @param value address of indexvalue to be stored
32 * @return 0 for success or negative error code.
34 static int rate_value(int rate, u8 *value)
38 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
39 if (rate_table[i] >= rate) {
50 * Sets hw params for max98088
52 * @priv: max98088 information pointer
53 * @rate: Sampling rate
54 * @bits_per_sample: Bits per sample
56 * @return -EIO for error, 0 for success.
58 int max98088_hw_params(struct maxim_priv *priv, unsigned int rate,
59 unsigned int bits_per_sample)
64 switch (bits_per_sample) {
66 error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
70 error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
71 M98088_DAI_WS, M98088_DAI_WS);
74 debug("%s: Illegal bits per sample %d.\n",
75 __func__, bits_per_sample);
79 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, 0);
81 if (rate_value(rate, ®val)) {
82 debug("%s: Failed to set sample rate to %d.\n",
87 error |= maxim_bic_or(priv, M98088_REG_DAI1_CLKMODE,
88 M98088_CLKMODE_MASK, regval << 4);
91 /* Update sample rate mode */
93 error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
96 error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
97 M98088_DAI_DHF, M98088_DAI_DHF);
99 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN,
103 debug("%s: Error setting hardware params.\n", __func__);
112 * Configures Audio interface system clock for the given frequency
114 * @priv: max98088 information
115 * @freq: Sampling frequency in Hz
117 * @return -EIO for error, 0 for success.
119 int max98088_set_sysclk(struct maxim_priv *priv, unsigned int freq)
124 /* Requested clock frequency is already setup */
125 if (freq == priv->sysclk)
129 * Setup clocks for slave mode, and using the PLL
130 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
131 * 0x02 (when master clk is 20MHz to 30MHz)..
133 if (freq >= 10000000 && freq < 20000000) {
134 error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x10);
135 } else if ((freq >= 20000000) && (freq < 30000000)) {
136 error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x20);
138 debug("%s: Invalid master clock frequency\n", __func__);
142 error |= maxim_i2c_read(priv, M98088_REG_PWR_SYS, &pwr);
143 if (pwr & M98088_SHDNRUN) {
144 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
146 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
147 M98088_SHDNRUN, M98088_SHDNRUN);
150 debug("%s: Clock at %uHz\n", __func__, freq);
160 * Sets Max98090 I2S format
162 * @priv: max98088 information
163 * @fmt: i2S format - supports a subset of the options defined in i2s.h.
165 * @return -EIO for error, 0 for success.
167 int max98088_set_fmt(struct maxim_priv *priv, int fmt)
173 if (fmt == priv->fmt)
178 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
179 case SND_SOC_DAIFMT_CBS_CFS:
181 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_HI,
183 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_LO,
186 case SND_SOC_DAIFMT_CBM_CFM:
187 /* Set to master mode */
188 reg14val |= M98088_DAI_MAS;
190 case SND_SOC_DAIFMT_CBS_CFM:
191 case SND_SOC_DAIFMT_CBM_CFS:
193 debug("%s: Clock mode unsupported\n", __func__);
197 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
198 case SND_SOC_DAIFMT_I2S:
199 reg14val |= M98088_DAI_DLY;
201 case SND_SOC_DAIFMT_LEFT_J:
204 debug("%s: Unrecognized format.\n", __func__);
208 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
209 case SND_SOC_DAIFMT_NB_NF:
211 case SND_SOC_DAIFMT_NB_IF:
212 reg14val |= M98088_DAI_WCI;
214 case SND_SOC_DAIFMT_IB_NF:
215 reg14val |= M98088_DAI_BCI;
217 case SND_SOC_DAIFMT_IB_IF:
218 reg14val |= M98088_DAI_BCI | M98088_DAI_WCI;
221 debug("%s: Unrecognized inversion settings.\n", __func__);
225 error |= maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
226 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
227 M98088_DAI_WCI, reg14val);
228 reg15val = M98088_DAI_BSEL64;
229 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLOCK, reg15val);
232 debug("%s: Error setting i2s format.\n", __func__);
240 * max98088_reset() - reset the audio codec
242 * @priv: max98088 information
243 * @return -EIO for error, 0 for success.
245 static int max98088_reset(struct maxim_priv *priv)
251 * Reset to hardware default for registers, as there is not a soft
252 * reset hardware control register.
254 for (i = M98088_REG_IRQ_ENABLE; i <= M98088_REG_PWR_SYS; i++) {
256 case M98088_REG_BIAS_CNTL:
259 case M98088_REG_DAC_BIAS2:
265 ret = maxim_i2c_write(priv, i, val);
267 debug("%s: Failed to reset: %d\n", __func__, ret);
276 * max98088_device_init() - Initialise max98088 codec device
278 * @priv: max98088 information
280 * @return -EIO for error, 0 for success.
282 static int max98088_device_init(struct maxim_priv *priv)
287 /* reset the codec, the DSP core, and disable all interrupts */
288 error = max98088_reset(priv);
294 /* initialize private data */
299 error = maxim_i2c_read(priv, M98088_REG_REV_ID, &id);
301 debug("%s: Failure reading hardware revision: %d\n",
305 debug("%s: Hardware revision: %d\n", __func__, id);
310 static int max98088_setup_interface(struct maxim_priv *priv)
314 /* Reading interrupt status to clear them */
315 error = maxim_i2c_write(priv, M98088_REG_PWR_SYS, M98088_PWRSV);
316 error |= maxim_i2c_write(priv, M98088_REG_IRQ_ENABLE, 0x00);
319 * initialize registers to hardware default configuring audio
322 error |= maxim_i2c_write(priv, M98088_REG_MIX_DAC,
323 M98088_DAI1L_TO_DACL | M98088_DAI1R_TO_DACR);
324 error |= maxim_i2c_write(priv, M98088_REG_BIAS_CNTL, 0xF0);
325 error |= maxim_i2c_write(priv, M98088_REG_DAC_BIAS2, 0x0F);
326 error |= maxim_i2c_write(priv, M98088_REG_DAI1_IOCFG,
327 M98088_S2NORMAL | M98088_SDATA);
330 * route DACL and DACR output to headphone and speakers
331 * Ordering: DACL, DACR, DACL, DACR
333 error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_LEFT, 1);
334 error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_RIGHT, 1);
335 error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_LEFT, 1);
336 error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_RIGHT, 1);
338 /* set volume: -12db */
339 error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_L, 0x0f);
340 error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_R, 0x0f);
342 /* set volume: -22db */
343 error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_L, 0x0d);
344 error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_R, 0x0d);
347 error |= maxim_i2c_write(priv, M98088_REG_PWR_EN_OUT,
348 M98088_HPLEN | M98088_HPREN | M98088_SPLEN |
349 M98088_SPREN | M98088_DALEN | M98088_DAREN);
356 static int max98088_do_init(struct maxim_priv *priv, int sampling_rate,
357 int mclk_freq, int bits_per_sample)
361 ret = max98088_setup_interface(priv);
363 debug("%s: max98088 setup interface failed\n", __func__);
367 ret = max98088_set_sysclk(priv, mclk_freq);
369 debug("%s: max98088 codec set sys clock failed\n", __func__);
373 ret = max98088_hw_params(priv, sampling_rate, bits_per_sample);
376 ret = max98088_set_fmt(priv, SND_SOC_DAIFMT_I2S |
377 SND_SOC_DAIFMT_NB_NF |
378 SND_SOC_DAIFMT_CBS_CFS);
384 static int max98088_set_params(struct udevice *dev, int interface, int rate,
385 int mclk_freq, int bits_per_sample,
388 struct maxim_priv *priv = dev_get_priv(dev);
390 return max98088_do_init(priv, rate, mclk_freq, bits_per_sample);
393 static int max98088_probe(struct udevice *dev)
395 struct maxim_priv *priv = dev_get_priv(dev);
399 ret = max98088_device_init(priv);
401 debug("%s: max98088 codec chip init failed\n", __func__);
408 static const struct audio_codec_ops max98088_ops = {
409 .set_params = max98088_set_params,
412 static const struct udevice_id max98088_ids[] = {
413 { .compatible = "maxim,max98088" },
417 U_BOOT_DRIVER(max98088) = {
419 .id = UCLASS_AUDIO_CODEC,
420 .of_match = max98088_ids,
421 .probe = max98088_probe,
422 .ops = &max98088_ops,
423 .priv_auto_alloc_size = sizeof(struct maxim_priv),