1 // SPDX-License-Identifier: GPL-2.0+
3 * max98088.c -- MAX98088 ALSA SoC Audio driver
5 * Copyright 2010 Maxim Integrated Products
7 * Modified for U-Boot by Chih-Chung Chang (chihchung@chromium.org),
8 * following the changes made in max98095.c
12 #include <audio_codec.h>
20 #include <asm/arch/clk.h>
21 #include <asm/arch/cpu.h>
22 #include <asm/arch/power.h>
23 #include "maxim_codec.h"
26 /* codec mclk clock divider coefficients. Index 0 is reserved. */
27 static const int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000,
28 44100, 48000, 88200, 96000};
31 * codec mclk clock divider coefficients based on sampling rate
33 * @param rate sampling rate
34 * @param value address of indexvalue to be stored
36 * @return 0 for success or negative error code.
38 static int rate_value(int rate, u8 *value)
42 for (i = 1; i < ARRAY_SIZE(rate_table); i++) {
43 if (rate_table[i] >= rate) {
54 * Sets hw params for max98088
56 * @priv: max98088 information pointer
57 * @rate: Sampling rate
58 * @bits_per_sample: Bits per sample
60 * @return -EIO for error, 0 for success.
62 int max98088_hw_params(struct maxim_priv *priv, unsigned int rate,
63 unsigned int bits_per_sample)
68 switch (bits_per_sample) {
70 error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
74 error = maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
75 M98088_DAI_WS, M98088_DAI_WS);
78 debug("%s: Illegal bits per sample %d.\n",
79 __func__, bits_per_sample);
83 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN, 0);
85 if (rate_value(rate, ®val)) {
86 debug("%s: Failed to set sample rate to %d.\n",
91 error |= maxim_bic_or(priv, M98088_REG_DAI1_CLKMODE,
92 M98088_CLKMODE_MASK, regval << 4);
95 /* Update sample rate mode */
97 error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
100 error |= maxim_bic_or(priv, M98088_REG_DAI1_FILTERS,
101 M98088_DAI_DHF, M98088_DAI_DHF);
103 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS, M98088_SHDNRUN,
107 debug("%s: Error setting hardware params.\n", __func__);
116 * Configures Audio interface system clock for the given frequency
118 * @priv: max98088 information
119 * @freq: Sampling frequency in Hz
121 * @return -EIO for error, 0 for success.
123 int max98088_set_sysclk(struct maxim_priv *priv, unsigned int freq)
128 /* Requested clock frequency is already setup */
129 if (freq == priv->sysclk)
133 * Setup clocks for slave mode, and using the PLL
134 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
135 * 0x02 (when master clk is 20MHz to 30MHz)..
137 if (freq >= 10000000 && freq < 20000000) {
138 error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x10);
139 } else if ((freq >= 20000000) && (freq < 30000000)) {
140 error = maxim_i2c_write(priv, M98088_REG_SYS_CLK, 0x20);
142 debug("%s: Invalid master clock frequency\n", __func__);
146 error |= maxim_i2c_read(priv, M98088_REG_PWR_SYS, &pwr);
147 if (pwr & M98088_SHDNRUN) {
148 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
150 error |= maxim_bic_or(priv, M98088_REG_PWR_SYS,
151 M98088_SHDNRUN, M98088_SHDNRUN);
154 debug("%s: Clock at %uHz\n", __func__, freq);
164 * Sets Max98090 I2S format
166 * @priv: max98088 information
167 * @fmt: i2S format - supports a subset of the options defined in i2s.h.
169 * @return -EIO for error, 0 for success.
171 int max98088_set_fmt(struct maxim_priv *priv, int fmt)
177 if (fmt == priv->fmt)
182 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
183 case SND_SOC_DAIFMT_CBS_CFS:
185 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_HI,
187 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLKCFG_LO,
190 case SND_SOC_DAIFMT_CBM_CFM:
191 /* Set to master mode */
192 reg14val |= M98088_DAI_MAS;
194 case SND_SOC_DAIFMT_CBS_CFM:
195 case SND_SOC_DAIFMT_CBM_CFS:
197 debug("%s: Clock mode unsupported\n", __func__);
201 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
202 case SND_SOC_DAIFMT_I2S:
203 reg14val |= M98088_DAI_DLY;
205 case SND_SOC_DAIFMT_LEFT_J:
208 debug("%s: Unrecognized format.\n", __func__);
212 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
213 case SND_SOC_DAIFMT_NB_NF:
215 case SND_SOC_DAIFMT_NB_IF:
216 reg14val |= M98088_DAI_WCI;
218 case SND_SOC_DAIFMT_IB_NF:
219 reg14val |= M98088_DAI_BCI;
221 case SND_SOC_DAIFMT_IB_IF:
222 reg14val |= M98088_DAI_BCI | M98088_DAI_WCI;
225 debug("%s: Unrecognized inversion settings.\n", __func__);
229 error |= maxim_bic_or(priv, M98088_REG_DAI1_FORMAT,
230 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
231 M98088_DAI_WCI, reg14val);
232 reg15val = M98088_DAI_BSEL64;
233 error |= maxim_i2c_write(priv, M98088_REG_DAI1_CLOCK, reg15val);
236 debug("%s: Error setting i2s format.\n", __func__);
244 * max98088_reset() - reset the audio codec
246 * @priv: max98088 information
247 * @return -EIO for error, 0 for success.
249 static int max98088_reset(struct maxim_priv *priv)
255 * Reset to hardware default for registers, as there is not a soft
256 * reset hardware control register.
258 for (i = M98088_REG_IRQ_ENABLE; i <= M98088_REG_PWR_SYS; i++) {
260 case M98088_REG_BIAS_CNTL:
263 case M98088_REG_DAC_BIAS2:
269 ret = maxim_i2c_write(priv, i, val);
271 debug("%s: Failed to reset: %d\n", __func__, ret);
280 * max98088_device_init() - Initialise max98088 codec device
282 * @priv: max98088 information
284 * @return -EIO for error, 0 for success.
286 static int max98088_device_init(struct maxim_priv *priv)
291 /* Enable codec clock */
294 /* reset the codec, the DSP core, and disable all interrupts */
295 error = max98088_reset(priv);
301 /* initialize private data */
306 error = maxim_i2c_read(priv, M98088_REG_REV_ID, &id);
308 debug("%s: Failure reading hardware revision: %d\n",
312 debug("%s: Hardware revision: %d\n", __func__, id);
317 static int max98088_setup_interface(struct maxim_priv *priv)
321 /* Reading interrupt status to clear them */
322 error = maxim_i2c_write(priv, M98088_REG_PWR_SYS, M98088_PWRSV);
323 error |= maxim_i2c_write(priv, M98088_REG_IRQ_ENABLE, 0x00);
326 * initialize registers to hardware default configuring audio
329 error |= maxim_i2c_write(priv, M98088_REG_MIX_DAC,
330 M98088_DAI1L_TO_DACL | M98088_DAI1R_TO_DACR);
331 error |= maxim_i2c_write(priv, M98088_REG_BIAS_CNTL, 0xF0);
332 error |= maxim_i2c_write(priv, M98088_REG_DAC_BIAS2, 0x0F);
333 error |= maxim_i2c_write(priv, M98088_REG_DAI1_IOCFG,
334 M98088_S2NORMAL | M98088_SDATA);
337 * route DACL and DACR output to headphone and speakers
338 * Ordering: DACL, DACR, DACL, DACR
340 error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_LEFT, 1);
341 error |= maxim_i2c_write(priv, M98088_REG_MIX_SPK_RIGHT, 1);
342 error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_LEFT, 1);
343 error |= maxim_i2c_write(priv, M98088_REG_MIX_HP_RIGHT, 1);
345 /* set volume: -12db */
346 error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_L, 0x0f);
347 error |= maxim_i2c_write(priv, M98088_REG_LVL_SPK_R, 0x0f);
349 /* set volume: -22db */
350 error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_L, 0x0d);
351 error |= maxim_i2c_write(priv, M98088_REG_LVL_HP_R, 0x0d);
354 error |= maxim_i2c_write(priv, M98088_REG_PWR_EN_OUT,
355 M98088_HPLEN | M98088_HPREN | M98088_SPLEN |
356 M98088_SPREN | M98088_DALEN | M98088_DAREN);
363 static int max98088_do_init(struct maxim_priv *priv, int sampling_rate,
364 int mclk_freq, int bits_per_sample)
368 ret = max98088_setup_interface(priv);
370 debug("%s: max98088 setup interface failed\n", __func__);
374 ret = max98088_set_sysclk(priv, mclk_freq);
376 debug("%s: max98088 codec set sys clock failed\n", __func__);
380 ret = max98088_hw_params(priv, sampling_rate, bits_per_sample);
383 ret = max98088_set_fmt(priv, SND_SOC_DAIFMT_I2S |
384 SND_SOC_DAIFMT_NB_NF |
385 SND_SOC_DAIFMT_CBS_CFS);
391 static int max98088_set_params(struct udevice *dev, int interface, int rate,
392 int mclk_freq, int bits_per_sample,
395 struct maxim_priv *priv = dev_get_priv(dev);
397 return max98088_do_init(priv, rate, mclk_freq, bits_per_sample);
400 static int max98088_probe(struct udevice *dev)
402 struct maxim_priv *priv = dev_get_priv(dev);
406 ret = max98088_device_init(priv);
408 debug("%s: max98088 codec chip init failed\n", __func__);
415 static const struct audio_codec_ops max98088_ops = {
416 .set_params = max98088_set_params,
419 static const struct udevice_id max98088_ids[] = {
420 { .compatible = "maxim,max98088" },
424 U_BOOT_DRIVER(max98088) = {
426 .id = UCLASS_AUDIO_CODEC,
427 .of_match = max98088_ids,
428 .probe = max98088_probe,
429 .ops = &max98088_ops,
430 .priv_auto_alloc_size = sizeof(struct maxim_priv),