2 * TI serdes driver for keystone2.
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/ti-common/keystone_serdes.h>
14 #define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
15 #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
16 #define SERDES_COMLANE_REGS 0x0a00
17 #define SERDES_WIZ_REGS 0x1fc0
19 #define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
20 #define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
21 #define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
22 #define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
23 #define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
24 #define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
25 #define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
27 #define SERDES_RESET BIT(28)
28 #define SERDES_LANE_RESET BIT(29)
29 #define SERDES_LANE_LOOPBACK BIT(30)
30 #define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10))
38 /* SERDES PHY lane enable configuration value, indexed by PHY interface */
39 static u32 serdes_cfg_lane_enable[] = {
40 0xf000f0c0, /* SGMII */
41 0xf0e9f038, /* PCSR */
44 /* SERDES PHY PLL enable configuration value, indexed by PHY interface */
45 static u32 serdes_cfg_pll_enable[] = {
46 0xe0000000, /* SGMII */
47 0xee000000, /* PCSR */
50 static struct serdes_cfg cfg_cmu_156p25m_5g[] = {
51 {0x0000, 0x00800000, 0xffff0000},
52 {0x0014, 0x00008282, 0x0000ffff},
53 {0x0060, 0x00142438, 0x00ffffff},
54 {0x0064, 0x00c3c700, 0x00ffff00},
55 {0x0078, 0x0000c000, 0x0000ff00}
58 static struct serdes_cfg cfg_comlane_156p25m_5g[] = {
59 {0x0a00, 0x00000800, 0x0000ff00},
60 {0x0a08, 0x38a20000, 0xffff0000},
61 {0x0a30, 0x008a8a00, 0x00ffff00},
62 {0x0a84, 0x00000600, 0x0000ff00},
63 {0x0a94, 0x10000000, 0xff000000},
64 {0x0aa0, 0x81000000, 0xff000000},
65 {0x0abc, 0xff000000, 0xff000000},
66 {0x0ac0, 0x0000008b, 0x000000ff},
67 {0x0b08, 0x583f0000, 0xffff0000},
68 {0x0b0c, 0x0000004e, 0x000000ff}
71 static struct serdes_cfg cfg_lane_156p25mhz_5g[] = {
72 {0x0004, 0x38000080, 0xff0000ff},
73 {0x0008, 0x00000000, 0x000000ff},
74 {0x000c, 0x02000000, 0xff000000},
75 {0x0010, 0x1b000000, 0xff000000},
76 {0x0014, 0x00006fb8, 0x0000ffff},
77 {0x0018, 0x758000e4, 0xffff00ff},
78 {0x00ac, 0x00004400, 0x0000ff00},
79 {0x002c, 0x00100800, 0x00ffff00},
80 {0x0080, 0x00820082, 0x00ff00ff},
81 {0x0084, 0x1d0f0385, 0xffffffff}
85 static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
87 writel(((readl(addr) & (~mask)) | (value & mask)), addr);
90 static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
94 for (i = 0; i < size; i++)
95 ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
98 static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
103 for (i = 0; i < size; i++)
104 ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
105 cfg_lane[i].val, cfg_lane[i].mask);
108 static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes)
112 ks2_serdes_cfg_setup(base, cfg_cmu_156p25m_5g,
113 ARRAY_SIZE(cfg_cmu_156p25m_5g));
114 ks2_serdes_cfg_setup(base, cfg_comlane_156p25m_5g,
115 ARRAY_SIZE(cfg_comlane_156p25m_5g));
117 for (i = 0; i < num_lanes; i++)
118 ks2_serdes_lane_config(base, cfg_lane_156p25mhz_5g,
119 ARRAY_SIZE(cfg_lane_156p25mhz_5g), i);
124 static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes)
126 /* Bring SerDes out of Reset */
127 ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET);
128 if (serdes->intf == SERDES_PHY_PCSR)
129 ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET);
131 /* Enable CMU and COMLANE */
132 ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff);
133 if (serdes->intf == SERDES_PHY_PCSR)
134 ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff);
136 ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff);
139 static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes)
141 writel(serdes_cfg_pll_enable[serdes->intf],
142 base + SERDES_PLL_CTL_REG);
145 static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane)
148 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
149 0x1, SERDES_LANE_RESET);
151 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
152 0x0, SERDES_LANE_RESET);
155 static void ks2_serdes_lane_enable(u32 base,
156 struct ks2_serdes *serdes, u32 lane)
158 /* Bring lane out of reset */
159 ks2_serdes_lane_reset(base, 0, lane);
161 writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf,
163 base + SERDES_LANE_CTL_STATUS_REG(lane));
165 /* Set NES bit if Loopback Enabled */
166 if (serdes->loopback)
167 ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane),
168 0x1, SERDES_LANE_LOOPBACK);
171 int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes)
176 /* The driver currently supports 5GBaud rate with ref clock 156.25MHz */
177 if (serdes->clk == SERDES_CLOCK_156P25M)
178 if (serdes->rate == SERDES_RATE_5G)
179 ret = ks2_serdes_init_156p25m_5g(base, num_lanes);
185 ks2_serdes_cmu_comlane_enable(base, serdes);
186 for (i = 0; i < num_lanes; i++)
187 ks2_serdes_lane_enable(base, serdes, i);
189 ks2_serdes_pll_enable(base, serdes);