drivers/soc/bcm/brcmstb/pm/s2-arm.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright © 2014-2017 Broadcom
   4  */
   5
   6 #include <linux/linkage.h>
   7 #include <asm/assembler.h>
   8
   9 #include "pm.h"
  10
  11         .text
  12         .align  3
  13
  14 #define AON_CTRL_REG            r10
  15 #define DDR_PHY_STATUS_REG      r11
  16
  17 /*
  18  * r0: AON_CTRL base address
  19  * r1: DDRY PHY PLL status register address
  20  */
  21 ENTRY(brcmstb_pm_do_s2)
  22         stmfd   sp!, {r4-r11, lr}
  23         mov     AON_CTRL_REG, r0
  24         mov     DDR_PHY_STATUS_REG, r1
  25
  26         /* Flush memory transactions */
  27         dsb
  28
  29         /* Cache DDR_PHY_STATUS_REG translation */
  30         ldr     r0, [DDR_PHY_STATUS_REG]
  31
  32         /* power down request */
  33         ldr     r0, =PM_S2_COMMAND
  34         ldr     r1, =0
  35         str     r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  36         ldr     r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  37         str     r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  38         ldr     r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  39
  40         /* Wait for interrupt */
  41         wfi
  42         nop
  43
  44         /* Bring MEMC back up */
  45 1:      ldr     r0, [DDR_PHY_STATUS_REG]
  46         ands    r0, #1
  47         beq     1b
  48
  49         /* Power-up handshake */
  50         ldr     r0, =1
  51         str     r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
  52         ldr     r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
  53
  54         ldr     r0, =0
  55         str     r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  56         ldr     r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
  57
  58         /* Return to caller */
  59         ldr     r0, =0
  60         ldmfd   sp!, {r4-r11, pc}
  61
  62         ENDPROC(brcmstb_pm_do_s2)
  63
  64         /* Place literal pool here */
  65         .ltorg
  66
  67 ENTRY(brcmstb_pm_do_s2_sz)
  68         .word   . - brcmstb_pm_do_s2