1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
39 . io = for the base address
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
55 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
56 . 07/25/01 Woojung Huh Modify for ADS Bitsy
57 . 04/25/01 Daris A Nevil Initial public release through SMSC
58 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
59 ----------------------------------------------------------------------------*/
66 #ifdef CONFIG_DRIVER_SMC91111
68 /* Use power-down feature of the chip */
73 static const char version[] =
74 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
78 /*------------------------------------------------------------------------
80 . Configuration options, for the experienced user to change.
82 -------------------------------------------------------------------------*/
85 . Wait time for memory to be free. This probably shouldn't be
86 . tuned that much, as waiting for this means nothing else happens
89 #define MEMORY_WAIT_TIME 16
93 #define PRINTK3(args...) printf(args)
95 #define PRINTK3(args...)
99 #define PRINTK2(args...) printf(args)
101 #define PRINTK2(args...)
105 #define PRINTK(args...) printf(args)
107 #define PRINTK(args...)
111 /*------------------------------------------------------------------------
113 . The internal workings of the driver. If you are changing anything
114 . here with the SMC stuff, you should have the datasheet and know
115 . what you are doing.
117 -------------------------------------------------------------------------*/
118 #define CARDNAME "LAN91C111"
120 /* Memory sizing constant */
121 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
123 #ifndef CONFIG_SMC91111_BASE
124 #define CONFIG_SMC91111_BASE 0x20000300
127 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
129 #define SMC_DEV_NAME "SMC91111"
130 #define SMC_PHY_ADDR 0x0000
131 #define SMC_ALLOC_MAX_TRY 5
132 #define SMC_TX_TIMEOUT 30
134 #define SMC_PHY_CLOCK_DELAY 1000
138 #ifdef CONFIG_SMC_USE_32_BIT
143 /*-----------------------------------------------------------------
145 . The driver can be entered at any of the following entry points.
147 .------------------------------------------------------------------ */
149 extern int eth_init(bd_t *bd);
150 extern void eth_halt(void);
151 extern int eth_rx(void);
152 extern int eth_send(volatile void *packet, int length);
159 . This is called by register_netdev(). It is responsible for
160 . checking the portlist for the SMC9000 series chipset. If it finds
161 . one, then it will initialize the device, find the hardware information,
162 . and sets up the appropriate device parameters.
163 . NOTE: Interrupts are *OFF* when this procedure is called.
165 . NB:This shouldn't be static since it is referred to externally.
170 . This is called by unregister_netdev(). It is responsible for
171 . cleaning up before the driver is finally unregistered and discarded.
173 void smc_destructor(void);
176 . The kernel calls this function when someone wants to use the device,
177 . typically 'ifconfig ethX up'.
179 static int smc_open(void);
183 . This is called by the kernel in response to 'ifconfig ethX down'. It
184 . is responsible for cleaning up everything that the open routine
185 . does, and maybe putting the card into a powerdown state.
187 static int smc_close(void);
190 . Configures the PHY through the MII Management interface
192 #ifndef CONFIG_SMC91111_EXT_PHY
193 static void smc_phy_configure(void);
194 #endif /* !CONFIG_SMC91111_EXT_PHY */
197 . This is a separate procedure to handle the receipt of a packet, to
198 . leave the interrupt code looking slightly cleaner
200 static int smc_rcv(void);
205 ------------------------------------------------------------
209 ------------------------------------------------------------
212 static char smc_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
215 * This function must be called before smc_open() if you want to override
216 * the default mac address.
219 void smc_set_mac_addr(const char *addr) {
222 for (i=0; i < sizeof(smc_mac_addr); i++){
223 smc_mac_addr[i] = addr[i];
228 * smc_get_macaddr is no longer used. If you want to override the default
229 * mac address, call smc_get_mac_addr as a part of the board initialisation.
233 void smc_get_macaddr( byte *addr ) {
234 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
235 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
239 for (i=0; i<6; i++) {
240 addr[0] = *(dnp1110_mac+0);
241 addr[1] = *(dnp1110_mac+1);
242 addr[2] = *(dnp1110_mac+2);
243 addr[3] = *(dnp1110_mac+3);
244 addr[4] = *(dnp1110_mac+4);
245 addr[5] = *(dnp1110_mac+5);
250 /***********************************************
251 * Show available memory *
252 ***********************************************/
253 void dump_memory_info(void)
258 old_bank = SMC_inw(BANK_SELECT)&0xF;
261 mem_info = SMC_inw( MIR_REG );
262 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
264 SMC_SELECT_BANK(old_bank);
267 . A rather simple routine to print out a packet for debugging purposes.
270 static void print_packet( byte *, int );
273 #define tx_done(dev) 1
277 /* this does a soft reset on the device */
278 static void smc_reset( void );
280 /* Enable Interrupts, Receive, and Transmit */
281 static void smc_enable( void );
283 /* this puts the device in an inactive state */
284 static void smc_shutdown( void );
286 /* Routines to Read and Write the PHY Registers across the
287 MII Management Interface
290 #ifndef CONFIG_SMC91111_EXT_PHY
291 static word smc_read_phy_register(byte phyreg);
292 static void smc_write_phy_register(byte phyreg, word phydata);
293 #endif /* !CONFIG_SMC91111_EXT_PHY */
296 static int poll4int( byte mask, int timeout ) {
297 int tmo = get_timer(0) + timeout * CFG_HZ;
299 word old_bank = SMC_inw(BSR_REG);
301 PRINTK2("Polling...\n");
303 while((SMC_inw(SMC91111_INT_REG) & mask) == 0)
305 if (get_timer(0) >= tmo) {
311 /* restore old bank selection */
312 SMC_SELECT_BANK(old_bank);
321 . Function: smc_reset( void )
323 . This sets the SMC91111 chip to its normal state, hopefully from whatever
324 . mess that any other DOS driver has put it in.
326 . Maybe I should reset more registers to defaults in here? SOFTRST should
330 . 1. send a SOFT RESET
331 . 2. wait for it to finish
332 . 3. enable autorelease mode
333 . 4. reset the memory management unit
334 . 5. clear all interrupts
337 static void smc_reset( void )
339 PRINTK2("%s:smc_reset\n", SMC_DEV_NAME);
341 /* This resets the registers mostly to defaults, but doesn't
342 affect EEPROM. That seems unnecessary */
343 SMC_SELECT_BANK( 0 );
344 SMC_outw( RCR_SOFTRST, RCR_REG );
346 /* Setup the Configuration Register */
347 /* This is necessary because the CONFIG_REG is not affected */
348 /* by a soft reset */
350 SMC_SELECT_BANK( 1 );
351 #if defined(CONFIG_SMC91111_EXT_PHY)
352 SMC_outw( CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
354 SMC_outw( CONFIG_DEFAULT, CONFIG_REG);
358 /* Release from possible power-down state */
359 /* Configuration register is not affected by Soft Reset */
360 SMC_outw( SMC_inw( CONFIG_REG ) | CONFIG_EPH_POWER_EN, CONFIG_REG );
362 SMC_SELECT_BANK( 0 );
364 /* this should pause enough for the chip to be happy */
367 /* Disable transmit and receive functionality */
368 SMC_outw( RCR_CLEAR, RCR_REG );
369 SMC_outw( TCR_CLEAR, TCR_REG );
371 /* set the control register */
372 SMC_SELECT_BANK( 1 );
373 SMC_outw( CTL_DEFAULT, CTL_REG );
376 SMC_SELECT_BANK( 2 );
377 SMC_outw( MC_RESET, MMU_CMD_REG );
378 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
379 udelay(1); /* Wait until not busy */
381 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
382 but this is a place where future chipsets _COULD_ break. Be wary
383 of issuing another MMU command right after this */
385 /* Disable all interrupts */
386 SMC_outb( 0, IM_REG );
390 . Function: smc_enable
391 . Purpose: let the chip talk to the outside work
393 . 1. Enable the transmitter
394 . 2. Enable the receiver
395 . 3. Enable interrupts
397 static void smc_enable()
399 PRINTK2("%s:smc_enable\n", SMC_DEV_NAME);
400 SMC_SELECT_BANK( 0 );
401 /* see the header file for options in TCR/RCR DEFAULT*/
402 SMC_outw( TCR_DEFAULT, TCR_REG );
403 SMC_outw( RCR_DEFAULT, RCR_REG );
406 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
410 . Function: smc_shutdown
411 . Purpose: closes down the SMC91xxx chip.
413 . 1. zero the interrupt mask
414 . 2. clear the enable receive flag
415 . 3. clear the enable xmit flags
418 . (1) maybe utilize power down mode.
419 . Why not yet? Because while the chip will go into power down mode,
420 . the manual says that it will wake up in response to any I/O requests
421 . in the register space. Empirical results do not show this working.
423 static void smc_shutdown()
425 PRINTK2(CARDNAME ":smc_shutdown\n");
427 /* no more interrupts for me */
428 SMC_SELECT_BANK( 2 );
429 SMC_outb( 0, IM_REG );
431 /* and tell the card to stay away from that nasty outside world */
432 SMC_SELECT_BANK( 0 );
433 SMC_outb( RCR_CLEAR, RCR_REG );
434 SMC_outb( TCR_CLEAR, TCR_REG );
439 . Function: smc_hardware_send_packet(struct net_device * )
441 . This sends the actual packet to the SMC9xxx chip.
444 . First, see if a saved_skb is available.
445 . ( this should NOT be called if there is no 'saved_skb'
446 . Now, find the packet number that the chip allocated
447 . Point the data pointers at it in memory
448 . Set the length word in the chip's memory
449 . Dump the packet to chip memory
450 . Check if a last byte is needed ( odd length packet )
451 . if so, set the control flag right
452 . Tell the card to send it
453 . Enable the transmit interrupt, so I know if it failed
454 . Free the kernel data if I actually sent it.
456 static int smc_send_packet(volatile void *packet, int packet_length)
459 unsigned long ioaddr;
468 PRINTK3("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
470 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
473 ** The MMU wants the number of pages to be the number of 256 bytes
474 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
476 ** The 91C111 ignores the size bits, but the code is left intact
477 ** for backwards and future compatibility.
479 ** Pkt size for allocating is data length +6 (for additional status
480 ** words, length and ctl!)
482 ** If odd size then last byte is included in this header.
484 numPages = ((length & 0xfffe) + 6);
485 numPages >>= 8; /* Divide by 256 */
488 printf("%s: Far too big packet error. \n", SMC_DEV_NAME);
492 /* now, try to allocate the memory */
493 SMC_SELECT_BANK( 2 );
494 SMC_outw( MC_ALLOC | numPages, MMU_CMD_REG );
496 /* FIXME: the ALLOC_INT bit never gets set *
497 * so the following will always give a *
498 * memory allocation error. *
499 * same code works in armboot though *
505 time_out = MEMORY_WAIT_TIME;
507 status = SMC_inb( SMC91111_INT_REG );
508 if ( status & IM_ALLOC_INT ) {
509 /* acknowledge the interrupt */
510 SMC_outb( IM_ALLOC_INT, SMC91111_INT_REG );
513 } while ( -- time_out );
516 PRINTK2("%s: memory allocation, try %d failed ...\n",
518 if (try < SMC_ALLOC_MAX_TRY)
524 PRINTK2("%s: memory allocation, try %d succeeded ...\n",
528 /* I can send the packet now.. */
530 ioaddr = SMC_BASE_ADDRESS;
532 buf = (byte *)packet;
534 /* If I get here, I _know_ there is a packet slot waiting for me */
535 packet_no = SMC_inb( AR_REG );
536 if ( packet_no & AR_FAILED ) {
537 /* or isn't there? BAD CHIP! */
538 printf("%s: Memory allocation failed. \n",
543 /* we have a packet address, so tell the card to use it */
544 SMC_outb( packet_no, PN_REG );
546 /* point to the beginning of the packet */
547 SMC_outw( PTR_AUTOINC , PTR_REG );
549 PRINTK3("%s: Trying to xmit packet of length %x\n",
550 SMC_DEV_NAME, length);
553 printf("Transmitting Packet\n");
554 print_packet( buf, length );
557 /* send the packet length ( +6 for status, length and ctl byte )
558 and the status word ( set to zeros ) */
560 SMC_outl( (length +6 ) << 16 , SMC91111_DATA_REG );
562 SMC_outw( 0, SMC91111_DATA_REG );
563 /* send the packet length ( +6 for status words, length, and ctl*/
564 SMC_outw( (length+6), SMC91111_DATA_REG );
567 /* send the actual data
568 . I _think_ it's faster to send the longs first, and then
569 . mop up by sending the last word. It depends heavily
570 . on alignment, at least on the 486. Maybe it would be
571 . a good idea to check which is optimal? But that could take
572 . almost as much time as is saved?
575 SMC_outsl(SMC91111_DATA_REG, buf, length >> 2 );
577 SMC_outw(*((word *)(buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG);
579 SMC_outsw(SMC91111_DATA_REG , buf, (length ) >> 1);
580 #endif /* USE_32_BIT */
582 /* Send the last byte, if there is one. */
583 if ( (length & 1) == 0 ) {
584 SMC_outw( 0, SMC91111_DATA_REG );
586 SMC_outw( buf[length -1 ] | 0x2000, SMC91111_DATA_REG );
589 /* and let the chipset deal with it */
590 SMC_outw( MC_ENQUEUE , MMU_CMD_REG );
592 /* poll for TX INT */
593 if (poll4int(IM_TX_INT, SMC_TX_TIMEOUT)) {
595 PRINTK2("%s: TX timeout, sending failed...\n",
599 SMC_outw(MC_FREEPKT, MMU_CMD_REG);
601 /* wait for MMU getting ready (low) */
602 while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
607 PRINTK2("MMU ready\n");
613 SMC_outw(IM_TX_INT, SMC91111_INT_REG);
614 PRINTK2("%s: Sent packet of length %d \n", SMC_DEV_NAME, length);
617 SMC_outw(MC_FREEPKT, MMU_CMD_REG);
619 /* wait for MMU getting ready (low) */
620 while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
625 PRINTK2("MMU ready\n");
633 /*-------------------------------------------------------------------------
635 | smc_destructor( struct net_device * dev )
637 | dev, pointer to the device structure
642 ---------------------------------------------------------------------------
644 void smc_destructor()
646 PRINTK2(CARDNAME ":smc_destructor\n");
651 * Open and Initialize the board
653 * Set up everything, reset the card, etc ..
656 static int smc_open()
658 int i; /* used to set hw ethernet address */
660 PRINTK2("%s:smc_open\n", SMC_DEV_NAME);
662 /* reset the hardware */
667 /* Configure the PHY */
668 #ifndef CONFIG_SMC91111_EXT_PHY
673 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
674 /* SMC_SELECT_BANK(0); */
675 /* SMC_outw(0, RPC_REG); */
678 for ( i = 0; i < 6; i += 2 ) {
681 address = smc_mac_addr[ i + 1 ] << 8 ;
682 address |= smc_mac_addr[ i ];
683 SMC_outw( address, ADDR0_REG + i );
686 for ( i = 0; i < 6; i ++ )
687 SMC_outb( smc_mac_addr[i], ADDR0_REG + i );
693 #if 0 /* dead code? -- wd */
702 for (__i = 0; __i < l; __i++) {
703 *(__b2 + __i) = *(dword *)(r+0x10000300);
709 /*-------------------------------------------------------------
711 . smc_rcv - receive a packet from the card
713 . There is ( at least ) a packet waiting to be read from
717 . o If an error, record it
718 . o otherwise, read in the packet
719 --------------------------------------------------------------
733 packet_number = SMC_inw( RXFIFO_REG );
735 if ( packet_number & RXFIFO_REMPTY ) {
740 PRINTK3("%s:smc_rcv\n", SMC_DEV_NAME);
741 /* start reading from the start of the packet */
742 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
744 /* First two words are status and packet_length */
746 stat_len = SMC_inl(SMC91111_DATA_REG);
747 status = stat_len & 0xffff;
748 packet_length = stat_len >> 16;
750 status = SMC_inw( SMC91111_DATA_REG );
751 packet_length = SMC_inw( SMC91111_DATA_REG );
754 packet_length &= 0x07ff; /* mask off top bits */
756 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
758 if ( !(status & RS_ERRORS ) ){
759 /* Adjust for having already read the first two words */
760 packet_length -= 4; /*4; */
764 /* set odd length for bug in LAN91C111, */
765 /* which never sets RS_ODDFRAME */
770 PRINTK3(" Reading %d dwords (and %d bytes) \n",
771 packet_length >> 2, packet_length & 3 );
772 /* QUESTION: Like in the TX routine, do I want
773 to send the DWORDs or the bytes first, or some
774 mixture. A mixture might improve already slow PIO
776 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
777 /* read the left over bytes */
778 if (packet_length & 3) {
781 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
782 dword leftover = SMC_inl(SMC91111_DATA_REG);
783 for (i=0; i<(packet_length & 3); i++)
784 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
787 PRINTK3(" Reading %d words and %d byte(s) \n",
788 (packet_length >> 1 ), packet_length & 1 );
789 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
791 #endif /* USE_32_BIT */
794 printf("Receiving Packet\n");
795 print_packet( NetRxPackets[0], packet_length );
803 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
804 udelay(1); /* Wait until not busy */
806 /* error or good, tell the card to get rid of this packet */
807 SMC_outw( MC_RELEASE, MMU_CMD_REG );
809 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
810 udelay(1); /* Wait until not busy */
813 /* Pass the packet up to the protocol layers. */
814 NetReceive(NetRxPackets[0], packet_length);
815 return packet_length;
824 /*----------------------------------------------------
827 . this makes the board clean up everything that it can
828 . and not talk to the outside world. Caused by
829 . an 'ifconfig ethX down'
831 -----------------------------------------------------*/
832 static int smc_close()
834 PRINTK2("%s:smc_close\n", SMC_DEV_NAME);
836 /* clear everything */
844 /*------------------------------------------------------------
845 . Modify a bit in the LAN91C111 register set
846 .-------------------------------------------------------------*/
847 static word smc_modify_regbit(int bank, int ioaddr, int reg,
848 unsigned int bit, int val)
852 SMC_SELECT_BANK( bank );
854 regval = SMC_inw( reg );
860 SMC_outw( regval, 0 );
865 /*------------------------------------------------------------
866 . Retrieve a bit in the LAN91C111 register set
867 .-------------------------------------------------------------*/
868 static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
870 SMC_SELECT_BANK( bank );
871 if ( SMC_inw( reg ) & bit)
878 /*------------------------------------------------------------
879 . Modify a LAN91C111 register (word access only)
880 .-------------------------------------------------------------*/
881 static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
883 SMC_SELECT_BANK( bank );
884 SMC_outw( val, reg );
888 /*------------------------------------------------------------
889 . Retrieve a LAN91C111 register (word access only)
890 .-------------------------------------------------------------*/
891 static int smc_get_reg(int bank, int ioaddr, int reg)
893 SMC_SELECT_BANK( bank );
894 return(SMC_inw( reg ));
899 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
903 /*------------------------------------------------------------
904 . Debugging function for viewing MII Management serial bitstream
905 .-------------------------------------------------------------*/
906 static void smc_dump_mii_stream(byte* bits, int size)
911 for (i = 0; i < size; ++i)
917 for (i = 0; i < size; ++i)
919 if (bits[i] & MII_MDOE)
926 for (i = 0; i < size; ++i)
928 if (bits[i] & MII_MDO)
935 for (i = 0; i < size; ++i)
937 if (bits[i] & MII_MDI)
947 /*------------------------------------------------------------
948 . Reads a register from the MII Management serial interface
949 .-------------------------------------------------------------*/
950 #ifndef CONFIG_SMC91111_EXT_PHY
951 static word smc_read_phy_register(byte phyreg)
961 byte phyaddr = SMC_PHY_ADDR;
963 /* 32 consecutive ones on MDO to establish sync */
964 for (i = 0; i < 32; ++i)
965 bits[clk_idx++] = MII_MDOE | MII_MDO;
967 /* Start code <01> */
968 bits[clk_idx++] = MII_MDOE;
969 bits[clk_idx++] = MII_MDOE | MII_MDO;
971 /* Read command <10> */
972 bits[clk_idx++] = MII_MDOE | MII_MDO;
973 bits[clk_idx++] = MII_MDOE;
975 /* Output the PHY address, msb first */
977 for (i = 0; i < 5; ++i)
980 bits[clk_idx++] = MII_MDOE | MII_MDO;
982 bits[clk_idx++] = MII_MDOE;
984 /* Shift to next lowest bit */
988 /* Output the phy register number, msb first */
990 for (i = 0; i < 5; ++i)
993 bits[clk_idx++] = MII_MDOE | MII_MDO;
995 bits[clk_idx++] = MII_MDOE;
997 /* Shift to next lowest bit */
1001 /* Tristate and turnaround (2 bit times) */
1002 bits[clk_idx++] = 0;
1003 /*bits[clk_idx++] = 0; */
1005 /* Input starts at this bit time */
1006 input_idx = clk_idx;
1008 /* Will input 16 bits */
1009 for (i = 0; i < 16; ++i)
1010 bits[clk_idx++] = 0;
1012 /* Final clock bit */
1013 bits[clk_idx++] = 0;
1015 /* Save the current bank */
1016 oldBank = SMC_inw( BANK_SELECT );
1019 SMC_SELECT_BANK( 3 );
1021 /* Get the current MII register value */
1022 mii_reg = SMC_inw( MII_REG );
1024 /* Turn off all MII Interface bits */
1025 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
1027 /* Clock all 64 cycles */
1028 for (i = 0; i < sizeof bits; ++i)
1030 /* Clock Low - output data */
1031 SMC_outw( mii_reg | bits[i], MII_REG );
1032 udelay(SMC_PHY_CLOCK_DELAY);
1035 /* Clock Hi - input data */
1036 SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
1037 udelay(SMC_PHY_CLOCK_DELAY);
1038 bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
1041 /* Return to idle state */
1042 /* Set clock to low, data to low, and output tristated */
1043 SMC_outw( mii_reg, MII_REG );
1044 udelay(SMC_PHY_CLOCK_DELAY);
1046 /* Restore original bank select */
1047 SMC_SELECT_BANK( oldBank );
1049 /* Recover input data */
1051 for (i = 0; i < 16; ++i)
1055 if (bits[input_idx++] & MII_MDI)
1059 #if (SMC_DEBUG > 2 )
1060 printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1061 phyaddr, phyreg, phydata);
1062 smc_dump_mii_stream(bits, sizeof bits);
1069 /*------------------------------------------------------------
1070 . Writes a register to the MII Management serial interface
1071 .-------------------------------------------------------------*/
1072 static void smc_write_phy_register(byte phyreg, word phydata)
1080 byte phyaddr = SMC_PHY_ADDR;
1082 /* 32 consecutive ones on MDO to establish sync */
1083 for (i = 0; i < 32; ++i)
1084 bits[clk_idx++] = MII_MDOE | MII_MDO;
1086 /* Start code <01> */
1087 bits[clk_idx++] = MII_MDOE;
1088 bits[clk_idx++] = MII_MDOE | MII_MDO;
1090 /* Write command <01> */
1091 bits[clk_idx++] = MII_MDOE;
1092 bits[clk_idx++] = MII_MDOE | MII_MDO;
1094 /* Output the PHY address, msb first */
1096 for (i = 0; i < 5; ++i)
1099 bits[clk_idx++] = MII_MDOE | MII_MDO;
1101 bits[clk_idx++] = MII_MDOE;
1103 /* Shift to next lowest bit */
1107 /* Output the phy register number, msb first */
1109 for (i = 0; i < 5; ++i)
1112 bits[clk_idx++] = MII_MDOE | MII_MDO;
1114 bits[clk_idx++] = MII_MDOE;
1116 /* Shift to next lowest bit */
1120 /* Tristate and turnaround (2 bit times) */
1121 bits[clk_idx++] = 0;
1122 bits[clk_idx++] = 0;
1124 /* Write out 16 bits of data, msb first */
1126 for (i = 0; i < 16; ++i)
1129 bits[clk_idx++] = MII_MDOE | MII_MDO;
1131 bits[clk_idx++] = MII_MDOE;
1133 /* Shift to next lowest bit */
1137 /* Final clock bit (tristate) */
1138 bits[clk_idx++] = 0;
1140 /* Save the current bank */
1141 oldBank = SMC_inw( BANK_SELECT );
1144 SMC_SELECT_BANK( 3 );
1146 /* Get the current MII register value */
1147 mii_reg = SMC_inw( MII_REG );
1149 /* Turn off all MII Interface bits */
1150 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
1152 /* Clock all cycles */
1153 for (i = 0; i < sizeof bits; ++i)
1155 /* Clock Low - output data */
1156 SMC_outw( mii_reg | bits[i], MII_REG );
1157 udelay(SMC_PHY_CLOCK_DELAY);
1160 /* Clock Hi - input data */
1161 SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
1162 udelay(SMC_PHY_CLOCK_DELAY);
1163 bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
1166 /* Return to idle state */
1167 /* Set clock to low, data to low, and output tristated */
1168 SMC_outw( mii_reg, MII_REG );
1169 udelay(SMC_PHY_CLOCK_DELAY);
1171 /* Restore original bank select */
1172 SMC_SELECT_BANK( oldBank );
1174 #if (SMC_DEBUG > 2 )
1175 printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1176 phyaddr, phyreg, phydata);
1177 smc_dump_mii_stream(bits, sizeof bits);
1180 #endif /* !CONFIG_SMC91111_EXT_PHY */
1184 /*------------------------------------------------------------
1185 . Waits the specified number of milliseconds - kernel friendly
1186 .-------------------------------------------------------------*/
1187 #ifndef CONFIG_SMC91111_EXT_PHY
1188 static void smc_wait_ms(unsigned int ms)
1192 #endif /* !CONFIG_SMC91111_EXT_PHY */
1196 /*------------------------------------------------------------
1197 . Configures the specified PHY using Autonegotiation. Calls
1198 . smc_phy_fixed() if the user has requested a certain config.
1199 .-------------------------------------------------------------*/
1200 #ifndef CONFIG_SMC91111_EXT_PHY
1201 static void smc_phy_configure()
1205 word my_phy_caps; /* My PHY capabilities */
1206 word my_ad_caps; /* My Advertised capabilities */
1207 word status = 0; /*;my status = 0 */
1210 PRINTK3("%s:smc_program_phy()\n", SMC_DEV_NAME);
1214 /* Get the detected phy address */
1215 phyaddr = SMC_PHY_ADDR;
1217 /* Reset the PHY, setting all other bits to zero */
1218 smc_write_phy_register(PHY_CNTL_REG, PHY_CNTL_RST);
1220 /* Wait for the reset to complete, or time out */
1221 timeout = 6; /* Wait up to 3 seconds */
1224 if (!(smc_read_phy_register(PHY_CNTL_REG)
1227 /* reset complete */
1231 smc_wait_ms(500); /* wait 500 millisecs */
1236 printf("%s:PHY reset timed out\n", SMC_DEV_NAME);
1237 goto smc_phy_configure_exit;
1240 /* Read PHY Register 18, Status Output */
1241 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1243 /* Enable PHY Interrupts (for register 18) */
1244 /* Interrupts listed here are disabled */
1245 smc_write_phy_register(PHY_INT_REG, 0xffff);
1247 /* Configure the Receive/Phy Control register */
1248 SMC_SELECT_BANK( 0 );
1249 SMC_outw( RPC_DEFAULT, RPC_REG );
1251 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1252 my_phy_caps = smc_read_phy_register(PHY_STAT_REG);
1253 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1255 if (my_phy_caps & PHY_STAT_CAP_T4)
1256 my_ad_caps |= PHY_AD_T4;
1258 if (my_phy_caps & PHY_STAT_CAP_TXF)
1259 my_ad_caps |= PHY_AD_TX_FDX;
1261 if (my_phy_caps & PHY_STAT_CAP_TXH)
1262 my_ad_caps |= PHY_AD_TX_HDX;
1264 if (my_phy_caps & PHY_STAT_CAP_TF)
1265 my_ad_caps |= PHY_AD_10_FDX;
1267 if (my_phy_caps & PHY_STAT_CAP_TH)
1268 my_ad_caps |= PHY_AD_10_HDX;
1270 /* Update our Auto-Neg Advertisement Register */
1271 smc_write_phy_register( PHY_AD_REG, my_ad_caps);
1273 PRINTK2("%s:phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1274 PRINTK2("%s:phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1276 /* Restart auto-negotiation process in order to advertise my caps */
1277 smc_write_phy_register( PHY_CNTL_REG,
1278 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
1280 /* Wait for the auto-negotiation to complete. This may take from */
1281 /* 2 to 3 seconds. */
1282 /* Wait for the reset to complete, or time out */
1283 timeout = 20; /* Wait up to 10 seconds */
1286 status = smc_read_phy_register( PHY_STAT_REG);
1287 if (status & PHY_STAT_ANEG_ACK)
1289 /* auto-negotiate complete */
1293 smc_wait_ms(500); /* wait 500 millisecs */
1295 /* Restart auto-negotiation if remote fault */
1296 if (status & PHY_STAT_REM_FLT)
1298 printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1300 /* Restart auto-negotiation */
1301 printf("%s:PHY restarting auto-negotiation\n",
1303 smc_write_phy_register( PHY_CNTL_REG,
1304 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
1305 PHY_CNTL_SPEED | PHY_CNTL_DPLX);
1311 printf("%s:PHY auto-negotiate timed out\n",
1313 printf("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1317 /* Fail if we detected an auto-negotiate remote fault */
1318 if (status & PHY_STAT_REM_FLT)
1320 printf( "%s:PHY remote fault detected\n", SMC_DEV_NAME);
1321 printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1325 /* Re-Configure the Receive/Phy Control register */
1326 SMC_outw( RPC_DEFAULT, RPC_REG );
1328 smc_phy_configure_exit:
1331 #endif /* !CONFIG_SMC91111_EXT_PHY */
1335 static void print_packet( byte * buf, int length )
1342 printf("Packet of length %d \n", length );
1345 lines = length / 16;
1346 remainder = length % 16;
1348 for ( i = 0; i < lines ; i ++ ) {
1351 for ( cur = 0; cur < 8; cur ++ ) {
1356 printf("%02x%02x ", a, b );
1360 for ( i = 0; i < remainder/2 ; i++ ) {
1365 printf("%02x%02x ", a, b );
1373 int eth_init(bd_t *bd) {
1386 int eth_send(volatile void *packet, int length) {
1387 return smc_send_packet(packet, length);
1390 #endif /* CONFIG_DRIVER_SMC91111 */