1 /*------------------------------------------------------------------------
3 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
6 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 . Rolf Offermanns <rof@sysgo.de>
9 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
10 . Developed by Simple Network Magic Corporation (SNMC)
11 . Copyright (C) 1996 by Erik Stahlman (ES)
13 . This program is free software; you can redistribute it and/or modify
14 . it under the terms of the GNU General Public License as published by
15 . the Free Software Foundation; either version 2 of the License, or
16 . (at your option) any later version.
18 . This program is distributed in the hope that it will be useful,
19 . but WITHOUT ANY WARRANTY; without even the implied warranty of
20 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 . GNU General Public License for more details.
23 . You should have received a copy of the GNU General Public License
24 . along with this program; if not, write to the Free Software
25 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 . Information contained in this file was obtained from the LAN91C111
28 . manual from SMC. To get a copy, if you really want one, you can find
29 . information under www.smsc.com.
32 . "Features" of the SMC chip:
33 . Integrated PHY/MAC for 10/100BaseT Operation
34 . Supports internal and external MII
35 . Integrated 8K packet memory
36 . EEPROM interface for configuration
39 . io = for the base address
43 . Erik Stahlman ( erik@vt.edu )
44 . Daris A Nevil ( dnevil@snmc.com )
47 . Hardware multicast code from Peter Cammaert ( pc@denkart.be )
50 . o SMSC LAN91C111 databook (www.smsc.com)
51 . o smc9194.c by Erik Stahlman
52 . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov )
55 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
56 . 10/17/01 Marco Hasewinkel Modify for DNP/1110
57 . 07/25/01 Woojung Huh Modify for ADS Bitsy
58 . 04/25/01 Daris A Nevil Initial public release through SMSC
59 . 03/16/01 Daris A Nevil Modified smc9194.c for use with LAN91C111
60 ----------------------------------------------------------------------------*/
67 #ifdef CONFIG_DRIVER_SMC91111
69 /* Use power-down feature of the chip */
74 static const char version[] =
75 "smc91111.c:v1.0 04/25/01 by Daris A Nevil (dnevil@snmc.com)\n";
79 /*------------------------------------------------------------------------
81 . Configuration options, for the experienced user to change.
83 -------------------------------------------------------------------------*/
86 . Wait time for memory to be free. This probably shouldn't be
87 . tuned that much, as waiting for this means nothing else happens
90 #define MEMORY_WAIT_TIME 16
94 #define PRINTK3(args...) printf(args)
96 #define PRINTK3(args...)
100 #define PRINTK2(args...) printf(args)
102 #define PRINTK2(args...)
106 #define PRINTK(args...) printf(args)
108 #define PRINTK(args...)
112 /*------------------------------------------------------------------------
114 . The internal workings of the driver. If you are changing anything
115 . here with the SMC stuff, you should have the datasheet and know
116 . what you are doing.
118 -------------------------------------------------------------------------*/
119 #define CARDNAME "LAN91C111"
121 /* Memory sizing constant */
122 #define LAN91C111_MEMORY_MULTIPLIER (1024*2)
124 #ifndef CONFIG_SMC91111_BASE
125 #define CONFIG_SMC91111_BASE 0x20000300
128 #define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE
130 #define SMC_DEV_NAME "SMC91111"
131 #define SMC_PHY_ADDR 0x0000
132 #define SMC_ALLOC_MAX_TRY 5
133 #define SMC_TX_TIMEOUT 30
135 #define SMC_PHY_CLOCK_DELAY 1000
139 #ifdef CONFIG_SMC_USE_32_BIT
144 /*-----------------------------------------------------------------
146 . The driver can be entered at any of the following entry points.
148 .------------------------------------------------------------------ */
150 extern int eth_init(bd_t *bd);
151 extern void eth_halt(void);
152 extern int eth_rx(void);
153 extern int eth_send(volatile void *packet, int length);
157 . This is called by register_netdev(). It is responsible for
158 . checking the portlist for the SMC9000 series chipset. If it finds
159 . one, then it will initialize the device, find the hardware information,
160 . and sets up the appropriate device parameters.
161 . NOTE: Interrupts are *OFF* when this procedure is called.
163 . NB:This shouldn't be static since it is referred to externally.
168 . This is called by unregister_netdev(). It is responsible for
169 . cleaning up before the driver is finally unregistered and discarded.
171 void smc_destructor(void);
174 . The kernel calls this function when someone wants to use the device,
175 . typically 'ifconfig ethX up'.
177 static int smc_open(bd_t *bd);
181 . This is called by the kernel in response to 'ifconfig ethX down'. It
182 . is responsible for cleaning up everything that the open routine
183 . does, and maybe putting the card into a powerdown state.
185 static int smc_close(void);
188 . Configures the PHY through the MII Management interface
190 #ifndef CONFIG_SMC91111_EXT_PHY
191 static void smc_phy_configure(void);
192 #endif /* !CONFIG_SMC91111_EXT_PHY */
195 . This is a separate procedure to handle the receipt of a packet, to
196 . leave the interrupt code looking slightly cleaner
198 static int smc_rcv(void);
200 /* See if a MAC address is defined in the current environment. If so use it. If not
201 . print a warning and set the environment and other globals with the default.
202 . If an EEPROM is present it really should be consulted.
204 int smc_get_ethaddr(bd_t *bd);
205 int get_rom_mac(char *v_rom_mac);
208 ------------------------------------------------------------
212 ------------------------------------------------------------
215 static char smc_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
218 * This function must be called before smc_open() if you want to override
219 * the default mac address.
222 void smc_set_mac_addr(const char *addr) {
225 for (i=0; i < sizeof(smc_mac_addr); i++){
226 smc_mac_addr[i] = addr[i];
231 * smc_get_macaddr is no longer used. If you want to override the default
232 * mac address, call smc_get_mac_addr as a part of the board initialization.
236 void smc_get_macaddr( byte *addr ) {
237 /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */
238 unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010);
242 for (i=0; i<6; i++) {
243 addr[0] = *(dnp1110_mac+0);
244 addr[1] = *(dnp1110_mac+1);
245 addr[2] = *(dnp1110_mac+2);
246 addr[3] = *(dnp1110_mac+3);
247 addr[4] = *(dnp1110_mac+4);
248 addr[5] = *(dnp1110_mac+5);
253 /***********************************************
254 * Show available memory *
255 ***********************************************/
256 void dump_memory_info(void)
261 old_bank = SMC_inw(BANK_SELECT)&0xF;
264 mem_info = SMC_inw( MIR_REG );
265 PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048);
267 SMC_SELECT_BANK(old_bank);
270 . A rather simple routine to print out a packet for debugging purposes.
273 static void print_packet( byte *, int );
276 #define tx_done(dev) 1
279 /* this does a soft reset on the device */
280 static void smc_reset( void );
282 /* Enable Interrupts, Receive, and Transmit */
283 static void smc_enable( void );
285 /* this puts the device in an inactive state */
286 static void smc_shutdown( void );
288 /* Routines to Read and Write the PHY Registers across the
289 MII Management Interface
292 #ifndef CONFIG_SMC91111_EXT_PHY
293 static word smc_read_phy_register(byte phyreg);
294 static void smc_write_phy_register(byte phyreg, word phydata);
295 #endif /* !CONFIG_SMC91111_EXT_PHY */
298 static int poll4int( byte mask, int timeout ) {
299 int tmo = get_timer(0) + timeout * CFG_HZ;
301 word old_bank = SMC_inw(BSR_REG);
303 PRINTK2("Polling...\n");
305 while((SMC_inw(SMC91111_INT_REG) & mask) == 0)
307 if (get_timer(0) >= tmo) {
313 /* restore old bank selection */
314 SMC_SELECT_BANK(old_bank);
322 /* Only one release command at a time, please */
323 static inline void smc_wait_mmu_release_complete(void)
326 /* assume bank 2 selected */
327 while ( SMC_inw(MMU_CMD_REG) & MC_BUSY ) {
328 udelay(1); /* Wait until not busy */
329 if( ++count > 200) break;
334 . Function: smc_reset( void )
336 . This sets the SMC91111 chip to its normal state, hopefully from whatever
337 . mess that any other DOS driver has put it in.
339 . Maybe I should reset more registers to defaults in here? SOFTRST should
343 . 1. send a SOFT RESET
344 . 2. wait for it to finish
345 . 3. enable autorelease mode
346 . 4. reset the memory management unit
347 . 5. clear all interrupts
350 static void smc_reset( void )
352 PRINTK2("%s:smc_reset\n", SMC_DEV_NAME);
354 /* This resets the registers mostly to defaults, but doesn't
355 affect EEPROM. That seems unnecessary */
356 SMC_SELECT_BANK( 0 );
357 SMC_outw( RCR_SOFTRST, RCR_REG );
359 /* Setup the Configuration Register */
360 /* This is necessary because the CONFIG_REG is not affected */
361 /* by a soft reset */
363 SMC_SELECT_BANK( 1 );
364 #if defined(CONFIG_SMC91111_EXT_PHY)
365 SMC_outw( CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG);
367 SMC_outw( CONFIG_DEFAULT, CONFIG_REG);
371 /* Release from possible power-down state */
372 /* Configuration register is not affected by Soft Reset */
373 SMC_outw( SMC_inw( CONFIG_REG ) | CONFIG_EPH_POWER_EN, CONFIG_REG );
375 SMC_SELECT_BANK( 0 );
377 /* this should pause enough for the chip to be happy */
380 /* Disable transmit and receive functionality */
381 SMC_outw( RCR_CLEAR, RCR_REG );
382 SMC_outw( TCR_CLEAR, TCR_REG );
384 /* set the control register */
385 SMC_SELECT_BANK( 1 );
386 SMC_outw( CTL_DEFAULT, CTL_REG );
389 SMC_SELECT_BANK( 2 );
390 smc_wait_mmu_release_complete();
391 SMC_outw( MC_RESET, MMU_CMD_REG );
392 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
393 udelay(1); /* Wait until not busy */
395 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
396 but this is a place where future chipsets _COULD_ break. Be wary
397 of issuing another MMU command right after this */
399 /* Disable all interrupts */
400 SMC_outb( 0, IM_REG );
404 . Function: smc_enable
405 . Purpose: let the chip talk to the outside work
407 . 1. Enable the transmitter
408 . 2. Enable the receiver
409 . 3. Enable interrupts
411 static void smc_enable()
413 PRINTK2("%s:smc_enable\n", SMC_DEV_NAME);
414 SMC_SELECT_BANK( 0 );
415 /* see the header file for options in TCR/RCR DEFAULT*/
416 SMC_outw( TCR_DEFAULT, TCR_REG );
417 SMC_outw( RCR_DEFAULT, RCR_REG );
420 /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */
424 . Function: smc_shutdown
425 . Purpose: closes down the SMC91xxx chip.
427 . 1. zero the interrupt mask
428 . 2. clear the enable receive flag
429 . 3. clear the enable xmit flags
432 . (1) maybe utilize power down mode.
433 . Why not yet? Because while the chip will go into power down mode,
434 . the manual says that it will wake up in response to any I/O requests
435 . in the register space. Empirical results do not show this working.
437 static void smc_shutdown()
439 PRINTK2(CARDNAME ":smc_shutdown\n");
441 /* no more interrupts for me */
442 SMC_SELECT_BANK( 2 );
443 SMC_outb( 0, IM_REG );
445 /* and tell the card to stay away from that nasty outside world */
446 SMC_SELECT_BANK( 0 );
447 SMC_outb( RCR_CLEAR, RCR_REG );
448 SMC_outb( TCR_CLEAR, TCR_REG );
453 . Function: smc_hardware_send_packet(struct net_device * )
455 . This sends the actual packet to the SMC9xxx chip.
458 . First, see if a saved_skb is available.
459 . ( this should NOT be called if there is no 'saved_skb'
460 . Now, find the packet number that the chip allocated
461 . Point the data pointers at it in memory
462 . Set the length word in the chip's memory
463 . Dump the packet to chip memory
464 . Check if a last byte is needed ( odd length packet )
465 . if so, set the control flag right
466 . Tell the card to send it
467 . Enable the transmit interrupt, so I know if it failed
468 . Free the kernel data if I actually sent it.
470 static int smc_send_packet(volatile void *packet, int packet_length)
473 unsigned long ioaddr;
482 PRINTK3("%s:smc_hardware_send_packet\n", SMC_DEV_NAME);
484 length = ETH_ZLEN < packet_length ? packet_length : ETH_ZLEN;
487 ** The MMU wants the number of pages to be the number of 256 bytes
488 ** 'pages', minus 1 ( since a packet can't ever have 0 pages :) )
490 ** The 91C111 ignores the size bits, but the code is left intact
491 ** for backwards and future compatibility.
493 ** Pkt size for allocating is data length +6 (for additional status
494 ** words, length and ctl!)
496 ** If odd size then last byte is included in this header.
498 numPages = ((length & 0xfffe) + 6);
499 numPages >>= 8; /* Divide by 256 */
502 printf("%s: Far too big packet error. \n", SMC_DEV_NAME);
506 /* now, try to allocate the memory */
507 SMC_SELECT_BANK( 2 );
508 SMC_outw( MC_ALLOC | numPages, MMU_CMD_REG );
510 /* FIXME: the ALLOC_INT bit never gets set *
511 * so the following will always give a *
512 * memory allocation error. *
513 * same code works in armboot though *
519 time_out = MEMORY_WAIT_TIME;
521 status = SMC_inb( SMC91111_INT_REG );
522 if ( status & IM_ALLOC_INT ) {
523 /* acknowledge the interrupt */
524 SMC_outb( IM_ALLOC_INT, SMC91111_INT_REG );
527 } while ( -- time_out );
530 PRINTK2("%s: memory allocation, try %d failed ...\n",
532 if (try < SMC_ALLOC_MAX_TRY)
538 PRINTK2("%s: memory allocation, try %d succeeded ...\n",
542 /* I can send the packet now.. */
544 ioaddr = SMC_BASE_ADDRESS;
546 buf = (byte *)packet;
548 /* If I get here, I _know_ there is a packet slot waiting for me */
549 packet_no = SMC_inb( AR_REG );
550 if ( packet_no & AR_FAILED ) {
551 /* or isn't there? BAD CHIP! */
552 printf("%s: Memory allocation failed. \n",
557 /* we have a packet address, so tell the card to use it */
558 SMC_outb( packet_no, PN_REG );
560 /* point to the beginning of the packet */
561 SMC_outw( PTR_AUTOINC , PTR_REG );
563 PRINTK3("%s: Trying to xmit packet of length %x\n",
564 SMC_DEV_NAME, length);
567 printf("Transmitting Packet\n");
568 print_packet( buf, length );
571 /* send the packet length ( +6 for status, length and ctl byte )
572 and the status word ( set to zeros ) */
574 SMC_outl( (length +6 ) << 16 , SMC91111_DATA_REG );
576 SMC_outw( 0, SMC91111_DATA_REG );
577 /* send the packet length ( +6 for status words, length, and ctl*/
578 SMC_outw( (length+6), SMC91111_DATA_REG );
581 /* send the actual data
582 . I _think_ it's faster to send the longs first, and then
583 . mop up by sending the last word. It depends heavily
584 . on alignment, at least on the 486. Maybe it would be
585 . a good idea to check which is optimal? But that could take
586 . almost as much time as is saved?
589 SMC_outsl(SMC91111_DATA_REG, buf, length >> 2 );
591 SMC_outw(*((word *)(buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG);
593 SMC_outsw(SMC91111_DATA_REG , buf, (length ) >> 1);
594 #endif /* USE_32_BIT */
596 /* Send the last byte, if there is one. */
597 if ( (length & 1) == 0 ) {
598 SMC_outw( 0, SMC91111_DATA_REG );
600 SMC_outw( buf[length -1 ] | 0x2000, SMC91111_DATA_REG );
603 /* and let the chipset deal with it */
604 SMC_outw( MC_ENQUEUE , MMU_CMD_REG );
606 /* poll for TX INT */
607 if (poll4int(IM_TX_INT, SMC_TX_TIMEOUT)) {
609 PRINTK2("%s: TX timeout, sending failed...\n",
613 SMC_outw(MC_FREEPKT, MMU_CMD_REG);
615 /* wait for MMU getting ready (low) */
616 while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
621 PRINTK2("MMU ready\n");
627 SMC_outw(IM_TX_INT, SMC91111_INT_REG);
628 PRINTK2("%s: Sent packet of length %d \n", SMC_DEV_NAME, length);
631 SMC_outw(MC_FREEPKT, MMU_CMD_REG);
633 /* wait for MMU getting ready (low) */
634 while (SMC_inw(MMU_CMD_REG) & MC_BUSY)
639 PRINTK2("MMU ready\n");
647 /*-------------------------------------------------------------------------
649 | smc_destructor( struct net_device * dev )
651 | dev, pointer to the device structure
656 ---------------------------------------------------------------------------
658 void smc_destructor()
660 PRINTK2(CARDNAME ":smc_destructor\n");
665 * Open and Initialize the board
667 * Set up everything, reset the card, etc ..
670 static int smc_open(bd_t *bd)
674 PRINTK2("%s:smc_open\n", SMC_DEV_NAME);
676 /* reset the hardware */
680 /* Configure the PHY */
681 #ifndef CONFIG_SMC91111_EXT_PHY
685 /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */
686 /* SMC_SELECT_BANK(0); */
687 /* SMC_outw(0, RPC_REG); */
690 err = smc_get_ethaddr(bd); /* set smc_mac_addr, and sync it with u-boot globals */
692 memset(bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set*/
693 return(-1); /* upper code ignores this, but NOT bi_enetaddr */
697 for ( i = 0; i < 6; i += 2 ) {
700 address = smc_mac_addr[ i + 1 ] << 8 ;
701 address |= smc_mac_addr[ i ];
702 SMC_outw( address, ADDR0_REG + i );
705 for ( i = 0; i < 6; i ++ )
706 SMC_outb( smc_mac_addr[i], ADDR0_REG + i );
712 #if 0 /* dead code? -- wd */
721 for (__i = 0; __i < l; __i++) {
722 *(__b2 + __i) = *(dword *)(r+0x10000300);
728 /*-------------------------------------------------------------
730 . smc_rcv - receive a packet from the card
732 . There is ( at least ) a packet waiting to be read from
736 . o If an error, record it
737 . o otherwise, read in the packet
738 --------------------------------------------------------------
752 packet_number = SMC_inw( RXFIFO_REG );
754 if ( packet_number & RXFIFO_REMPTY ) {
759 PRINTK3("%s:smc_rcv\n", SMC_DEV_NAME);
760 /* start reading from the start of the packet */
761 SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG );
763 /* First two words are status and packet_length */
765 stat_len = SMC_inl(SMC91111_DATA_REG);
766 status = stat_len & 0xffff;
767 packet_length = stat_len >> 16;
769 status = SMC_inw( SMC91111_DATA_REG );
770 packet_length = SMC_inw( SMC91111_DATA_REG );
773 packet_length &= 0x07ff; /* mask off top bits */
775 PRINTK2("RCV: STATUS %4x LENGTH %4x\n", status, packet_length );
777 if ( !(status & RS_ERRORS ) ){
778 /* Adjust for having already read the first two words */
779 packet_length -= 4; /*4; */
782 /* set odd length for bug in LAN91C111, */
783 /* which never sets RS_ODDFRAME */
788 PRINTK3(" Reading %d dwords (and %d bytes) \n",
789 packet_length >> 2, packet_length & 3 );
790 /* QUESTION: Like in the TX routine, do I want
791 to send the DWORDs or the bytes first, or some
792 mixture. A mixture might improve already slow PIO
794 SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 );
795 /* read the left over bytes */
796 if (packet_length & 3) {
799 byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3));
800 dword leftover = SMC_inl(SMC91111_DATA_REG);
801 for (i=0; i<(packet_length & 3); i++)
802 *tail++ = (byte) (leftover >> (8*i)) & 0xff;
805 PRINTK3(" Reading %d words and %d byte(s) \n",
806 (packet_length >> 1 ), packet_length & 1 );
807 SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1);
809 #endif /* USE_32_BIT */
812 printf("Receiving Packet\n");
813 print_packet( NetRxPackets[0], packet_length );
821 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
822 udelay(1); /* Wait until not busy */
824 /* error or good, tell the card to get rid of this packet */
825 SMC_outw( MC_RELEASE, MMU_CMD_REG );
827 while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY )
828 udelay(1); /* Wait until not busy */
831 /* Pass the packet up to the protocol layers. */
832 NetReceive(NetRxPackets[0], packet_length);
833 return packet_length;
841 /*----------------------------------------------------
844 . this makes the board clean up everything that it can
845 . and not talk to the outside world. Caused by
846 . an 'ifconfig ethX down'
848 -----------------------------------------------------*/
849 static int smc_close()
851 PRINTK2("%s:smc_close\n", SMC_DEV_NAME);
853 /* clear everything */
861 /*------------------------------------------------------------
862 . Modify a bit in the LAN91C111 register set
863 .-------------------------------------------------------------*/
864 static word smc_modify_regbit(int bank, int ioaddr, int reg,
865 unsigned int bit, int val)
869 SMC_SELECT_BANK( bank );
871 regval = SMC_inw( reg );
877 SMC_outw( regval, 0 );
882 /*------------------------------------------------------------
883 . Retrieve a bit in the LAN91C111 register set
884 .-------------------------------------------------------------*/
885 static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit)
887 SMC_SELECT_BANK( bank );
888 if ( SMC_inw( reg ) & bit)
895 /*------------------------------------------------------------
896 . Modify a LAN91C111 register (word access only)
897 .-------------------------------------------------------------*/
898 static void smc_modify_reg(int bank, int ioaddr, int reg, word val)
900 SMC_SELECT_BANK( bank );
901 SMC_outw( val, reg );
905 /*------------------------------------------------------------
906 . Retrieve a LAN91C111 register (word access only)
907 .-------------------------------------------------------------*/
908 static int smc_get_reg(int bank, int ioaddr, int reg)
910 SMC_SELECT_BANK( bank );
911 return(SMC_inw( reg ));
916 /*---PHY CONTROL AND CONFIGURATION----------------------------------------- */
920 /*------------------------------------------------------------
921 . Debugging function for viewing MII Management serial bitstream
922 .-------------------------------------------------------------*/
923 static void smc_dump_mii_stream(byte* bits, int size)
928 for (i = 0; i < size; ++i)
934 for (i = 0; i < size; ++i)
936 if (bits[i] & MII_MDOE)
943 for (i = 0; i < size; ++i)
945 if (bits[i] & MII_MDO)
952 for (i = 0; i < size; ++i)
954 if (bits[i] & MII_MDI)
964 /*------------------------------------------------------------
965 . Reads a register from the MII Management serial interface
966 .-------------------------------------------------------------*/
967 #ifndef CONFIG_SMC91111_EXT_PHY
968 static word smc_read_phy_register(byte phyreg)
978 byte phyaddr = SMC_PHY_ADDR;
980 /* 32 consecutive ones on MDO to establish sync */
981 for (i = 0; i < 32; ++i)
982 bits[clk_idx++] = MII_MDOE | MII_MDO;
984 /* Start code <01> */
985 bits[clk_idx++] = MII_MDOE;
986 bits[clk_idx++] = MII_MDOE | MII_MDO;
988 /* Read command <10> */
989 bits[clk_idx++] = MII_MDOE | MII_MDO;
990 bits[clk_idx++] = MII_MDOE;
992 /* Output the PHY address, msb first */
994 for (i = 0; i < 5; ++i)
997 bits[clk_idx++] = MII_MDOE | MII_MDO;
999 bits[clk_idx++] = MII_MDOE;
1001 /* Shift to next lowest bit */
1005 /* Output the phy register number, msb first */
1007 for (i = 0; i < 5; ++i)
1010 bits[clk_idx++] = MII_MDOE | MII_MDO;
1012 bits[clk_idx++] = MII_MDOE;
1014 /* Shift to next lowest bit */
1018 /* Tristate and turnaround (2 bit times) */
1019 bits[clk_idx++] = 0;
1020 /*bits[clk_idx++] = 0; */
1022 /* Input starts at this bit time */
1023 input_idx = clk_idx;
1025 /* Will input 16 bits */
1026 for (i = 0; i < 16; ++i)
1027 bits[clk_idx++] = 0;
1029 /* Final clock bit */
1030 bits[clk_idx++] = 0;
1032 /* Save the current bank */
1033 oldBank = SMC_inw( BANK_SELECT );
1036 SMC_SELECT_BANK( 3 );
1038 /* Get the current MII register value */
1039 mii_reg = SMC_inw( MII_REG );
1041 /* Turn off all MII Interface bits */
1042 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
1044 /* Clock all 64 cycles */
1045 for (i = 0; i < sizeof bits; ++i)
1047 /* Clock Low - output data */
1048 SMC_outw( mii_reg | bits[i], MII_REG );
1049 udelay(SMC_PHY_CLOCK_DELAY);
1052 /* Clock Hi - input data */
1053 SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
1054 udelay(SMC_PHY_CLOCK_DELAY);
1055 bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
1058 /* Return to idle state */
1059 /* Set clock to low, data to low, and output tristated */
1060 SMC_outw( mii_reg, MII_REG );
1061 udelay(SMC_PHY_CLOCK_DELAY);
1063 /* Restore original bank select */
1064 SMC_SELECT_BANK( oldBank );
1066 /* Recover input data */
1068 for (i = 0; i < 16; ++i)
1072 if (bits[input_idx++] & MII_MDI)
1076 #if (SMC_DEBUG > 2 )
1077 printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1078 phyaddr, phyreg, phydata);
1079 smc_dump_mii_stream(bits, sizeof bits);
1086 /*------------------------------------------------------------
1087 . Writes a register to the MII Management serial interface
1088 .-------------------------------------------------------------*/
1089 static void smc_write_phy_register(byte phyreg, word phydata)
1097 byte phyaddr = SMC_PHY_ADDR;
1099 /* 32 consecutive ones on MDO to establish sync */
1100 for (i = 0; i < 32; ++i)
1101 bits[clk_idx++] = MII_MDOE | MII_MDO;
1103 /* Start code <01> */
1104 bits[clk_idx++] = MII_MDOE;
1105 bits[clk_idx++] = MII_MDOE | MII_MDO;
1107 /* Write command <01> */
1108 bits[clk_idx++] = MII_MDOE;
1109 bits[clk_idx++] = MII_MDOE | MII_MDO;
1111 /* Output the PHY address, msb first */
1113 for (i = 0; i < 5; ++i)
1116 bits[clk_idx++] = MII_MDOE | MII_MDO;
1118 bits[clk_idx++] = MII_MDOE;
1120 /* Shift to next lowest bit */
1124 /* Output the phy register number, msb first */
1126 for (i = 0; i < 5; ++i)
1129 bits[clk_idx++] = MII_MDOE | MII_MDO;
1131 bits[clk_idx++] = MII_MDOE;
1133 /* Shift to next lowest bit */
1137 /* Tristate and turnaround (2 bit times) */
1138 bits[clk_idx++] = 0;
1139 bits[clk_idx++] = 0;
1141 /* Write out 16 bits of data, msb first */
1143 for (i = 0; i < 16; ++i)
1146 bits[clk_idx++] = MII_MDOE | MII_MDO;
1148 bits[clk_idx++] = MII_MDOE;
1150 /* Shift to next lowest bit */
1154 /* Final clock bit (tristate) */
1155 bits[clk_idx++] = 0;
1157 /* Save the current bank */
1158 oldBank = SMC_inw( BANK_SELECT );
1161 SMC_SELECT_BANK( 3 );
1163 /* Get the current MII register value */
1164 mii_reg = SMC_inw( MII_REG );
1166 /* Turn off all MII Interface bits */
1167 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
1169 /* Clock all cycles */
1170 for (i = 0; i < sizeof bits; ++i)
1172 /* Clock Low - output data */
1173 SMC_outw( mii_reg | bits[i], MII_REG );
1174 udelay(SMC_PHY_CLOCK_DELAY);
1177 /* Clock Hi - input data */
1178 SMC_outw( mii_reg | bits[i] | MII_MCLK, MII_REG );
1179 udelay(SMC_PHY_CLOCK_DELAY);
1180 bits[i] |= SMC_inw( MII_REG ) & MII_MDI;
1183 /* Return to idle state */
1184 /* Set clock to low, data to low, and output tristated */
1185 SMC_outw( mii_reg, MII_REG );
1186 udelay(SMC_PHY_CLOCK_DELAY);
1188 /* Restore original bank select */
1189 SMC_SELECT_BANK( oldBank );
1191 #if (SMC_DEBUG > 2 )
1192 printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
1193 phyaddr, phyreg, phydata);
1194 smc_dump_mii_stream(bits, sizeof bits);
1197 #endif /* !CONFIG_SMC91111_EXT_PHY */
1200 /*------------------------------------------------------------
1201 . Waits the specified number of milliseconds - kernel friendly
1202 .-------------------------------------------------------------*/
1203 #ifndef CONFIG_SMC91111_EXT_PHY
1204 static void smc_wait_ms(unsigned int ms)
1208 #endif /* !CONFIG_SMC91111_EXT_PHY */
1211 /*------------------------------------------------------------
1212 . Configures the specified PHY using Autonegotiation. Calls
1213 . smc_phy_fixed() if the user has requested a certain config.
1214 .-------------------------------------------------------------*/
1215 #ifndef CONFIG_SMC91111_EXT_PHY
1216 static void smc_phy_configure()
1220 word my_phy_caps; /* My PHY capabilities */
1221 word my_ad_caps; /* My Advertised capabilities */
1222 word status = 0; /*;my status = 0 */
1225 PRINTK3("%s:smc_program_phy()\n", SMC_DEV_NAME);
1228 /* Get the detected phy address */
1229 phyaddr = SMC_PHY_ADDR;
1231 /* Reset the PHY, setting all other bits to zero */
1232 smc_write_phy_register(PHY_CNTL_REG, PHY_CNTL_RST);
1234 /* Wait for the reset to complete, or time out */
1235 timeout = 6; /* Wait up to 3 seconds */
1238 if (!(smc_read_phy_register(PHY_CNTL_REG)
1241 /* reset complete */
1245 smc_wait_ms(500); /* wait 500 millisecs */
1250 printf("%s:PHY reset timed out\n", SMC_DEV_NAME);
1251 goto smc_phy_configure_exit;
1254 /* Read PHY Register 18, Status Output */
1255 /* lp->lastPhy18 = smc_read_phy_register(PHY_INT_REG); */
1257 /* Enable PHY Interrupts (for register 18) */
1258 /* Interrupts listed here are disabled */
1259 smc_write_phy_register(PHY_INT_REG, 0xffff);
1261 /* Configure the Receive/Phy Control register */
1262 SMC_SELECT_BANK( 0 );
1263 SMC_outw( RPC_DEFAULT, RPC_REG );
1265 /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */
1266 my_phy_caps = smc_read_phy_register(PHY_STAT_REG);
1267 my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */
1269 if (my_phy_caps & PHY_STAT_CAP_T4)
1270 my_ad_caps |= PHY_AD_T4;
1272 if (my_phy_caps & PHY_STAT_CAP_TXF)
1273 my_ad_caps |= PHY_AD_TX_FDX;
1275 if (my_phy_caps & PHY_STAT_CAP_TXH)
1276 my_ad_caps |= PHY_AD_TX_HDX;
1278 if (my_phy_caps & PHY_STAT_CAP_TF)
1279 my_ad_caps |= PHY_AD_10_FDX;
1281 if (my_phy_caps & PHY_STAT_CAP_TH)
1282 my_ad_caps |= PHY_AD_10_HDX;
1284 /* Update our Auto-Neg Advertisement Register */
1285 smc_write_phy_register( PHY_AD_REG, my_ad_caps);
1287 PRINTK2("%s:phy caps=%x\n", SMC_DEV_NAME, my_phy_caps);
1288 PRINTK2("%s:phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps);
1290 /* Restart auto-negotiation process in order to advertise my caps */
1291 smc_write_phy_register( PHY_CNTL_REG,
1292 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
1294 /* Wait for the auto-negotiation to complete. This may take from */
1295 /* 2 to 3 seconds. */
1296 /* Wait for the reset to complete, or time out */
1297 timeout = 20; /* Wait up to 10 seconds */
1300 status = smc_read_phy_register( PHY_STAT_REG);
1301 if (status & PHY_STAT_ANEG_ACK)
1303 /* auto-negotiate complete */
1307 smc_wait_ms(500); /* wait 500 millisecs */
1309 /* Restart auto-negotiation if remote fault */
1310 if (status & PHY_STAT_REM_FLT)
1312 printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1314 /* Restart auto-negotiation */
1315 printf("%s:PHY restarting auto-negotiation\n",
1317 smc_write_phy_register( PHY_CNTL_REG,
1318 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
1319 PHY_CNTL_SPEED | PHY_CNTL_DPLX);
1325 printf("%s:PHY auto-negotiate timed out\n",
1327 printf("%s:PHY auto-negotiate timed out\n", SMC_DEV_NAME);
1331 /* Fail if we detected an auto-negotiate remote fault */
1332 if (status & PHY_STAT_REM_FLT)
1334 printf( "%s:PHY remote fault detected\n", SMC_DEV_NAME);
1335 printf("%s:PHY remote fault detected\n", SMC_DEV_NAME);
1339 /* Re-Configure the Receive/Phy Control register */
1340 SMC_outw( RPC_DEFAULT, RPC_REG );
1342 smc_phy_configure_exit:
1345 #endif /* !CONFIG_SMC91111_EXT_PHY */
1349 static void print_packet( byte * buf, int length )
1356 printf("Packet of length %d \n", length );
1359 lines = length / 16;
1360 remainder = length % 16;
1362 for ( i = 0; i < lines ; i ++ ) {
1365 for ( cur = 0; cur < 8; cur ++ ) {
1370 printf("%02x%02x ", a, b );
1374 for ( i = 0; i < remainder/2 ; i++ ) {
1379 printf("%02x%02x ", a, b );
1387 int eth_init(bd_t *bd) {
1388 return (smc_open(bd));
1399 int eth_send(volatile void *packet, int length) {
1400 return smc_send_packet(packet, length);
1403 int smc_get_ethaddr(bd_t *bd)
1405 int env_size, rom_valid, env_present = 0, reg;
1406 char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66";
1407 uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6];
1409 env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac));
1410 if ((env_size > 0) && (env_size < sizeof(es))) { /* exit if env is bad */
1411 printf("\n*** ERROR: ethaddr is not set properly!!\n");
1420 for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */
1421 v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0;
1423 s = (*e) ? e + 1 : e;
1426 rom_valid = get_rom_mac(v_rom_mac); /* get ROM mac value if any */
1428 if(!env_present){ /* if NO env */
1429 if(rom_valid){ /* but ROM is valid */
1431 sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", v_mac[0],
1432 v_mac[1] ,v_mac[2], v_mac[3],v_mac[4], v_mac[5]) ;
1433 setenv ("ethaddr", s_env_mac);
1434 }else{ /* no env, bad ROM */
1435 printf("\n*** ERROR: ethaddr is NOT set !!\n");
1438 }else /* good env, don't care ROM */
1439 v_mac = v_env_mac; /* always use a good env over a ROM */
1441 if(env_present && rom_valid) /* if both env and ROM are good */
1442 if(memcmp(v_env_mac, v_rom_mac, 6) != 0){
1443 printf("\n*** Warning: Environment and ROM MAC addresses don't match\n");
1444 printf("*** Using Environment MAC\n");
1446 memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */
1447 smc_set_mac_addr(v_mac); /* use old function to update smc default */
1451 int get_rom_mac(char *v_rom_mac)
1453 int is_rom_present = 0;
1454 #ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */
1455 char hw_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
1457 memcpy (v_rom_mac, hw_mac_addr, 6);
1462 /* if eeprom contents are valid
1463 * extract mac address into hw_mac_addr, 8 or 16 bit accesses
1464 * memcpy (v_rom_mac, hc_mac_addr, 6);
1468 memset(v_rom_mac, 0, 6);
1473 #endif /* CONFIG_DRIVER_SMC91111 */