2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/compiler.h>
13 #include <asm/arch/hardware.h>
15 #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
16 #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
18 #define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */
19 #define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */
20 #define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */
21 #define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */
23 #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
26 u32 control; /* Control Register [8:0] */
27 u32 mode; /* Mode Register [10:0] */
29 u32 baud_rate_gen; /* Baud Rate Generator [15:0] */
31 u32 channel_sts; /* Channel Status [11:0] */
32 u32 tx_rx_fifo; /* FIFO [15:0] or [7:0] */
33 u32 baud_rate_divider; /* Baud Rate Divider [7:0] */
36 static struct uart_zynq *uart_zynq_ports[2] = {
37 [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0,
38 [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1,
41 #if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0)
42 # define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
44 #if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1)
45 # define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE
48 #if !defined(CONFIG_ZYNQ_SERIAL_CLOCK0)
49 # define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000
51 #if !defined(CONFIG_ZYNQ_SERIAL_CLOCK1)
52 # define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000
55 struct uart_zynq_params {
60 static struct uart_zynq_params uart_zynq_ports_param[2] = {
61 [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0,
62 [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0,
63 [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1,
64 [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1,
67 /* Set up the baud rate in gd struct */
68 static void uart_zynq_serial_setbrg(const int port)
70 /* Calculation results. */
71 unsigned int calc_bauderror, bdiv, bgen;
72 unsigned long calc_baud = 0;
73 unsigned long baud = uart_zynq_ports_param[port].baudrate;
74 unsigned long clock = uart_zynq_ports_param[port].clock;
75 struct uart_zynq *regs = uart_zynq_ports[port];
78 * Baud rate = ------------------
81 * Find acceptable values for baud generation.
83 for (bdiv = 4; bdiv < 255; bdiv++) {
84 bgen = clock / (baud * (bdiv + 1));
85 if (bgen < 2 || bgen > 65535)
88 calc_baud = clock / (bgen * (bdiv + 1));
91 * Use first calculated baudrate with
92 * an acceptable (<3%) error
95 calc_bauderror = baud - calc_baud;
97 calc_bauderror = calc_baud - baud;
98 if (((calc_bauderror * 100) / baud) < 3)
102 writel(bdiv, ®s->baud_rate_divider);
103 writel(bgen, ®s->baud_rate_gen);
106 /* Initialize the UART, with...some settings. */
107 static int uart_zynq_serial_init(const int port)
109 struct uart_zynq *regs = uart_zynq_ports[port];
114 /* RX/TX enabled & reset */
115 writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \
116 ZYNQ_UART_CR_RXRST, ®s->control);
117 writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */
118 uart_zynq_serial_setbrg(port);
123 static void uart_zynq_serial_putc(const char c, const int port)
125 struct uart_zynq *regs = uart_zynq_ports[port];
127 while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
131 writel('\r', ®s->tx_rx_fifo);
132 while ((readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) != 0)
135 writel(c, ®s->tx_rx_fifo);
138 static void uart_zynq_serial_puts(const char *s, const int port)
141 uart_zynq_serial_putc(*s++, port);
144 static int uart_zynq_serial_tstc(const int port)
146 struct uart_zynq *regs = uart_zynq_ports[port];
148 return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0;
151 static int uart_zynq_serial_getc(const int port)
153 struct uart_zynq *regs = uart_zynq_ports[port];
155 while (!uart_zynq_serial_tstc(port))
157 return readl(®s->tx_rx_fifo);
160 /* Multi serial device functions */
161 #define DECLARE_PSSERIAL_FUNCTIONS(port) \
162 int uart_zynq##port##_init(void) \
163 { return uart_zynq_serial_init(port); } \
164 void uart_zynq##port##_setbrg(void) \
165 { return uart_zynq_serial_setbrg(port); } \
166 int uart_zynq##port##_getc(void) \
167 { return uart_zynq_serial_getc(port); } \
168 int uart_zynq##port##_tstc(void) \
169 { return uart_zynq_serial_tstc(port); } \
170 void uart_zynq##port##_putc(const char c) \
171 { uart_zynq_serial_putc(c, port); } \
172 void uart_zynq##port##_puts(const char *s) \
173 { uart_zynq_serial_puts(s, port); }
175 /* Serial device descriptor */
176 #define INIT_PSSERIAL_STRUCTURE(port, __name) { \
178 .start = uart_zynq##port##_init, \
180 .setbrg = uart_zynq##port##_setbrg, \
181 .getc = uart_zynq##port##_getc, \
182 .tstc = uart_zynq##port##_tstc, \
183 .putc = uart_zynq##port##_putc, \
184 .puts = uart_zynq##port##_puts, \
187 DECLARE_PSSERIAL_FUNCTIONS(0);
188 struct serial_device uart_zynq_serial0_device =
189 INIT_PSSERIAL_STRUCTURE(0, "ttyPS0");
190 DECLARE_PSSERIAL_FUNCTIONS(1);
191 struct serial_device uart_zynq_serial1_device =
192 INIT_PSSERIAL_STRUCTURE(1, "ttyPS1");
194 __weak struct serial_device *default_serial_console(void)
196 #if defined(CONFIG_ZYNQ_SERIAL_UART0)
197 if (uart_zynq_ports[0])
198 return &uart_zynq_serial0_device;
200 #if defined(CONFIG_ZYNQ_SERIAL_UART1)
201 if (uart_zynq_ports[1])
202 return &uart_zynq_serial1_device;
207 void zynq_serial_initalize(void)
209 serial_register(&uart_zynq_serial0_device);
210 serial_register(&uart_zynq_serial1_device);