common: Drop linux/bitops.h from common header
[oweals/u-boot.git] / drivers / serial / serial_stm32.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
4  * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
5  */
6
7 #include <common.h>
8 #include <clk.h>
9 #include <dm.h>
10 #include <log.h>
11 #include <reset.h>
12 #include <serial.h>
13 #include <watchdog.h>
14 #include <asm/io.h>
15 #include <asm/arch/stm32.h>
16 #include <linux/bitops.h>
17 #include <linux/delay.h>
18 #include "serial_stm32.h"
19 #include <dm/device_compat.h>
20
21 static void _stm32_serial_setbrg(fdt_addr_t base,
22                                  struct stm32_uart_info *uart_info,
23                                  u32 clock_rate,
24                                  int baudrate)
25 {
26         bool stm32f4 = uart_info->stm32f4;
27         u32 int_div, mantissa, fraction, oversampling;
28
29         int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate);
30
31         if (int_div < 16) {
32                 oversampling = 8;
33                 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
34         } else {
35                 oversampling = 16;
36                 clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_OVER8);
37         }
38
39         mantissa = (int_div / oversampling) << USART_BRR_M_SHIFT;
40         fraction = int_div % oversampling;
41
42         writel(mantissa | fraction, base + BRR_OFFSET(stm32f4));
43 }
44
45 static int stm32_serial_setbrg(struct udevice *dev, int baudrate)
46 {
47         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
48
49         _stm32_serial_setbrg(plat->base, plat->uart_info,
50                              plat->clock_rate, baudrate);
51
52         return 0;
53 }
54
55 static int stm32_serial_setconfig(struct udevice *dev, uint serial_config)
56 {
57         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
58         bool stm32f4 = plat->uart_info->stm32f4;
59         u8 uart_enable_bit = plat->uart_info->uart_enable_bit;
60         u32 cr1 = plat->base + CR1_OFFSET(stm32f4);
61         u32 config = 0;
62         uint parity = SERIAL_GET_PARITY(serial_config);
63         uint bits = SERIAL_GET_BITS(serial_config);
64         uint stop = SERIAL_GET_STOP(serial_config);
65
66         /*
67          * only parity config is implemented, check if other serial settings
68          * are the default one.
69          * (STM32F4 serial IP didn't support parity setting)
70          */
71         if (bits != SERIAL_8_BITS || stop != SERIAL_ONE_STOP || stm32f4)
72                 return -ENOTSUPP; /* not supported in driver*/
73
74         clrbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
75         /* update usart configuration (uart need to be disable)
76          * PCE: parity check enable
77          * PS : '0' : Even / '1' : Odd
78          * M[1:0] = '00' : 8 Data bits
79          * M[1:0] = '01' : 9 Data bits with parity
80          */
81         switch (parity) {
82         default:
83         case SERIAL_PAR_NONE:
84                 config = 0;
85                 break;
86         case SERIAL_PAR_ODD:
87                 config = USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0;
88                 break;
89         case SERIAL_PAR_EVEN:
90                 config = USART_CR1_PCE | USART_CR1_M0;
91                 break;
92         }
93
94         clrsetbits_le32(cr1,
95                         USART_CR1_PCE | USART_CR1_PS | USART_CR1_M1 |
96                         USART_CR1_M0,
97                         config);
98         setbits_le32(cr1, USART_CR1_RE | USART_CR1_TE | BIT(uart_enable_bit));
99
100         return 0;
101 }
102
103 static int stm32_serial_getc(struct udevice *dev)
104 {
105         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
106         bool stm32f4 = plat->uart_info->stm32f4;
107         fdt_addr_t base = plat->base;
108         u32 isr = readl(base + ISR_OFFSET(stm32f4));
109
110         if ((isr & USART_ISR_RXNE) == 0)
111                 return -EAGAIN;
112
113         if (isr & (USART_ISR_PE | USART_ISR_ORE | USART_ISR_FE)) {
114                 if (!stm32f4)
115                         setbits_le32(base + ICR_OFFSET,
116                                      USART_ICR_PCECF | USART_ICR_ORECF |
117                                      USART_ICR_FECF);
118                 else
119                         readl(base + RDR_OFFSET(stm32f4));
120                 return -EIO;
121         }
122
123         return readl(base + RDR_OFFSET(stm32f4));
124 }
125
126 static int _stm32_serial_putc(fdt_addr_t base,
127                               struct stm32_uart_info *uart_info,
128                               const char c)
129 {
130         bool stm32f4 = uart_info->stm32f4;
131
132         if ((readl(base + ISR_OFFSET(stm32f4)) & USART_ISR_TXE) == 0)
133                 return -EAGAIN;
134
135         writel(c, base + TDR_OFFSET(stm32f4));
136
137         return 0;
138 }
139
140 static int stm32_serial_putc(struct udevice *dev, const char c)
141 {
142         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
143
144         return _stm32_serial_putc(plat->base, plat->uart_info, c);
145 }
146
147 static int stm32_serial_pending(struct udevice *dev, bool input)
148 {
149         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
150         bool stm32f4 = plat->uart_info->stm32f4;
151         fdt_addr_t base = plat->base;
152
153         if (input)
154                 return readl(base + ISR_OFFSET(stm32f4)) &
155                         USART_ISR_RXNE ? 1 : 0;
156         else
157                 return readl(base + ISR_OFFSET(stm32f4)) &
158                         USART_ISR_TXE ? 0 : 1;
159 }
160
161 static void _stm32_serial_init(fdt_addr_t base,
162                                struct stm32_uart_info *uart_info)
163 {
164         bool stm32f4 = uart_info->stm32f4;
165         u8 uart_enable_bit = uart_info->uart_enable_bit;
166
167         /* Disable uart-> enable fifo -> enable uart */
168         clrbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
169                      BIT(uart_enable_bit));
170         if (uart_info->has_fifo)
171                 setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_FIFOEN);
172         setbits_le32(base + CR1_OFFSET(stm32f4), USART_CR1_RE | USART_CR1_TE |
173                      BIT(uart_enable_bit));
174 }
175
176 static int stm32_serial_probe(struct udevice *dev)
177 {
178         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
179         struct clk clk;
180         struct reset_ctl reset;
181         int ret;
182
183         plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev);
184
185         ret = clk_get_by_index(dev, 0, &clk);
186         if (ret < 0)
187                 return ret;
188
189         ret = clk_enable(&clk);
190         if (ret) {
191                 dev_err(dev, "failed to enable clock\n");
192                 return ret;
193         }
194
195         ret = reset_get_by_index(dev, 0, &reset);
196         if (!ret) {
197                 reset_assert(&reset);
198                 udelay(2);
199                 reset_deassert(&reset);
200         }
201
202         plat->clock_rate = clk_get_rate(&clk);
203         if (!plat->clock_rate) {
204                 clk_disable(&clk);
205                 return -EINVAL;
206         };
207
208         _stm32_serial_init(plat->base, plat->uart_info);
209
210         return 0;
211 }
212
213 static const struct udevice_id stm32_serial_id[] = {
214         { .compatible = "st,stm32-uart", .data = (ulong)&stm32f4_info},
215         { .compatible = "st,stm32f7-uart", .data = (ulong)&stm32f7_info},
216         { .compatible = "st,stm32h7-uart", .data = (ulong)&stm32h7_info},
217         {}
218 };
219
220 static int stm32_serial_ofdata_to_platdata(struct udevice *dev)
221 {
222         struct stm32x7_serial_platdata *plat = dev_get_platdata(dev);
223
224         plat->base = devfdt_get_addr(dev);
225         if (plat->base == FDT_ADDR_T_NONE)
226                 return -EINVAL;
227
228         return 0;
229 }
230
231 static const struct dm_serial_ops stm32_serial_ops = {
232         .putc = stm32_serial_putc,
233         .pending = stm32_serial_pending,
234         .getc = stm32_serial_getc,
235         .setbrg = stm32_serial_setbrg,
236         .setconfig = stm32_serial_setconfig
237 };
238
239 U_BOOT_DRIVER(serial_stm32) = {
240         .name = "serial_stm32",
241         .id = UCLASS_SERIAL,
242         .of_match = of_match_ptr(stm32_serial_id),
243         .ofdata_to_platdata = of_match_ptr(stm32_serial_ofdata_to_platdata),
244         .platdata_auto_alloc_size = sizeof(struct stm32x7_serial_platdata),
245         .ops = &stm32_serial_ops,
246         .probe = stm32_serial_probe,
247 #if !CONFIG_IS_ENABLED(OF_CONTROL)
248         .flags = DM_FLAG_PRE_RELOC,
249 #endif
250 };
251
252 #ifdef CONFIG_DEBUG_UART_STM32
253 #include <debug_uart.h>
254 static inline struct stm32_uart_info *_debug_uart_info(void)
255 {
256         struct stm32_uart_info *uart_info;
257
258 #if defined(CONFIG_STM32F4)
259         uart_info = &stm32f4_info;
260 #elif defined(CONFIG_STM32F7)
261         uart_info = &stm32f7_info;
262 #else
263         uart_info = &stm32h7_info;
264 #endif
265         return uart_info;
266 }
267
268 static inline void _debug_uart_init(void)
269 {
270         fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
271         struct stm32_uart_info *uart_info = _debug_uart_info();
272
273         _stm32_serial_init(base, uart_info);
274         _stm32_serial_setbrg(base, uart_info,
275                              CONFIG_DEBUG_UART_CLOCK,
276                              CONFIG_BAUDRATE);
277 }
278
279 static inline void _debug_uart_putc(int c)
280 {
281         fdt_addr_t base = CONFIG_DEBUG_UART_BASE;
282         struct stm32_uart_info *uart_info = _debug_uart_info();
283
284         while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN)
285                 ;
286 }
287
288 DEBUG_UART_FUNCS
289 #endif