1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Anup Patel <anup@brainfault.org>
8 #include <debug_uart.h>
14 #include <linux/compiler.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 #define UART_TXFIFO_FULL 0x80000000
20 #define UART_RXFIFO_EMPTY 0x80000000
21 #define UART_RXFIFO_DATA 0x000000ff
22 #define UART_TXCTRL_TXEN 0x1
23 #define UART_RXCTRL_RXEN 0x1
26 #define UART_IP_RXWM 0x2
38 struct sifive_uart_platdata {
40 struct uart_sifive *regs;
44 * Find minimum divisor divides in_freq to max_target_hz;
45 * Based on uart driver n SiFive FSBL.
47 * f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
48 * The nearest integer solution requires rounding up as to not exceed
50 * div = ceil(f_in / f_baud) - 1
51 * = floor((f_in - 1 + f_baud) / f_baud) - 1
52 * This should not overflow as long as (f_in - 1 + f_baud) does not exceed
53 * 2^32 - 1, which is unlikely since we represent frequencies in kHz.
55 static inline unsigned int uart_min_clk_divisor(unsigned long in_freq,
56 unsigned long max_target_hz)
58 unsigned long quotient =
59 (in_freq + max_target_hz - 1) / (max_target_hz);
67 /* Set up the baud rate in gd struct */
68 static void _sifive_serial_setbrg(struct uart_sifive *regs,
69 unsigned long clock, unsigned long baud)
71 writel((uart_min_clk_divisor(clock, baud)), ®s->div);
74 static void _sifive_serial_init(struct uart_sifive *regs)
76 writel(UART_TXCTRL_TXEN, ®s->txctrl);
77 writel(UART_RXCTRL_RXEN, ®s->rxctrl);
81 static int _sifive_serial_putc(struct uart_sifive *regs, const char c)
83 if (readl(®s->txfifo) & UART_TXFIFO_FULL)
86 writel(c, ®s->txfifo);
91 static int _sifive_serial_getc(struct uart_sifive *regs)
93 int ch = readl(®s->rxfifo);
95 if (ch & UART_RXFIFO_EMPTY)
97 ch &= UART_RXFIFO_DATA;
102 static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
106 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
109 ret = clk_get_by_index(dev, 0, &clk);
110 if (IS_ERR_VALUE(ret)) {
111 debug("SiFive UART failed to get clock\n");
112 ret = dev_read_u32(dev, "clock-frequency", &clock);
113 if (IS_ERR_VALUE(ret)) {
114 debug("SiFive UART clock not defined\n");
118 clock = clk_get_rate(&clk);
119 if (IS_ERR_VALUE(clock)) {
120 debug("SiFive UART clock get rate failed\n");
124 platdata->clock = clock;
125 _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
130 static int sifive_serial_probe(struct udevice *dev)
132 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
134 /* No need to reinitialize the UART after relocation */
135 if (gd->flags & GD_FLG_RELOC)
138 _sifive_serial_init(platdata->regs);
143 static int sifive_serial_getc(struct udevice *dev)
146 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
147 struct uart_sifive *regs = platdata->regs;
149 while ((c = _sifive_serial_getc(regs)) == -EAGAIN) ;
154 static int sifive_serial_putc(struct udevice *dev, const char ch)
157 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
159 while ((rc = _sifive_serial_putc(platdata->regs, ch)) == -EAGAIN) ;
164 static int sifive_serial_pending(struct udevice *dev, bool input)
166 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
167 struct uart_sifive *regs = platdata->regs;
170 return (readl(®s->ip) & UART_IP_RXWM);
172 return !!(readl(®s->txfifo) & UART_TXFIFO_FULL);
175 static int sifive_serial_ofdata_to_platdata(struct udevice *dev)
177 struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
179 platdata->regs = (struct uart_sifive *)dev_read_addr(dev);
180 if (IS_ERR(platdata->regs))
181 return PTR_ERR(platdata->regs);
186 static const struct dm_serial_ops sifive_serial_ops = {
187 .putc = sifive_serial_putc,
188 .getc = sifive_serial_getc,
189 .pending = sifive_serial_pending,
190 .setbrg = sifive_serial_setbrg,
193 static const struct udevice_id sifive_serial_ids[] = {
194 { .compatible = "sifive,uart0" },
198 U_BOOT_DRIVER(serial_sifive) = {
199 .name = "serial_sifive",
201 .of_match = sifive_serial_ids,
202 .ofdata_to_platdata = sifive_serial_ofdata_to_platdata,
203 .platdata_auto_alloc_size = sizeof(struct sifive_uart_platdata),
204 .probe = sifive_serial_probe,
205 .ops = &sifive_serial_ops,
208 #ifdef CONFIG_DEBUG_UART_SIFIVE
209 static inline void _debug_uart_init(void)
211 struct uart_sifive *regs =
212 (struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
214 _sifive_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK,
216 _sifive_serial_init(regs);
219 static inline void _debug_uart_putc(int ch)
221 struct uart_sifive *regs =
222 (struct uart_sifive *)CONFIG_DEBUG_UART_BASE;
224 while (_sifive_serial_putc(regs, ch) == -EAGAIN)