2 * Copy and modify from linux/drivers/serial/sh-sci.h
5 #include <dm/platform_data/serial_sh.h>
8 unsigned long iobase; /* in/out[bwl] */
9 unsigned char *membase; /* read/write[bwl] */
10 unsigned long mapbase; /* for ioremap */
11 enum sh_serial_type type; /* port type */
12 enum sh_clk_mode clk_mode; /* clock mode */
15 #if defined(CONFIG_CPU_SH7706) || \
16 defined(CONFIG_CPU_SH7707) || \
17 defined(CONFIG_CPU_SH7708) || \
18 defined(CONFIG_CPU_SH7709)
19 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
20 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
21 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
22 #elif defined(CONFIG_CPU_SH7705)
23 # define SCIF0 0xA4400000
24 # define SCIF2 0xA4410000
25 # define SCSMR_Ir 0xA44A0000
26 # define IRDA_SCIF SCIF0
27 # define SCPCR 0xA4000116
28 # define SCPDR 0xA4000136
30 /* Set the clock source,
31 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
32 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
34 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
35 #elif defined(CONFIG_CPU_SH7720) || \
36 defined(CONFIG_CPU_SH7721) || \
37 defined(CONFIG_ARCH_SH7367) || \
38 defined(CONFIG_ARCH_SH7377) || \
39 defined(CONFIG_ARCH_SH7372) || \
40 defined(CONFIG_SH73A0) || \
41 defined(CONFIG_R8A7740)
42 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
43 # define PORT_PTCR 0xA405011EUL
44 # define PORT_PVCR 0xA4050122UL
45 # define SCIF_ORER 0x0200 /* overrun error bit */
46 #elif defined(CONFIG_SH_RTS7751R2D)
47 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
48 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
49 # define SCIF_ORER 0x0001 /* overrun error bit */
50 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
51 #elif defined(CONFIG_CPU_SH7750) || \
52 defined(CONFIG_CPU_SH7750R) || \
53 defined(CONFIG_CPU_SH7750S) || \
54 defined(CONFIG_CPU_SH7091) || \
55 defined(CONFIG_CPU_SH7751) || \
56 defined(CONFIG_CPU_SH7751R)
57 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
58 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
59 # define SCIF_ORER 0x0001 /* overrun error bit */
60 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
61 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
62 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
63 #elif defined(CONFIG_CPU_SH7760)
64 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
65 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
66 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
67 # define SCIF_ORER 0x0001 /* overrun error bit */
68 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
69 #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
70 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
71 # define SCIF_ORER 0x0001 /* overrun error bit */
72 # define PACR 0xa4050100
73 # define PBCR 0xa4050102
74 # define SCSCR_INIT(port) 0x3B
75 #elif defined(CONFIG_CPU_SH7343)
76 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
77 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
78 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
79 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
80 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
81 #elif defined(CONFIG_CPU_SH7722)
82 # define PADR 0xA4050120
84 # define PSDR 0xA405013e
85 # define PWDR 0xA4050166
86 # define PSCR 0xA405011E
87 # define SCIF_ORER 0x0001 /* overrun error bit */
88 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
89 #elif defined(CONFIG_CPU_SH7366)
90 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
91 # define SCSPTR0 SCPDR0
92 # define SCIF_ORER 0x0001 /* overrun error bit */
93 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94 #elif defined(CONFIG_CPU_SH7723)
95 # define SCSPTR0 0xa4050160
96 # define SCSPTR1 0xa405013e
97 # define SCSPTR2 0xa4050160
98 # define SCSPTR3 0xa405013e
99 # define SCSPTR4 0xa4050128
100 # define SCSPTR5 0xa4050128
101 # define SCIF_ORER 0x0001 /* overrun error bit */
102 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
103 #elif defined(CONFIG_CPU_SH7734)
104 # define SCSPTR0 0xFFE40020
105 # define SCSPTR1 0xFFE41020
106 # define SCSPTR2 0xFFE42020
107 # define SCSPTR3 0xFFE43020
108 # define SCSPTR4 0xFFE44020
109 # define SCSPTR5 0xFFE45020
110 # define SCIF_ORER 0x0001 /* overrun error bit */
111 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
112 #elif defined(CONFIG_CPU_SH4_202)
113 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
114 # define SCIF_ORER 0x0001 /* overrun error bit */
115 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
116 #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103)
117 # define SCIF_BASE_ADDR 0x01030000
118 # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR)
119 # define SCIF_PTR2_OFFS 0x0000020
120 # define SCIF_LSR2_OFFS 0x0000024
122 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
124 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
125 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
126 #elif defined(CONFIG_CPU_SH7757) || \
127 defined(CONFIG_CPU_SH7752) || \
128 defined(CONFIG_CPU_SH7753)
129 # define SCSPTR0 0xfe4b0020
130 # define SCSPTR1 0xfe4b0020
131 # define SCSPTR2 0xfe4b0020
132 # define SCIF_ORER 0x0001
133 # define SCSCR_INIT(port) 0x38
135 #elif defined(CONFIG_CPU_SH7763)
136 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
137 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
138 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
139 # define SCIF_ORER 0x0001 /* overrun error bit */
140 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
141 #elif defined(CONFIG_CPU_SH7770)
142 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
143 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
144 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
145 # define SCIF_ORER 0x0001 /* overrun error bit */
146 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
147 #elif defined(CONFIG_CPU_SH7780)
148 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
149 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
150 # define SCIF_ORER 0x0001 /* Overrun error bit */
152 #if defined(CONFIG_SH_SH2007)
153 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
154 # define SCSCR_INIT(port) 0x38
156 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
157 # define SCSCR_INIT(port) 0x3a
160 #elif defined(CONFIG_CPU_SH7786)
161 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
162 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
163 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
164 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
165 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
166 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
167 # define SCIF_ORER 0x0001 /* Overrun error bit */
168 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
169 #elif defined(CONFIG_CPU_SH7201) || \
170 defined(CONFIG_CPU_SH7203) || \
171 defined(CONFIG_CPU_SH7206) || \
172 defined(CONFIG_CPU_SH7263) || \
173 defined(CONFIG_CPU_SH7264)
174 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
175 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
176 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
177 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
178 # if defined(CONFIG_CPU_SH7201)
179 # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
180 # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
181 # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
182 # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
184 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
185 #elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1)
186 # define SCSPTR0 0xe8007020 /* 16 bit SCIF */
187 # define SCSPTR1 0xe8007820 /* 16 bit SCIF */
188 # define SCSPTR2 0xe8008020 /* 16 bit SCIF */
189 # define SCSPTR3 0xe8008820 /* 16 bit SCIF */
190 # define SCSPTR4 0xe8009020 /* 16 bit SCIF */
191 # define SCSPTR5 0xe8009820 /* 16 bit SCIF */
192 # define SCSPTR6 0xe800a020 /* 16 bit SCIF */
193 # define SCSPTR7 0xe800a820 /* 16 bit SCIF */
194 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
195 # define SCIF_ORER 0x0001 /* overrun error bit */
196 #elif defined(CONFIG_CPU_SH7619)
197 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
198 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
199 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
200 # define SCIF_ORER 0x0001 /* overrun error bit */
201 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
202 #elif defined(CONFIG_CPU_SHX3)
203 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
204 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
205 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
206 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
207 # define SCIF_ORER 0x0001 /* Overrun error bit */
208 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
209 #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \
210 defined(CONFIG_R7S72100)
211 # if defined(CONFIG_SCIF_A)
212 # define SCIF_ORER 0x0200
214 # define SCIF_ORER 0x0001
216 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30)
217 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
219 # error CPU subtype not defined
223 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
224 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
225 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
226 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
227 #if defined(CONFIG_CPU_SH7750) || \
228 defined(CONFIG_CPU_SH7091) || \
229 defined(CONFIG_CPU_SH7750R) || \
230 defined(CONFIG_CPU_SH7722) || \
231 defined(CONFIG_CPU_SH7734) || \
232 defined(CONFIG_CPU_SH7750S) || \
233 defined(CONFIG_CPU_SH7751) || \
234 defined(CONFIG_CPU_SH7751R) || \
235 defined(CONFIG_CPU_SH7763) || \
236 defined(CONFIG_CPU_SH7780) || \
237 defined(CONFIG_CPU_SH7786) || \
238 defined(CONFIG_CPU_SHX3)
239 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
241 #define SCI_CTRL_FLAGS_REIE 0
243 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
244 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
245 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
246 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
249 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
250 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
251 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
252 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
253 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
254 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
255 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
256 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
258 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
261 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
262 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
263 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
264 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
265 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
266 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
267 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
268 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
270 #if defined(CONFIG_CPU_SH7705) || \
271 defined(CONFIG_CPU_SH7720) || \
272 defined(CONFIG_CPU_SH7721) || \
273 defined(CONFIG_ARCH_SH7367) || \
274 defined(CONFIG_ARCH_SH7377) || \
275 defined(CONFIG_ARCH_SH7372) || \
276 defined(CONFIG_SH73A0) || \
277 defined(CONFIG_R8A7740)
278 # define SCIF_ORER 0x0200
279 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
280 # define SCIF_RFDC_MASK 0x007f
281 # define SCIF_TXROOM_MAX 64
282 #elif defined(CONFIG_CPU_SH7763)
283 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
284 # define SCIF_RFDC_MASK 0x007f
285 # define SCIF_TXROOM_MAX 64
286 /* SH7763 SCIF2 support */
287 # define SCIF2_RFDC_MASK 0x001f
288 # define SCIF2_TXROOM_MAX 16
289 #elif defined(CONFIG_RCAR_GEN2)
290 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
291 # if defined(CONFIG_SCIF_A)
292 # define SCIF_RFDC_MASK 0x007f
294 # define SCIF_RFDC_MASK 0x001f
297 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
298 # define SCIF_RFDC_MASK 0x001f
299 # define SCIF_TXROOM_MAX 16
303 #define SCIF_ORER 0x0000
306 #define SCxSR_TEND(port)\
307 (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
308 #define SCxSR_ERRORS(port)\
309 (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
310 #define SCxSR_RDxF(port)\
311 (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
312 #define SCxSR_TDxE(port)\
313 (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
314 #define SCxSR_FER(port)\
315 (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
316 #define SCxSR_PER(port)\
317 (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
318 #define SCxSR_BRK(port)\
319 ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
320 #define SCxSR_ORER(port)\
321 (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
323 #if defined(CONFIG_CPU_SH7705) || \
324 defined(CONFIG_CPU_SH7720) || \
325 defined(CONFIG_CPU_SH7721) || \
326 defined(CONFIG_ARCH_SH7367) || \
327 defined(CONFIG_ARCH_SH7377) || \
328 defined(CONFIG_ARCH_SH7372) || \
329 defined(CONFIG_SH73A0) || \
330 defined(CONFIG_R8A7740)
331 # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
332 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
333 # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
334 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
336 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
337 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
338 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
339 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
343 #define SCFCR_RFRST 0x0002
344 #define SCFCR_TFRST 0x0004
345 #define SCFCR_TCRST 0x4000
346 #define SCFCR_MCE 0x0008
348 #define SCI_MAJOR 204
349 #define SCI_MINOR_START 8
351 /* Generic serial flags */
352 #define SCI_RX_THROTTLE 0x0000001
354 #define SCI_MAGIC 0xbabeface
357 * Events are used to schedule things to happen at timer-interrupt
358 * time, instead of at rs interrupt time.
360 #define SCI_EVENT_WRITE_WAKEUP 0
362 #define SCI_IN(size, offset)\
364 return readb(port->membase + (offset));\
366 return readw(port->membase + (offset));\
368 #define SCI_OUT(size, offset, value)\
370 writeb(value, port->membase + (offset));\
371 } else if ((size) == 16) {\
372 writew(value, port->membase + (offset));\
375 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
376 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
377 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
378 SCI_IN(scif_size, scif_offset)\
379 } else { /* PORT_SCI or PORT_SCIFA */\
380 SCI_IN(sci_size, sci_offset);\
383 static inline void sci_##name##_out(struct uart_port *port,\
384 unsigned int value) {\
385 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\
386 SCI_OUT(scif_size, scif_offset, value)\
387 } else { /* PORT_SCI or PORT_SCIFA */\
388 SCI_OUT(sci_size, sci_offset, value);\
392 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
393 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
394 SCI_IN(scif_size, scif_offset);\
396 static inline void sci_##name##_out(struct uart_port *port,\
397 unsigned int value) {\
398 SCI_OUT(scif_size, scif_offset, value);\
401 #define CPU_SCI_FNS(name, sci_offset, sci_size)\
402 static inline unsigned int sci_##name##_in(struct uart_port *port) {\
403 SCI_IN(sci_size, sci_offset);\
405 static inline void sci_##name##_out(struct uart_port *port,\
406 unsigned int value) {\
407 SCI_OUT(sci_size, sci_offset, value);\
410 #if defined(CONFIG_CPU_SH3) || \
411 defined(CONFIG_ARCH_SH7367) || \
412 defined(CONFIG_ARCH_SH7377) || \
413 defined(CONFIG_ARCH_SH7372) || \
414 defined(CONFIG_SH73A0) || \
415 defined(CONFIG_R8A7740)
416 #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
417 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
418 sh4_sci_offset, sh4_sci_size, \
419 sh3_scif_offset, sh3_scif_size, \
420 sh4_scif_offset, sh4_scif_size, \
421 h8_sci_offset, h8_sci_size) \
422 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
423 sh4_scif_offset, sh4_scif_size)
424 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
425 sh4_scif_offset, sh4_scif_size) \
426 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
427 #elif defined(CONFIG_CPU_SH7705) || \
428 defined(CONFIG_CPU_SH7720) || \
429 defined(CONFIG_CPU_SH7721) || \
430 defined(CONFIG_ARCH_SH7367) || \
431 defined(CONFIG_ARCH_SH7377) || \
432 defined(CONFIG_SH73A0)
433 #define SCIF_FNS(name, scif_offset, scif_size) \
434 CPU_SCIF_FNS(name, scif_offset, scif_size)
435 #elif defined(CONFIG_ARCH_SH7372) || \
436 defined(CONFIG_R8A7740)
437 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
438 sh4_scifb_offset, sh4_scifb_size) \
439 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
440 sh4_scifb_offset, sh4_scifb_size)
441 #define SCIF_FNS(name, scif_offset, scif_size) \
442 CPU_SCIF_FNS(name, scif_offset, scif_size)
444 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
445 sh4_sci_offset, sh4_sci_size, \
446 sh3_scif_offset, sh3_scif_size,\
447 sh4_scif_offset, sh4_scif_size, \
448 h8_sci_offset, h8_sci_size) \
449 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
450 sh3_scif_offset, sh3_scif_size)
451 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
452 sh4_scif_offset, sh4_scif_size) \
453 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
455 #elif defined(CONFIG_CPU_SH7723)
456 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
457 sh4_scif_offset, sh4_scif_size) \
458 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\
459 sh4_scif_offset, sh4_scif_size)
460 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
461 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
463 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
464 sh4_sci_offset, sh4_sci_size, \
465 sh3_scif_offset, sh3_scif_size,\
466 sh4_scif_offset, sh4_scif_size, \
467 h8_sci_offset, h8_sci_size) \
468 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
469 sh4_scif_offset, sh4_scif_size)
470 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \
471 sh4_scif_offset, sh4_scif_size) \
472 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
475 #if defined(CONFIG_CPU_SH7705) || \
476 defined(CONFIG_CPU_SH7720) || \
477 defined(CONFIG_CPU_SH7721) || \
478 defined(CONFIG_ARCH_SH7367) || \
479 defined(CONFIG_ARCH_SH7377) || \
480 defined(CONFIG_SH73A0)
482 SCIF_FNS(SCSMR, 0x00, 16)
483 SCIF_FNS(SCBRR, 0x04, 8)
484 SCIF_FNS(SCSCR, 0x08, 16)
485 SCIF_FNS(SCTDSR, 0x0c, 8)
486 SCIF_FNS(SCFER, 0x10, 16)
487 SCIF_FNS(SCxSR, 0x14, 16)
488 SCIF_FNS(SCFCR, 0x18, 16)
489 SCIF_FNS(SCFDR, 0x1c, 16)
490 SCIF_FNS(SCxTDR, 0x20, 8)
491 SCIF_FNS(SCxRDR, 0x24, 8)
492 SCIF_FNS(SCLSR, 0x00, 0)
493 SCIF_FNS(DL, 0x00, 0) /* dummy */
494 #elif defined(CONFIG_ARCH_SH7372) || \
495 defined(CONFIG_R8A7740)
496 SCIF_FNS(SCSMR, 0x00, 16)
497 SCIF_FNS(SCBRR, 0x04, 8)
498 SCIF_FNS(SCSCR, 0x08, 16)
499 SCIF_FNS(SCTDSR, 0x0c, 16)
500 SCIF_FNS(SCFER, 0x10, 16)
501 SCIF_FNS(SCxSR, 0x14, 16)
502 SCIF_FNS(SCFCR, 0x18, 16)
503 SCIF_FNS(SCFDR, 0x1c, 16)
504 SCIF_FNS(SCTFDR, 0x38, 16)
505 SCIF_FNS(SCRFDR, 0x3c, 16)
506 SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
507 SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
508 SCIF_FNS(SCLSR, 0x00, 0)
509 SCIF_FNS(DL, 0x00, 0) /* dummy */
510 #elif defined(CONFIG_CPU_SH7723)
511 SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
512 SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
513 SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
514 SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
515 SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
516 SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
517 SCIx_FNS(SCSPTR, 0, 0, 0, 0)
518 SCIF_FNS(SCTDSR, 0x0c, 8)
519 SCIF_FNS(SCFER, 0x10, 16)
520 SCIF_FNS(SCFCR, 0x18, 16)
521 SCIF_FNS(SCFDR, 0x1c, 16)
522 SCIF_FNS(SCLSR, 0x24, 16)
523 SCIF_FNS(DL, 0x00, 0) /* dummy */
524 #elif defined(CONFIG_RCAR_GEN2)
525 /* SCIFA and SCIF register offsets and size */
526 SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0)
527 SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0)
528 SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0)
529 SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0)
530 SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0)
531 SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0)
532 SCIF_FNS(SCFCR, 0, 0, 0x18, 16)
533 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
534 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
535 SCIF_FNS(DL, 0, 0, 0x30, 16)
536 SCIF_FNS(CKS, 0, 0, 0x34, 16)
537 #if defined(CONFIG_SCIF_A)
538 SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
540 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
543 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
544 /* name off sz off sz off sz off sz off sz*/
545 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
546 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
547 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
548 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
549 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
550 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
551 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
552 #if defined(CONFIG_CPU_SH7760) || \
553 defined(CONFIG_CPU_SH7780) || \
554 defined(CONFIG_CPU_SH7786)
555 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
556 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
557 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
558 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
559 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
560 #elif defined(CONFIG_CPU_SH7763)
561 SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
562 SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
563 SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
564 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
565 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
566 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
567 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
570 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
571 #if defined(CONFIG_CPU_SH7722)
572 SCIF_FNS(SCSPTR, 0, 0, 0, 0)
574 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
576 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
578 SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
580 #define sci_in(port, reg) sci_##reg##_in(port)
581 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
583 #if defined(CONFIG_CPU_SH7706) || \
584 defined(CONFIG_CPU_SH7707) || \
585 defined(CONFIG_CPU_SH7708) || \
586 defined(CONFIG_CPU_SH7709)
587 static inline int sci_rxd_in(struct uart_port *port)
589 if (port->mapbase == 0xfffffe80)
590 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
593 #elif defined(CONFIG_CPU_SH7750) || \
594 defined(CONFIG_CPU_SH7751) || \
595 defined(CONFIG_CPU_SH7751R) || \
596 defined(CONFIG_CPU_SH7750R) || \
597 defined(CONFIG_CPU_SH7750S) || \
598 defined(CONFIG_CPU_SH7091)
599 static inline int sci_rxd_in(struct uart_port *port)
601 if (port->mapbase == 0xffe00000)
602 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
605 #else /* default case for non-SCI processors */
606 static inline int sci_rxd_in(struct uart_port *port)
613 * Values for the BitRate Register (SCBRR)
615 * The values are actually divisors for a frequency which can
616 * be internal to the SH3 (14.7456MHz) or derived from an external
617 * clock source. This driver assumes the internal clock is used;
618 * to support using an external clock source, config options or
619 * possibly command-line options would need to be added.
621 * Also, to support speeds below 2400 (why?) the lower 2 bits of
622 * the SCSMR register would also need to be set to non-zero values.
624 * -- Greg Banks 27Feb2000
626 * Answer: The SCBRR register is only eight bits, and the value in
627 * it gets larger with lower baud rates. At around 2400 (depending on
628 * the peripherial module clock) you run out of bits. However the
629 * lower two bits of SCSMR allow the module clock to be divided down,
630 * scaling the value which is needed in SCBRR.
632 * -- Stuart Menefy - 23 May 2000
634 * I meant, why would anyone bother with bitrates below 2400.
636 * -- Greg Banks - 7Jul2000
638 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
639 * tape reader as a console!
641 * -- Mitch Davis - 15 Jul 2000
644 #if (defined(CONFIG_CPU_SH7780) || \
645 defined(CONFIG_CPU_SH7786)) && \
646 !defined(CONFIG_SH_SH2007)
647 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
648 #elif defined(CONFIG_CPU_SH7705) || \
649 defined(CONFIG_CPU_SH7720) || \
650 defined(CONFIG_CPU_SH7721) || \
651 defined(CONFIG_ARCH_SH7367) || \
652 defined(CONFIG_ARCH_SH7377) || \
653 defined(CONFIG_ARCH_SH7372) || \
654 defined(CONFIG_SH73A0) || \
655 defined(CONFIG_R8A7740)
656 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
657 #elif defined(CONFIG_CPU_SH7723)
658 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
660 if (port->type == PORT_SCIF)
661 return (clk+16*bps)/(32*bps)-1;
663 return ((clk*2)+16*bps)/(16*bps)-1;
665 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
666 #elif defined(CONFIG_RCAR_GEN2)
667 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
668 #if defined(CONFIG_SCIF_A)
669 #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */
671 #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */
673 #else /* Generic SH */
674 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
678 #define DL_VALUE(bps, clk) 0