3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
7 * Philippe Robin, <philippe.robin@arm.com>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
34 #include <linux/compiler.h>
35 #include "serial_pl01x.h"
38 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
39 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
40 * Versatile PB has four UARTs.
42 #define CONSOLE_PORT CONFIG_CONS_INDEX
43 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
44 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
46 static void pl01x_putc (int portnum, char c);
47 static int pl01x_getc (int portnum);
48 static int pl01x_tstc (int portnum);
49 unsigned int baudrate = CONFIG_BAUDRATE;
50 DECLARE_GLOBAL_DATA_PTR;
52 static struct pl01x_regs *pl01x_get_regs(int portnum)
54 return (struct pl01x_regs *) port[portnum];
57 #ifdef CONFIG_PL010_SERIAL
59 static int pl01x_serial_init(void)
61 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
64 /* First, disable everything */
65 writel(0, ®s->pl010_cr);
70 divisor = UART_PL010_BAUD_9600;
74 divisor = UART_PL010_BAUD_9600;
78 divisor = UART_PL010_BAUD_38400;
82 divisor = UART_PL010_BAUD_57600;
86 divisor = UART_PL010_BAUD_115200;
90 divisor = UART_PL010_BAUD_38400;
93 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
94 writel(divisor & 0xff, ®s->pl010_lcrl);
96 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
97 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN, ®s->pl010_lcrh);
99 /* Finally, enable the UART */
100 writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
105 #endif /* CONFIG_PL010_SERIAL */
107 #ifdef CONFIG_PL011_SERIAL
109 static int pl01x_serial_init(void)
111 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
113 unsigned int divider;
114 unsigned int remainder;
115 unsigned int fraction;
118 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
119 /* Empty RX fifo if necessary */
120 if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
121 while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
126 /* First, disable everything */
127 writel(0, ®s->pl011_cr);
132 * IBRD = UART_CLK / (16 * BAUD_RATE)
133 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE))) / (16 * BAUD_RATE))
135 temp = 16 * baudrate;
136 divider = CONFIG_PL011_CLOCK / temp;
137 remainder = CONFIG_PL011_CLOCK % temp;
138 temp = (8 * remainder) / baudrate;
139 fraction = (temp >> 1) + (temp & 1);
141 writel(divider, ®s->pl011_ibrd);
142 writel(fraction, ®s->pl011_fbrd);
144 /* Set the UART to be 8 bits, 1 stop bit, no parity, fifo enabled */
145 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
146 writel(lcr, ®s->pl011_lcrh);
148 #ifdef CONFIG_PL011_SERIAL_RLCR
153 * Program receive line control register after waiting
154 * 10 bus cycles. Delay be writing to readonly register
157 for (i = 0; i < 10; i++)
158 writel(lcr, ®s->fr);
160 writel(lcr, ®s->pl011_rlcr);
161 /* lcrh needs to be set again for change to be effective */
162 writel(lcr, ®s->pl011_lcrh);
165 /* Finally, enable the UART */
166 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE | UART_PL011_CR_RXE |
167 UART_PL011_CR_RTS, ®s->pl011_cr);
172 #endif /* CONFIG_PL011_SERIAL */
174 static void pl01x_serial_putc(const char c)
177 pl01x_putc (CONSOLE_PORT, '\r');
179 pl01x_putc (CONSOLE_PORT, c);
182 static int pl01x_serial_getc(void)
184 return pl01x_getc (CONSOLE_PORT);
187 static int pl01x_serial_tstc(void)
189 return pl01x_tstc (CONSOLE_PORT);
192 static void pl01x_serial_setbrg(void)
194 struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
196 baudrate = gd->baudrate;
198 * Flush FIFO and wait for non-busy before changing baudrate to avoid
201 while (!(readl(®s->fr) & UART_PL01x_FR_TXFE))
203 while (readl(®s->fr) & UART_PL01x_FR_BUSY)
208 static void pl01x_putc (int portnum, char c)
210 struct pl01x_regs *regs = pl01x_get_regs(portnum);
212 /* Wait until there is space in the FIFO */
213 while (readl(®s->fr) & UART_PL01x_FR_TXFF)
216 /* Send the character */
217 writel(c, ®s->dr);
220 static int pl01x_getc (int portnum)
222 struct pl01x_regs *regs = pl01x_get_regs(portnum);
225 /* Wait until there is data in the FIFO */
226 while (readl(®s->fr) & UART_PL01x_FR_RXFE)
229 data = readl(®s->dr);
231 /* Check for an error flag */
232 if (data & 0xFFFFFF00) {
233 /* Clear the error */
234 writel(0xFFFFFFFF, ®s->ecr);
241 static int pl01x_tstc (int portnum)
243 struct pl01x_regs *regs = pl01x_get_regs(portnum);
246 return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
249 static struct serial_device pl01x_serial_drv = {
250 .name = "pl01x_serial",
251 .start = pl01x_serial_init,
253 .setbrg = pl01x_serial_setbrg,
254 .putc = pl01x_serial_putc,
255 .puts = default_serial_puts,
256 .getc = pl01x_serial_getc,
257 .tstc = pl01x_serial_tstc,
260 void pl01x_serial_initialize(void)
262 serial_register(&pl01x_serial_drv);
265 __weak struct serial_device *default_serial_console(void)
267 return &pl01x_serial_drv;