3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
7 * Philippe Robin, <philippe.robin@arm.com>
9 * SPDX-License-Identifier: GPL-2.0+
12 /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
20 #include <dm/platform_data/serial_pl01x.h>
21 #include <linux/compiler.h>
22 #include "serial_pl01x_internal.h"
25 DECLARE_GLOBAL_DATA_PTR;
27 #ifndef CONFIG_DM_SERIAL
29 static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
30 static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
31 static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
32 #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
36 static int pl01x_putc(struct pl01x_regs *regs, char c)
38 /* Wait until there is space in the FIFO */
39 if (readl(®s->fr) & UART_PL01x_FR_TXFF)
42 /* Send the character */
48 static int pl01x_getc(struct pl01x_regs *regs)
52 /* Wait until there is data in the FIFO */
53 if (readl(®s->fr) & UART_PL01x_FR_RXFE)
56 data = readl(®s->dr);
58 /* Check for an error flag */
59 if (data & 0xFFFFFF00) {
61 writel(0xFFFFFFFF, ®s->ecr);
68 static int pl01x_tstc(struct pl01x_regs *regs)
71 return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
74 static int pl01x_generic_serial_init(struct pl01x_regs *regs,
79 /* disable everything */
80 writel(0, ®s->pl010_cr);
83 #ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT
84 /* Empty RX fifo if necessary */
85 if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) {
86 while (!(readl(®s->fr) & UART_PL01x_FR_RXFE))
90 /* disable everything */
91 writel(0, ®s->pl011_cr);
100 static int pl011_set_line_control(struct pl01x_regs *regs)
104 * Internal update of baud rate register require line
105 * control register write
107 lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
108 #ifdef CONFIG_PL011_SERIAL_RLCR
113 * Program receive line control register after waiting
114 * 10 bus cycles. Delay be writing to readonly register
117 for (i = 0; i < 10; i++)
118 writel(lcr, ®s->fr);
120 writel(lcr, ®s->pl011_rlcr);
123 writel(lcr, ®s->pl011_lcrh);
127 static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
128 int clock, int baudrate)
132 unsigned int divisor;
134 /* disable everything */
135 writel(0, ®s->pl010_cr);
139 divisor = UART_PL010_BAUD_9600;
142 divisor = UART_PL010_BAUD_9600;
145 divisor = UART_PL010_BAUD_38400;
148 divisor = UART_PL010_BAUD_57600;
151 divisor = UART_PL010_BAUD_115200;
154 divisor = UART_PL010_BAUD_38400;
157 writel((divisor & 0xf00) >> 8, ®s->pl010_lcrm);
158 writel(divisor & 0xff, ®s->pl010_lcrl);
161 * Set line control for the PL010 to be 8 bits, 1 stop bit,
162 * no parity, fifo enabled
164 writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
166 /* Finally, enable the UART */
167 writel(UART_PL010_CR_UARTEN, ®s->pl010_cr);
172 unsigned int divider;
173 unsigned int remainder;
174 unsigned int fraction;
179 * IBRD = UART_CLK / (16 * BAUD_RATE)
180 * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
181 * / (16 * BAUD_RATE))
183 temp = 16 * baudrate;
184 divider = clock / temp;
185 remainder = clock % temp;
186 temp = (8 * remainder) / baudrate;
187 fraction = (temp >> 1) + (temp & 1);
189 writel(divider, ®s->pl011_ibrd);
190 writel(fraction, ®s->pl011_fbrd);
192 pl011_set_line_control(regs);
193 /* Finally, enable the UART */
194 writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
195 UART_PL011_CR_RXE | UART_PL011_CR_RTS, ®s->pl011_cr);
205 #ifndef CONFIG_DM_SERIAL
206 static void pl01x_serial_init_baud(int baudrate)
210 #if defined(CONFIG_PL010_SERIAL)
211 pl01x_type = TYPE_PL010;
212 #elif defined(CONFIG_PL011_SERIAL)
213 pl01x_type = TYPE_PL011;
214 clock = CONFIG_PL011_CLOCK;
216 base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
218 pl01x_generic_serial_init(base_regs, pl01x_type);
219 pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
223 * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
224 * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
225 * Versatile PB has four UARTs.
227 int pl01x_serial_init(void)
229 pl01x_serial_init_baud(CONFIG_BAUDRATE);
234 static void pl01x_serial_putc(const char c)
237 while (pl01x_putc(base_regs, '\r') == -EAGAIN);
239 while (pl01x_putc(base_regs, c) == -EAGAIN);
242 static int pl01x_serial_getc(void)
245 int ch = pl01x_getc(base_regs);
256 static int pl01x_serial_tstc(void)
258 return pl01x_tstc(base_regs);
261 static void pl01x_serial_setbrg(void)
264 * Flush FIFO and wait for non-busy before changing baudrate to avoid
267 while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
269 while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
271 pl01x_serial_init_baud(gd->baudrate);
274 static struct serial_device pl01x_serial_drv = {
275 .name = "pl01x_serial",
276 .start = pl01x_serial_init,
278 .setbrg = pl01x_serial_setbrg,
279 .putc = pl01x_serial_putc,
280 .puts = default_serial_puts,
281 .getc = pl01x_serial_getc,
282 .tstc = pl01x_serial_tstc,
285 void pl01x_serial_initialize(void)
287 serial_register(&pl01x_serial_drv);
290 __weak struct serial_device *default_serial_console(void)
292 return &pl01x_serial_drv;
295 #endif /* nCONFIG_DM_SERIAL */
297 #ifdef CONFIG_DM_SERIAL
300 struct pl01x_regs *regs;
301 enum pl01x_type type;
304 static int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
306 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
307 struct pl01x_priv *priv = dev_get_priv(dev);
309 pl01x_generic_setbrg(priv->regs, priv->type, plat->clock, baudrate);
314 static int pl01x_serial_probe(struct udevice *dev)
316 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
317 struct pl01x_priv *priv = dev_get_priv(dev);
319 priv->regs = (struct pl01x_regs *)plat->base;
320 priv->type = plat->type;
321 return pl01x_generic_serial_init(priv->regs, priv->type);
324 static int pl01x_serial_getc(struct udevice *dev)
326 struct pl01x_priv *priv = dev_get_priv(dev);
328 return pl01x_getc(priv->regs);
331 static int pl01x_serial_putc(struct udevice *dev, const char ch)
333 struct pl01x_priv *priv = dev_get_priv(dev);
335 return pl01x_putc(priv->regs, ch);
338 static int pl01x_serial_pending(struct udevice *dev, bool input)
340 struct pl01x_priv *priv = dev_get_priv(dev);
341 unsigned int fr = readl(&priv->regs->fr);
344 return pl01x_tstc(priv->regs);
346 return fr & UART_PL01x_FR_TXFF ? 0 : 1;
349 static const struct dm_serial_ops pl01x_serial_ops = {
350 .putc = pl01x_serial_putc,
351 .pending = pl01x_serial_pending,
352 .getc = pl01x_serial_getc,
353 .setbrg = pl01x_serial_setbrg,
356 #ifdef CONFIG_OF_CONTROL
357 static const struct udevice_id pl01x_serial_id[] ={
358 {.compatible = "arm,pl011", .data = TYPE_PL011},
359 {.compatible = "arm,pl010", .data = TYPE_PL010},
363 static int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
365 struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
368 addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg");
369 if (addr == FDT_ADDR_T_NONE)
373 plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1);
374 plat->type = dev_get_driver_data(dev);
379 U_BOOT_DRIVER(serial_pl01x) = {
380 .name = "serial_pl01x",
382 .of_match = of_match_ptr(pl01x_serial_id),
383 .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
384 .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
385 .probe = pl01x_serial_probe,
386 .ops = &pl01x_serial_ops,
387 .flags = DM_FLAG_PRE_RELOC,
388 .priv_auto_alloc_size = sizeof(struct pl01x_priv),