2 * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/clock.h>
13 #include <dm/platform_data/serial_mxc.h>
15 #include <linux/compiler.h>
17 /* UART Control Register Bit Fields.*/
18 #define URXD_CHARRDY (1<<15)
19 #define URXD_ERR (1<<14)
20 #define URXD_OVRRUN (1<<13)
21 #define URXD_FRMERR (1<<12)
22 #define URXD_BRK (1<<11)
23 #define URXD_PRERR (1<<10)
24 #define URXD_RX_DATA (0xFF)
25 #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
26 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
27 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
28 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
29 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
30 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
31 #define UCR1_IREN (1<<7) /* Infrared interface enable */
32 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
33 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
34 #define UCR1_SNDBRK (1<<4) /* Send break */
35 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
36 #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
37 #define UCR1_DOZE (1<<1) /* Doze */
38 #define UCR1_UARTEN (1<<0) /* UART enabled */
39 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
40 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
41 #define UCR2_CTSC (1<<13) /* CTS pin control */
42 #define UCR2_CTS (1<<12) /* Clear to send */
43 #define UCR2_ESCEN (1<<11) /* Escape enable */
44 #define UCR2_PREN (1<<8) /* Parity enable */
45 #define UCR2_PROE (1<<7) /* Parity odd/even */
46 #define UCR2_STPB (1<<6) /* Stop */
47 #define UCR2_WS (1<<5) /* Word size */
48 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
49 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
50 #define UCR2_RXEN (1<<1) /* Receiver enabled */
51 #define UCR2_SRST (1<<0) /* SW reset */
52 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
53 #define UCR3_PARERREN (1<<12) /* Parity enable */
54 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
55 #define UCR3_DSR (1<<10) /* Data set ready */
56 #define UCR3_DCD (1<<9) /* Data carrier detect */
57 #define UCR3_RI (1<<8) /* Ring indicator */
58 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
59 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
60 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
61 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
62 #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
63 #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
64 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
65 #define UCR3_BPEN (1<<0) /* Preset registers enable */
66 #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
67 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
68 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
69 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
70 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
71 #define UCR4_IRSC (1<<5) /* IR special case */
72 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
73 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
74 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
75 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
76 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
77 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
78 #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */
79 #define UFCR_DCEDTE (1<<6) /* DTE mode select */
80 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
81 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
82 #define USR1_RTSS (1<<14) /* RTS pin status */
83 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
84 #define USR1_RTSD (1<<12) /* RTS delta */
85 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
86 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
87 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
88 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
89 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
90 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
91 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
92 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
93 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
94 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
95 #define USR2_IDLE (1<<12) /* Idle condition */
96 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
97 #define USR2_WAKE (1<<7) /* Wake */
98 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
99 #define USR2_TXDC (1<<3) /* Transmitter complete */
100 #define USR2_BRCD (1<<2) /* Break condition */
101 #define USR2_ORE (1<<1) /* Overrun error */
102 #define USR2_RDR (1<<0) /* Recv data ready */
103 #define UTS_FRCPERR (1<<13) /* Force parity error */
104 #define UTS_LOOP (1<<12) /* Loop tx and rx */
105 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
106 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
107 #define UTS_TXFULL (1<<4) /* TxFIFO full */
108 #define UTS_RXFULL (1<<3) /* RxFIFO full */
109 #define UTS_SOFTRST (1<<0) /* Software reset */
111 DECLARE_GLOBAL_DATA_PTR;
139 #ifndef CONFIG_DM_SERIAL
141 #ifndef CONFIG_MXC_UART_BASE
142 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
145 #define mxc_base ((struct mxc_uart *)CONFIG_MXC_UART_BASE)
147 #define TXTL 2 /* reset default */
148 #define RXTL 1 /* reset default */
149 #define RFDIV 4 /* divide input clock by 2 */
151 static void mxc_serial_setbrg(void)
153 u32 clk = imx_get_uartclk();
156 gd->baudrate = CONFIG_BAUDRATE;
158 writel(((RFDIV << UFCR_RFDIV_SHF) |
159 (TXTL << UFCR_TXTL_SHF) |
160 (RXTL << UFCR_RXTL_SHF)),
162 writel(0xf, &mxc_base->bir);
163 writel(clk / (2 * gd->baudrate), &mxc_base->bmr);
167 static int mxc_serial_getc(void)
169 while (readl(&mxc_base->ts) & UTS_RXEMPTY)
171 return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
174 static void mxc_serial_putc(const char c)
176 /* If \n, also do \r */
180 writel(c, &mxc_base->txd);
182 /* wait for transmitter to be ready */
183 while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
188 * Test whether a character is in the RX buffer
190 static int mxc_serial_tstc(void)
192 /* If receive fifo is empty, return false */
193 if (readl(&mxc_base->ts) & UTS_RXEMPTY)
199 * Initialise the serial port with the given baudrate. The settings
200 * are always 8 data bits, no parity, 1 stop bit, no start bits.
203 static int mxc_serial_init(void)
205 writel(0, &mxc_base->cr1);
206 writel(0, &mxc_base->cr2);
208 while (!(readl(&mxc_base->cr2) & UCR2_SRST));
210 writel(0x704 | UCR3_ADNIMP, &mxc_base->cr3);
211 writel(0x8000, &mxc_base->cr4);
212 writel(0x2b, &mxc_base->esc);
213 writel(0, &mxc_base->tim);
215 writel(0, &mxc_base->ts);
219 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
222 writel(UCR1_UARTEN, &mxc_base->cr1);
227 static struct serial_device mxc_serial_drv = {
228 .name = "mxc_serial",
229 .start = mxc_serial_init,
231 .setbrg = mxc_serial_setbrg,
232 .putc = mxc_serial_putc,
233 .puts = default_serial_puts,
234 .getc = mxc_serial_getc,
235 .tstc = mxc_serial_tstc,
238 void mxc_serial_initialize(void)
240 serial_register(&mxc_serial_drv);
243 __weak struct serial_device *default_serial_console(void)
245 return &mxc_serial_drv;
249 #ifdef CONFIG_DM_SERIAL
251 int mxc_serial_setbrg(struct udevice *dev, int baudrate)
253 struct mxc_serial_platdata *plat = dev->platdata;
254 struct mxc_uart *const uart = plat->reg;
255 u32 clk = imx_get_uartclk();
258 tmp = 4 << UFCR_RFDIV_SHF;
261 writel(tmp, &uart->fcr);
263 writel(0xf, &uart->bir);
264 writel(clk / (2 * baudrate), &uart->bmr);
266 writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
268 writel(UCR1_UARTEN, &uart->cr1);
273 static int mxc_serial_probe(struct udevice *dev)
275 struct mxc_serial_platdata *plat = dev->platdata;
276 struct mxc_uart *const uart = plat->reg;
278 writel(0, &uart->cr1);
279 writel(0, &uart->cr2);
280 while (!(readl(&uart->cr2) & UCR2_SRST));
281 writel(0x704 | UCR3_ADNIMP, &uart->cr3);
282 writel(0x8000, &uart->cr4);
283 writel(0x2b, &uart->esc);
284 writel(0, &uart->tim);
285 writel(0, &uart->ts);
290 static int mxc_serial_getc(struct udevice *dev)
292 struct mxc_serial_platdata *plat = dev->platdata;
293 struct mxc_uart *const uart = plat->reg;
295 if (readl(&uart->ts) & UTS_RXEMPTY)
298 return readl(&uart->rxd) & URXD_RX_DATA;
301 static int mxc_serial_putc(struct udevice *dev, const char ch)
303 struct mxc_serial_platdata *plat = dev->platdata;
304 struct mxc_uart *const uart = plat->reg;
306 if (!(readl(&uart->ts) & UTS_TXEMPTY))
309 writel(ch, &uart->txd);
314 static int mxc_serial_pending(struct udevice *dev, bool input)
316 struct mxc_serial_platdata *plat = dev->platdata;
317 struct mxc_uart *const uart = plat->reg;
318 uint32_t sr2 = readl(&uart->sr2);
321 return sr2 & USR2_RDR ? 1 : 0;
323 return sr2 & USR2_TXDC ? 0 : 1;
326 static const struct dm_serial_ops mxc_serial_ops = {
327 .putc = mxc_serial_putc,
328 .pending = mxc_serial_pending,
329 .getc = mxc_serial_getc,
330 .setbrg = mxc_serial_setbrg,
333 #if CONFIG_IS_ENABLED(OF_CONTROL)
334 static int mxc_serial_ofdata_to_platdata(struct udevice *dev)
336 struct mxc_serial_platdata *plat = dev->platdata;
339 addr = devfdt_get_addr(dev);
340 if (addr == FDT_ADDR_T_NONE)
343 plat->reg = (struct mxc_uart *)addr;
345 plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
350 static const struct udevice_id mxc_serial_ids[] = {
351 { .compatible = "fsl,imx6ul-uart" },
352 { .compatible = "fsl,imx7d-uart" },
357 U_BOOT_DRIVER(serial_mxc) = {
358 .name = "serial_mxc",
360 #if CONFIG_IS_ENABLED(OF_CONTROL)
361 .of_match = mxc_serial_ids,
362 .ofdata_to_platdata = mxc_serial_ofdata_to_platdata,
363 .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata),
365 .probe = mxc_serial_probe,
366 .ops = &mxc_serial_ops,
367 .flags = DM_FLAG_PRE_RELOC,