1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Freescale Semiconductor, Inc.
8 #include <fsl_lpuart.h>
12 #include <linux/compiler.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
16 #define US1_TDRE (1 << 7)
17 #define US1_RDRF (1 << 5)
18 #define US1_OR (1 << 3)
19 #define UC2_TE (1 << 3)
20 #define UC2_RE (1 << 2)
21 #define CFIFO_TXFLUSH (1 << 7)
22 #define CFIFO_RXFLUSH (1 << 6)
23 #define SFIFO_RXOF (1 << 2)
24 #define SFIFO_RXUF (1 << 0)
26 #define STAT_LBKDIF (1 << 31)
27 #define STAT_RXEDGIF (1 << 30)
28 #define STAT_TDRE (1 << 23)
29 #define STAT_RDRF (1 << 21)
30 #define STAT_IDLE (1 << 20)
31 #define STAT_OR (1 << 19)
32 #define STAT_NF (1 << 18)
33 #define STAT_FE (1 << 17)
34 #define STAT_PF (1 << 16)
35 #define STAT_MA1F (1 << 15)
36 #define STAT_MA2F (1 << 14)
37 #define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
38 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
40 #define CTRL_TE (1 << 19)
41 #define CTRL_RE (1 << 18)
43 #define FIFO_RXFLUSH BIT(14)
44 #define FIFO_TXFLUSH BIT(15)
45 #define FIFO_TXSIZE_MASK 0x70
46 #define FIFO_TXSIZE_OFF 4
47 #define FIFO_RXSIZE_MASK 0x7
48 #define FIFO_RXSIZE_OFF 0
49 #define FIFO_TXFE 0x80
50 #ifdef CONFIG_ARCH_IMX8
51 #define FIFO_RXFE 0x08
53 #define FIFO_RXFE 0x40
56 #define WATER_TXWATER_OFF 0
57 #define WATER_RXWATER_OFF 16
59 DECLARE_GLOBAL_DATA_PTR;
61 #define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
62 #define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
71 struct lpuart_serial_platdata {
73 enum lpuart_devtype devtype;
77 static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
79 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
80 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
81 *(u32 *)val = in_be32(addr);
83 *(u32 *)val = in_le32(addr);
87 static void lpuart_write32(u32 flags, u32 *addr, u32 val)
89 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
90 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
98 #ifndef CONFIG_SYS_CLK_FREQ
99 #define CONFIG_SYS_CLK_FREQ 0
102 u32 __weak get_lpuart_clk(void)
104 return CONFIG_SYS_CLK_FREQ;
107 static bool is_lpuart32(struct udevice *dev)
109 struct lpuart_serial_platdata *plat = dev->platdata;
111 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
114 static void _lpuart_serial_setbrg(struct lpuart_serial_platdata *plat,
117 struct lpuart_fsl *base = plat->reg;
118 u32 clk = get_lpuart_clk();
121 sbr = (u16)(clk / (16 * baudrate));
123 /* place adjustment later - n/32 BRFA */
124 __raw_writeb(sbr >> 8, &base->ubdh);
125 __raw_writeb(sbr & 0xff, &base->ubdl);
128 static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
130 struct lpuart_fsl *base = plat->reg;
131 while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
136 return __raw_readb(&base->ud);
139 static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
142 struct lpuart_fsl *base = plat->reg;
144 while (!(__raw_readb(&base->us1) & US1_TDRE))
147 __raw_writeb(c, &base->ud);
150 /* Test whether a character is in the RX buffer */
151 static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
153 struct lpuart_fsl *base = plat->reg;
155 if (__raw_readb(&base->urcfifo) == 0)
162 * Initialise the serial port with the given baudrate. The settings
163 * are always 8 data bits, no parity, 1 stop bit, no start bits.
165 static int _lpuart_serial_init(struct lpuart_serial_platdata *plat)
167 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
170 ctrl = __raw_readb(&base->uc2);
173 __raw_writeb(ctrl, &base->uc2);
175 __raw_writeb(0, &base->umodem);
176 __raw_writeb(0, &base->uc1);
178 /* Disable FIFO and flush buffer */
179 __raw_writeb(0x0, &base->upfifo);
180 __raw_writeb(0x0, &base->utwfifo);
181 __raw_writeb(0x1, &base->urwfifo);
182 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
184 /* provide data bits, parity, stop bit, etc */
185 _lpuart_serial_setbrg(plat, gd->baudrate);
187 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
192 static void _lpuart32_serial_setbrg_7ulp(struct lpuart_serial_platdata *plat,
195 struct lpuart_fsl_reg32 *base = plat->reg;
196 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
197 u32 clk = get_lpuart_clk();
199 baud_diff = baudrate;
203 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
204 tmp_sbr = (clk / (baudrate * tmp_osr));
209 /*calculate difference in actual buad w/ current values */
210 tmp_diff = (clk / (tmp_osr * tmp_sbr));
211 tmp_diff = tmp_diff - baudrate;
213 /* select best values between sbr and sbr+1 */
214 if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
215 tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
219 if (tmp_diff <= baud_diff) {
220 baud_diff = tmp_diff;
227 * TODO: handle buadrate outside acceptable rate
228 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
230 * Unacceptable baud rate difference of more than 3%
231 * return kStatus_LPUART_BaudrateNotSupport;
234 tmp = in_le32(&base->baud);
236 if ((osr > 3) && (osr < 8))
237 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
239 tmp &= ~LPUART_BAUD_OSR_MASK;
240 tmp |= LPUART_BAUD_OSR(osr-1);
242 tmp &= ~LPUART_BAUD_SBR_MASK;
243 tmp |= LPUART_BAUD_SBR(sbr);
245 /* explicitly disable 10 bit mode & set 1 stop bit */
246 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
248 out_le32(&base->baud, tmp);
251 static void _lpuart32_serial_setbrg(struct lpuart_serial_platdata *plat,
254 struct lpuart_fsl_reg32 *base = plat->reg;
255 u32 clk = get_lpuart_clk();
258 sbr = (clk / (16 * baudrate));
260 /* place adjustment later - n/32 BRFA */
261 lpuart_write32(plat->flags, &base->baud, sbr);
264 static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
266 struct lpuart_fsl_reg32 *base = plat->reg;
269 lpuart_read32(plat->flags, &base->stat, &stat);
270 while ((stat & STAT_RDRF) == 0) {
271 lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
273 lpuart_read32(plat->flags, &base->stat, &stat);
276 lpuart_read32(plat->flags, &base->data, &val);
278 lpuart_read32(plat->flags, &base->stat, &stat);
280 lpuart_write32(plat->flags, &base->stat, STAT_OR);
285 static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
288 struct lpuart_fsl_reg32 *base = plat->reg;
295 lpuart_read32(plat->flags, &base->stat, &stat);
297 if ((stat & STAT_TDRE))
303 lpuart_write32(plat->flags, &base->data, c);
306 /* Test whether a character is in the RX buffer */
307 static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
309 struct lpuart_fsl_reg32 *base = plat->reg;
312 lpuart_read32(plat->flags, &base->water, &water);
314 if ((water >> 24) == 0)
321 * Initialise the serial port with the given baudrate. The settings
322 * are always 8 data bits, no parity, 1 stop bit, no start bits.
324 static int _lpuart32_serial_init(struct lpuart_serial_platdata *plat)
326 struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
327 u32 val, tx_fifo_size;
329 lpuart_read32(plat->flags, &base->ctrl, &val);
332 lpuart_write32(plat->flags, &base->ctrl, val);
334 lpuart_write32(plat->flags, &base->modir, 0);
336 lpuart_read32(plat->flags, &base->fifo, &val);
337 tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
338 /* Set the TX water to half of FIFO size */
339 if (tx_fifo_size > 1)
340 tx_fifo_size = tx_fifo_size >> 1;
342 /* Set RX water to 0, to be triggered by any receive data */
343 lpuart_write32(plat->flags, &base->water,
344 (tx_fifo_size << WATER_TXWATER_OFF));
346 /* Enable TX and RX FIFO */
347 val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
348 lpuart_write32(plat->flags, &base->fifo, val);
350 lpuart_write32(plat->flags, &base->match, 0);
352 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8) {
353 _lpuart32_serial_setbrg_7ulp(plat, gd->baudrate);
355 /* provide data bits, parity, stop bit, etc */
356 _lpuart32_serial_setbrg(plat, gd->baudrate);
359 lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
364 static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
366 struct lpuart_serial_platdata *plat = dev->platdata;
368 if (is_lpuart32(dev)) {
369 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8)
370 _lpuart32_serial_setbrg_7ulp(plat, baudrate);
372 _lpuart32_serial_setbrg(plat, baudrate);
374 _lpuart_serial_setbrg(plat, baudrate);
380 static int lpuart_serial_getc(struct udevice *dev)
382 struct lpuart_serial_platdata *plat = dev->platdata;
384 if (is_lpuart32(dev))
385 return _lpuart32_serial_getc(plat);
387 return _lpuart_serial_getc(plat);
390 static int lpuart_serial_putc(struct udevice *dev, const char c)
392 struct lpuart_serial_platdata *plat = dev->platdata;
394 if (is_lpuart32(dev))
395 _lpuart32_serial_putc(plat, c);
397 _lpuart_serial_putc(plat, c);
402 static int lpuart_serial_pending(struct udevice *dev, bool input)
404 struct lpuart_serial_platdata *plat = dev->platdata;
405 struct lpuart_fsl *reg = plat->reg;
406 struct lpuart_fsl_reg32 *reg32 = plat->reg;
409 if (is_lpuart32(dev)) {
411 return _lpuart32_serial_tstc(plat);
413 lpuart_read32(plat->flags, ®32->stat, &stat);
414 return stat & STAT_TDRE ? 0 : 1;
419 return _lpuart_serial_tstc(plat);
421 return __raw_readb(®->us1) & US1_TDRE ? 0 : 1;
424 static int lpuart_serial_probe(struct udevice *dev)
426 struct lpuart_serial_platdata *plat = dev->platdata;
428 if (is_lpuart32(dev))
429 return _lpuart32_serial_init(plat);
431 return _lpuart_serial_init(plat);
434 static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
436 struct lpuart_serial_platdata *plat = dev->platdata;
437 const void *blob = gd->fdt_blob;
438 int node = dev_of_offset(dev);
441 addr = devfdt_get_addr(dev);
442 if (addr == FDT_ADDR_T_NONE)
445 plat->reg = (void *)addr;
446 plat->flags = dev_get_driver_data(dev);
448 if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
449 plat->devtype = DEV_LS1021A;
450 else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
451 plat->devtype = DEV_MX7ULP;
452 else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
453 plat->devtype = DEV_VF610;
454 else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
455 plat->devtype = DEV_IMX8;
460 static const struct dm_serial_ops lpuart_serial_ops = {
461 .putc = lpuart_serial_putc,
462 .pending = lpuart_serial_pending,
463 .getc = lpuart_serial_getc,
464 .setbrg = lpuart_serial_setbrg,
467 static const struct udevice_id lpuart_serial_ids[] = {
468 { .compatible = "fsl,ls1021a-lpuart", .data =
469 LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
470 { .compatible = "fsl,imx7ulp-lpuart",
471 .data = LPUART_FLAG_REGMAP_32BIT_REG },
472 { .compatible = "fsl,vf610-lpuart"},
473 { .compatible = "fsl,imx8qm-lpuart",
474 .data = LPUART_FLAG_REGMAP_32BIT_REG },
478 U_BOOT_DRIVER(serial_lpuart) = {
479 .name = "serial_lpuart",
481 .of_match = lpuart_serial_ids,
482 .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
483 .platdata_auto_alloc_size = sizeof(struct lpuart_serial_platdata),
484 .probe = lpuart_serial_probe,
485 .ops = &lpuart_serial_ops,
486 .flags = DM_FLAG_PRE_RELOC,