1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
5 * Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Derived from linux/drivers/tty/serial/serial_bcm6345.c
8 * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
13 #include <debug_uart.h>
17 #include <asm/types.h>
19 /* UART Control register */
20 #define UART_CTL_REG 0x0
21 #define UART_CTL_RXTIMEOUT_MASK 0x1f
22 #define UART_CTL_RXTIMEOUT_5 0x5
23 #define UART_CTL_RSTRXFIFO_SHIFT 6
24 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
25 #define UART_CTL_RSTTXFIFO_SHIFT 7
26 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
27 #define UART_CTL_STOPBITS_SHIFT 8
28 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
29 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
30 #define UART_CTL_BITSPERSYM_SHIFT 12
31 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
32 #define UART_CTL_BITSPERSYM_8 (0x3 << UART_CTL_BITSPERSYM_SHIFT)
33 #define UART_CTL_XMITBRK_SHIFT 14
34 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
35 #define UART_CTL_RSVD_SHIFT 15
36 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
37 #define UART_CTL_RXPAREVEN_SHIFT 16
38 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
39 #define UART_CTL_RXPAREN_SHIFT 17
40 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
41 #define UART_CTL_TXPAREVEN_SHIFT 18
42 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
43 #define UART_CTL_TXPAREN_SHIFT 19
44 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
45 #define UART_CTL_LOOPBACK_SHIFT 20
46 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
47 #define UART_CTL_RXEN_SHIFT 21
48 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
49 #define UART_CTL_TXEN_SHIFT 22
50 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
51 #define UART_CTL_BRGEN_SHIFT 23
52 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
54 /* UART Baudword register */
55 #define UART_BAUD_REG 0x4
57 /* UART FIFO Config register */
58 #define UART_FIFO_CFG_REG 0x8
59 #define UART_FIFO_CFG_RX_SHIFT 8
60 #define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT)
61 #define UART_FIFO_CFG_RX_4 (0x4 << UART_FIFO_CFG_RX_SHIFT)
62 #define UART_FIFO_CFG_TX_SHIFT 12
63 #define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT)
64 #define UART_FIFO_CFG_TX_4 (0x4 << UART_FIFO_CFG_TX_SHIFT)
66 /* UART Interrupt register */
67 #define UART_IR_REG 0x10
68 #define UART_IR_STAT(x) (1 << (x))
69 #define UART_IR_TXEMPTY 5
70 #define UART_IR_RXOVER 7
71 #define UART_IR_RXNOTEMPTY 11
73 /* UART FIFO register */
74 #define UART_FIFO_REG 0x14
75 #define UART_FIFO_VALID_MASK 0xff
76 #define UART_FIFO_FRAMEERR_SHIFT 8
77 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
78 #define UART_FIFO_PARERR_SHIFT 9
79 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
80 #define UART_FIFO_BRKDET_SHIFT 10
81 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
82 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
83 UART_FIFO_PARERR_MASK | \
84 UART_FIFO_BRKDET_MASK)
86 struct bcm6858_serial_priv {
91 /* enable rx & tx operation on uart */
92 static void bcm6858_serial_enable(void __iomem *base)
94 setbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
95 UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
98 /* disable rx & tx operation on uart */
99 static void bcm6858_serial_disable(void __iomem *base)
101 clrbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
102 UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
105 /* clear all unread data in rx fifo and unsent data in tx fifo */
106 static void bcm6858_serial_flush(void __iomem *base)
108 /* empty rx and tx fifo */
109 setbits_le32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
110 UART_CTL_RSTTXFIFO_MASK);
112 /* read any pending char to make sure all irq status are cleared */
113 readl(base + UART_FIFO_REG);
116 static int bcm6858_serial_init(void __iomem *base, ulong clk, u32 baudrate)
120 /* mask all irq and flush port */
121 bcm6858_serial_disable(base);
122 bcm6858_serial_flush(base);
124 /* set uart control config */
125 clrsetbits_le32(base + UART_CTL_REG,
126 /* clear rx timeout */
127 UART_CTL_RXTIMEOUT_MASK |
128 /* clear stop bits */
129 UART_CTL_STOPBITS_MASK |
130 /* clear bits per symbol */
131 UART_CTL_BITSPERSYM_MASK |
132 /* clear xmit break */
133 UART_CTL_XMITBRK_MASK |
134 /* clear reserved bit */
137 UART_CTL_RXPAREN_MASK |
138 UART_CTL_TXPAREN_MASK |
139 /* disable loopback */
140 UART_CTL_LOOPBACK_MASK,
141 /* set timeout to 5 */
142 UART_CTL_RXTIMEOUT_5 |
143 /* set 8 bits/symbol */
144 UART_CTL_BITSPERSYM_8 |
146 UART_CTL_STOPBITS_1 |
147 /* set parity to even */
148 UART_CTL_RXPAREVEN_MASK |
149 UART_CTL_TXPAREVEN_MASK);
151 /* set uart fifo config */
152 clrsetbits_le32(base + UART_FIFO_CFG_REG,
153 /* clear fifo config */
154 UART_FIFO_CFG_RX_MASK |
155 UART_FIFO_CFG_TX_MASK,
156 /* set fifo config to 4 */
161 val = ((clk / baudrate) >> 4);
165 val = (val >> 1) - 1;
166 writel(val, base + UART_BAUD_REG);
168 /* clear interrupts */
169 writel(0, base + UART_IR_REG);
172 bcm6858_serial_enable(base);
177 static int bcm6858_serial_pending(struct udevice *dev, bool input)
179 struct bcm6858_serial_priv *priv = dev_get_priv(dev);
180 u32 val = readl(priv->base + UART_IR_REG);
183 return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
185 return !(val & UART_IR_STAT(UART_IR_TXEMPTY));
188 static int bcm6858_serial_setbrg(struct udevice *dev, int baudrate)
190 struct bcm6858_serial_priv *priv = dev_get_priv(dev);
192 return bcm6858_serial_init(priv->base, priv->uartclk, baudrate);
195 static int bcm6858_serial_putc(struct udevice *dev, const char ch)
197 struct bcm6858_serial_priv *priv = dev_get_priv(dev);
200 val = readl(priv->base + UART_IR_REG);
201 if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
204 writel(ch, priv->base + UART_FIFO_REG);
209 static int bcm6858_serial_getc(struct udevice *dev)
211 struct bcm6858_serial_priv *priv = dev_get_priv(dev);
214 val = readl(priv->base + UART_IR_REG);
215 if (val & UART_IR_STAT(UART_IR_RXOVER))
216 setbits_le32(priv->base + UART_CTL_REG,
217 UART_CTL_RSTRXFIFO_MASK);
219 if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
222 val = readl(priv->base + UART_FIFO_REG);
223 if (val & UART_FIFO_ANYERR_MASK)
226 return val & UART_FIFO_VALID_MASK;
229 static int bcm6858_serial_probe(struct udevice *dev)
231 struct bcm6858_serial_priv *priv = dev_get_priv(dev);
236 priv->base = dev_remap_addr(dev);
241 ret = clk_get_by_index(dev, 0, &clk);
244 priv->uartclk = clk_get_rate(&clk);
247 /* initialize serial */
248 return bcm6858_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
251 static const struct dm_serial_ops bcm6858_serial_ops = {
252 .putc = bcm6858_serial_putc,
253 .pending = bcm6858_serial_pending,
254 .getc = bcm6858_serial_getc,
255 .setbrg = bcm6858_serial_setbrg,
258 static const struct udevice_id bcm6858_serial_ids[] = {
259 { .compatible = "brcm,bcm6858-uart" },
263 U_BOOT_DRIVER(bcm6858_serial) = {
264 .name = "bcm6858-uart",
266 .of_match = bcm6858_serial_ids,
267 .probe = bcm6858_serial_probe,
268 .priv_auto_alloc_size = sizeof(struct bcm6858_serial_priv),
269 .ops = &bcm6858_serial_ops,
270 .flags = DM_FLAG_PRE_RELOC,
273 #ifdef CONFIG_DEBUG_UART_BCM6858
274 static inline void _debug_uart_init(void)
276 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
278 bcm6858_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
281 static inline void wait_xfered(void __iomem *base)
284 u32 val = readl(base + UART_IR_REG);
285 if (val & UART_IR_STAT(UART_IR_TXEMPTY))
290 static inline void _debug_uart_putc(int ch)
292 void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
295 writel(ch, base + UART_FIFO_REG);