drivers/serial/atmel_usart.c

   1 /*
   2  * Copyright (C) 2004-2006 Atmel Corporation
   3  *
   4  * Modified to support C structur SoC access by
   5  * Andreas Bießmann <biessmann@corscience.de>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <watchdog.h>
  14 #include <serial.h>
  15 #include <debug_uart.h>
  16 #include <linux/compiler.h>
  17
  18 #include <asm/io.h>
  19 #ifdef CONFIG_DM_SERIAL
  20 #include <asm/arch/atmel_serial.h>
  21 #endif
  22 #include <asm/arch/clk.h>
  23 #include <asm/arch/hardware.h>
  24
  25 #include "atmel_usart.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifndef CONFIG_DM_SERIAL
  30 static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
  31                                          int baudrate)
  32 {
  33         unsigned long divisor;
  34         unsigned long usart_hz;
  35
  36         /*
  37          *              Master Clock
  38          * Baud Rate = --------------
  39          *                16 * CD
  40          */
  41         usart_hz = get_usart_clk_rate(id);
  42         divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
  43         writel(USART3_BF(CD, divisor), &usart->brgr);
  44 }
  45
  46 static void atmel_serial_init_internal(atmel_usart3_t *usart)
  47 {
  48         /*
  49          * Just in case: drain transmitter register
  50          * 1000us is enough for baudrate >= 9600
  51          */
  52         if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
  53                 __udelay(1000);
  54
  55         writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
  56 }
  57
  58 static void atmel_serial_activate(atmel_usart3_t *usart)
  59 {
  60         writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
  61                            | USART3_BF(USCLKS, USART3_USCLKS_MCK)
  62                            | USART3_BF(CHRL, USART3_CHRL_8)
  63                            | USART3_BF(PAR, USART3_PAR_NONE)
  64                            | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
  65                            &usart->mr);
  66         writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
  67         /* 100us is enough for the new settings to be settled */
  68         __udelay(100);
  69 }
  70
  71 static void atmel_serial_setbrg(void)
  72 {
  73         atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
  74                                      CONFIG_USART_ID, gd->baudrate);
  75 }
  76
  77 static int atmel_serial_init(void)
  78 {
  79         atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
  80
  81         atmel_serial_init_internal(usart);
  82         serial_setbrg();
  83         atmel_serial_activate(usart);
  84
  85         return 0;
  86 }
  87
  88 static void atmel_serial_putc(char c)
  89 {
  90         atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
  91
  92         if (c == '\n')
  93                 serial_putc('\r');
  94
  95         while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
  96         writel(c, &usart->thr);
  97 }
  98
  99 static int atmel_serial_getc(void)
 100 {
 101         atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
 102
 103         while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
 104                  WATCHDOG_RESET();
 105         return readl(&usart->rhr);
 106 }
 107
 108 static int atmel_serial_tstc(void)
 109 {
 110         atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
 111         return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
 112 }
 113
 114 static struct serial_device atmel_serial_drv = {
 115         .name   = "atmel_serial",
 116         .start  = atmel_serial_init,
 117         .stop   = NULL,
 118         .setbrg = atmel_serial_setbrg,
 119         .putc   = atmel_serial_putc,
 120         .puts   = default_serial_puts,
 121         .getc   = atmel_serial_getc,
 122         .tstc   = atmel_serial_tstc,
 123 };
 124
 125 void atmel_serial_initialize(void)
 126 {
 127         serial_register(&atmel_serial_drv);
 128 }
 129
 130 __weak struct serial_device *default_serial_console(void)
 131 {
 132         return &atmel_serial_drv;
 133 }
 134 #endif
 135
 136 #ifdef CONFIG_DM_SERIAL
 137 enum serial_clk_type {
 138         CLK_TYPE_NORMAL = 0,
 139         CLK_TYPE_DBGU,
 140 };
 141
 142 struct atmel_serial_priv {
 143         atmel_usart3_t *usart;
 144         ulong usart_clk_rate;
 145 };
 146
 147 static void _atmel_serial_set_brg(atmel_usart3_t *usart,
 148                                   ulong usart_clk_rate, int baudrate)
 149 {
 150         unsigned long divisor;
 151
 152         divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
 153         writel(USART3_BF(CD, divisor), &usart->brgr);
 154 }
 155
 156 void _atmel_serial_init(atmel_usart3_t *usart,
 157                         ulong usart_clk_rate, int baudrate)
 158 {
 159         writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);
 160
 161         writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
 162                 USART3_BF(USCLKS, USART3_USCLKS_MCK) |
 163                 USART3_BF(CHRL, USART3_CHRL_8) |
 164                 USART3_BF(PAR, USART3_PAR_NONE) |
 165                 USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
 166
 167         _atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
 168
 169         writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
 170         writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
 171 }
 172
 173 int atmel_serial_setbrg(struct udevice *dev, int baudrate)
 174 {
 175         struct atmel_serial_priv *priv = dev_get_priv(dev);
 176
 177         _atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
 178
 179         return 0;
 180 }
 181
 182 static int atmel_serial_getc(struct udevice *dev)
 183 {
 184         struct atmel_serial_priv *priv = dev_get_priv(dev);
 185
 186         if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
 187                 return -EAGAIN;
 188
 189         return readl(&priv->usart->rhr);
 190 }
 191
 192 static int atmel_serial_putc(struct udevice *dev, const char ch)
 193 {
 194         struct atmel_serial_priv *priv = dev_get_priv(dev);
 195
 196         if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
 197                 return -EAGAIN;
 198
 199         writel(ch, &priv->usart->thr);
 200
 201         return 0;
 202 }
 203
 204 static int atmel_serial_pending(struct udevice *dev, bool input)
 205 {
 206         struct atmel_serial_priv *priv = dev_get_priv(dev);
 207         uint32_t csr = readl(&priv->usart->csr);
 208
 209         if (input)
 210                 return csr & USART3_BIT(RXRDY) ? 1 : 0;
 211         else
 212                 return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
 213 }
 214
 215 static const struct dm_serial_ops atmel_serial_ops = {
 216         .putc = atmel_serial_putc,
 217         .pending = atmel_serial_pending,
 218         .getc = atmel_serial_getc,
 219         .setbrg = atmel_serial_setbrg,
 220 };
 221
 222 static int atmel_serial_enable_clk(struct udevice *dev)
 223 {
 224         struct atmel_serial_priv *priv = dev_get_priv(dev);
 225         struct clk clk;
 226         ulong clk_rate;
 227         int ret;
 228
 229         ret = clk_get_by_index(dev, 0, &clk);
 230         if (ret)
 231                 return -EINVAL;
 232
 233         if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
 234                 ret = clk_enable(&clk);
 235                 if (ret)
 236                         return ret;
 237         }
 238
 239         clk_rate = clk_get_rate(&clk);
 240         if (!clk_rate)
 241                 return -EINVAL;
 242
 243         priv->usart_clk_rate = clk_rate;
 244
 245         clk_free(&clk);
 246
 247         return 0;
 248 }
 249
 250 static int atmel_serial_probe(struct udevice *dev)
 251 {
 252         struct atmel_serial_platdata *plat = dev->platdata;
 253         struct atmel_serial_priv *priv = dev_get_priv(dev);
 254         int ret;
 255 #if CONFIG_IS_ENABLED(OF_CONTROL)
 256         fdt_addr_t addr_base;
 257
 258         addr_base = dev_get_addr(dev);
 259         if (addr_base == FDT_ADDR_T_NONE)
 260                 return -ENODEV;
 261
 262         plat->base_addr = (uint32_t)addr_base;
 263 #endif
 264         priv->usart = (atmel_usart3_t *)plat->base_addr;
 265
 266         ret = atmel_serial_enable_clk(dev);
 267         if (ret)
 268                 return ret;
 269
 270         _atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
 271
 272         return 0;
 273 }
 274
 275 #if CONFIG_IS_ENABLED(OF_CONTROL)
 276 static const struct udevice_id atmel_serial_ids[] = {
 277         {
 278                 .compatible = "atmel,at91sam9260-dbgu",
 279                 .data = CLK_TYPE_DBGU,
 280         },
 281         {
 282                 .compatible = "atmel,at91sam9260-usart",
 283                 .data = CLK_TYPE_NORMAL,
 284         },
 285         { }
 286 };
 287 #endif
 288
 289 U_BOOT_DRIVER(serial_atmel) = {
 290         .name   = "serial_atmel",
 291         .id     = UCLASS_SERIAL,
 292 #if CONFIG_IS_ENABLED(OF_CONTROL)
 293         .of_match = atmel_serial_ids,
 294         .platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
 295 #endif
 296         .probe = atmel_serial_probe,
 297         .ops    = &atmel_serial_ops,
 298         .flags = DM_FLAG_PRE_RELOC,
 299         .priv_auto_alloc_size   = sizeof(struct atmel_serial_priv),
 300 };
 301 #endif
 302
 303 #ifdef CONFIG_DEBUG_UART_ATMEL
 304 static inline void _debug_uart_init(void)
 305 {
 306         atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
 307
 308         _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
 309 }
 310
 311 static inline void _debug_uart_putc(int ch)
 312 {
 313         atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
 314
 315         while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
 316                 ;
 317
 318         writel(ch, &usart->thr);
 319 }
 320
 321 DEBUG_UART_FUNCS
 322 #endif