1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
11 #include <dm/device_compat.h>
12 #include <linux/iopoll.h>
14 #define STM32_RTC_TR 0x00
15 #define STM32_RTC_DR 0x04
16 #define STM32_RTC_ISR 0x0C
17 #define STM32_RTC_PRER 0x10
18 #define STM32_RTC_CR 0x18
19 #define STM32_RTC_WPR 0x24
21 /* STM32_RTC_TR bit fields */
22 #define STM32_RTC_SEC_SHIFT 0
23 #define STM32_RTC_SEC GENMASK(6, 0)
24 #define STM32_RTC_MIN_SHIFT 8
25 #define STM32_RTC_MIN GENMASK(14, 8)
26 #define STM32_RTC_HOUR_SHIFT 16
27 #define STM32_RTC_HOUR GENMASK(21, 16)
29 /* STM32_RTC_DR bit fields */
30 #define STM32_RTC_DATE_SHIFT 0
31 #define STM32_RTC_DATE GENMASK(5, 0)
32 #define STM32_RTC_MONTH_SHIFT 8
33 #define STM32_RTC_MONTH GENMASK(12, 8)
34 #define STM32_RTC_WDAY_SHIFT 13
35 #define STM32_RTC_WDAY GENMASK(15, 13)
36 #define STM32_RTC_YEAR_SHIFT 16
37 #define STM32_RTC_YEAR GENMASK(23, 16)
39 /* STM32_RTC_CR bit fields */
40 #define STM32_RTC_CR_FMT BIT(6)
42 /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
43 #define STM32_RTC_ISR_INITS BIT(4)
44 #define STM32_RTC_ISR_RSF BIT(5)
45 #define STM32_RTC_ISR_INITF BIT(6)
46 #define STM32_RTC_ISR_INIT BIT(7)
48 /* STM32_RTC_PRER bit fields */
49 #define STM32_RTC_PRER_PRED_S_SHIFT 0
50 #define STM32_RTC_PRER_PRED_S GENMASK(14, 0)
51 #define STM32_RTC_PRER_PRED_A_SHIFT 16
52 #define STM32_RTC_PRER_PRED_A GENMASK(22, 16)
54 /* STM32_RTC_WPR key constants */
55 #define RTC_WPR_1ST_KEY 0xCA
56 #define RTC_WPR_2ND_KEY 0x53
57 #define RTC_WPR_WRONG_KEY 0xFF
59 struct stm32_rtc_priv {
63 static int stm32_rtc_get(struct udevice *dev, struct rtc_time *tm)
65 struct stm32_rtc_priv *priv = dev_get_priv(dev);
68 tr = readl(priv->base + STM32_RTC_TR);
69 dr = readl(priv->base + STM32_RTC_DR);
71 tm->tm_sec = bcd2bin((tr & STM32_RTC_SEC) >> STM32_RTC_SEC_SHIFT);
72 tm->tm_min = bcd2bin((tr & STM32_RTC_MIN) >> STM32_RTC_MIN_SHIFT);
73 tm->tm_hour = bcd2bin((tr & STM32_RTC_HOUR) >> STM32_RTC_HOUR_SHIFT);
75 tm->tm_mday = bcd2bin((dr & STM32_RTC_DATE) >> STM32_RTC_DATE_SHIFT);
76 tm->tm_mon = bcd2bin((dr & STM32_RTC_MONTH) >> STM32_RTC_MONTH_SHIFT);
78 bcd2bin((dr & STM32_RTC_YEAR) >> STM32_RTC_YEAR_SHIFT);
79 tm->tm_wday = bcd2bin((dr & STM32_RTC_WDAY) >> STM32_RTC_WDAY_SHIFT);
83 dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
84 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
85 tm->tm_hour, tm->tm_min, tm->tm_sec);
90 static void stm32_rtc_unlock(struct udevice *dev)
92 struct stm32_rtc_priv *priv = dev_get_priv(dev);
94 writel(RTC_WPR_1ST_KEY, priv->base + STM32_RTC_WPR);
95 writel(RTC_WPR_2ND_KEY, priv->base + STM32_RTC_WPR);
98 static void stm32_rtc_lock(struct udevice *dev)
100 struct stm32_rtc_priv *priv = dev_get_priv(dev);
102 writel(RTC_WPR_WRONG_KEY, priv->base + STM32_RTC_WPR);
105 static int stm32_rtc_enter_init_mode(struct udevice *dev)
107 struct stm32_rtc_priv *priv = dev_get_priv(dev);
108 u32 isr = readl(priv->base + STM32_RTC_ISR);
110 if (!(isr & STM32_RTC_ISR_INITF)) {
111 isr |= STM32_RTC_ISR_INIT;
112 writel(isr, priv->base + STM32_RTC_ISR);
114 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
116 (isr & STM32_RTC_ISR_INITF),
123 static int stm32_rtc_wait_sync(struct udevice *dev)
125 struct stm32_rtc_priv *priv = dev_get_priv(dev);
126 u32 isr = readl(priv->base + STM32_RTC_ISR);
128 isr &= ~STM32_RTC_ISR_RSF;
129 writel(isr, priv->base + STM32_RTC_ISR);
132 * Wait for RSF to be set to ensure the calendar registers are
133 * synchronised, it takes around 2 rtc_ck clock cycles
135 return readl_poll_timeout(priv->base + STM32_RTC_ISR,
136 isr, (isr & STM32_RTC_ISR_RSF),
140 static void stm32_rtc_exit_init_mode(struct udevice *dev)
142 struct stm32_rtc_priv *priv = dev_get_priv(dev);
143 u32 isr = readl(priv->base + STM32_RTC_ISR);
145 isr &= ~STM32_RTC_ISR_INIT;
146 writel(isr, priv->base + STM32_RTC_ISR);
149 static int stm32_rtc_set_time(struct udevice *dev, u32 time, u32 date)
151 struct stm32_rtc_priv *priv = dev_get_priv(dev);
154 stm32_rtc_unlock(dev);
156 ret = stm32_rtc_enter_init_mode(dev);
160 writel(time, priv->base + STM32_RTC_TR);
161 writel(date, priv->base + STM32_RTC_DR);
163 stm32_rtc_exit_init_mode(dev);
165 ret = stm32_rtc_wait_sync(dev);
172 static int stm32_rtc_set(struct udevice *dev, const struct rtc_time *tm)
176 dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
177 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
178 tm->tm_hour, tm->tm_min, tm->tm_sec);
180 if (tm->tm_year < 2000 || tm->tm_year > 2099)
183 /* Time in BCD format */
184 t = (bin2bcd(tm->tm_sec) << STM32_RTC_SEC_SHIFT) & STM32_RTC_SEC;
185 t |= (bin2bcd(tm->tm_min) << STM32_RTC_MIN_SHIFT) & STM32_RTC_MIN;
186 t |= (bin2bcd(tm->tm_hour) << STM32_RTC_HOUR_SHIFT) & STM32_RTC_HOUR;
188 /* Date in BCD format */
189 d = (bin2bcd(tm->tm_mday) << STM32_RTC_DATE_SHIFT) & STM32_RTC_DATE;
190 d |= (bin2bcd(tm->tm_mon) << STM32_RTC_MONTH_SHIFT) & STM32_RTC_MONTH;
191 d |= (bin2bcd(tm->tm_year - 2000) << STM32_RTC_YEAR_SHIFT) &
193 d |= (bin2bcd(tm->tm_wday) << STM32_RTC_WDAY_SHIFT) & STM32_RTC_WDAY;
195 return stm32_rtc_set_time(dev, t, d);
198 static int stm32_rtc_reset(struct udevice *dev)
200 dev_dbg(dev, "Reset DATE\n");
202 return stm32_rtc_set_time(dev, 0, 0);
205 static int stm32_rtc_init(struct udevice *dev)
207 struct stm32_rtc_priv *priv = dev_get_priv(dev);
208 unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
212 u32 isr = readl(priv->base + STM32_RTC_ISR);
214 if (isr & STM32_RTC_ISR_INITS)
217 ret = clk_get_by_index(dev, 1, &clk);
221 ret = clk_enable(&clk);
227 rate = clk_get_rate(&clk);
229 /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
230 pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
231 pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
233 for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
234 pred_s = (rate / (pred_a + 1)) - 1;
236 if (((pred_s + 1) * (pred_a + 1)) == rate)
241 * Can't find a 1Hz, so give priority to RTC power consumption
242 * by choosing the higher possible value for prediv_a
244 if (pred_s > pred_s_max || pred_a > pred_a_max) {
246 pred_s = (rate / (pred_a + 1)) - 1;
249 stm32_rtc_unlock(dev);
251 ret = stm32_rtc_enter_init_mode(dev);
254 "Can't enter in init mode. Prescaler config failed.\n");
258 prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
259 prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
260 writel(prer, priv->base + STM32_RTC_PRER);
262 /* Force 24h time format */
263 cr = readl(priv->base + STM32_RTC_CR);
264 cr &= ~STM32_RTC_CR_FMT;
265 writel(cr, priv->base + STM32_RTC_CR);
267 stm32_rtc_exit_init_mode(dev);
269 ret = stm32_rtc_wait_sync(dev);
282 static int stm32_rtc_probe(struct udevice *dev)
284 struct stm32_rtc_priv *priv = dev_get_priv(dev);
288 priv->base = dev_read_addr(dev);
289 if (priv->base == FDT_ADDR_T_NONE)
292 ret = clk_get_by_index(dev, 0, &clk);
296 ret = clk_enable(&clk);
302 ret = stm32_rtc_init(dev);
312 static const struct rtc_ops stm32_rtc_ops = {
313 .get = stm32_rtc_get,
314 .set = stm32_rtc_set,
315 .reset = stm32_rtc_reset,
318 static const struct udevice_id stm32_rtc_ids[] = {
319 { .compatible = "st,stm32mp1-rtc" },
323 U_BOOT_DRIVER(rtc_stm32) = {
326 .probe = stm32_rtc_probe,
327 .of_match = stm32_rtc_ids,
328 .ops = &stm32_rtc_ops,
329 .priv_auto_alloc_size = sizeof(struct stm32_rtc_priv),