1 // SPDX-License-Identifier: GPL-2.0+
4 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de.
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * based on a the Linux rtc-m41t80.c driver which is:
10 * Alexander Bigga <ab@mycable.de>, 2006 (c) mycable GmbH
14 * Date & Time support for STMicroelectronics M41T62
26 #define M41T62_REG_SSEC 0
27 #define M41T62_REG_SEC 1
28 #define M41T62_REG_MIN 2
29 #define M41T62_REG_HOUR 3
30 #define M41T62_REG_WDAY 4
31 #define M41T62_REG_DAY 5
32 #define M41T62_REG_MON 6
33 #define M41T62_REG_YEAR 7
34 #define M41T62_REG_ALARM_MON 0xa
35 #define M41T62_REG_ALARM_DAY 0xb
36 #define M41T62_REG_ALARM_HOUR 0xc
37 #define M41T62_REG_ALARM_MIN 0xd
38 #define M41T62_REG_ALARM_SEC 0xe
39 #define M41T62_REG_FLAGS 0xf
41 #define M41T62_DATETIME_REG_SIZE (M41T62_REG_YEAR + 1)
42 #define M41T62_ALARM_REG_SIZE \
43 (M41T62_REG_ALARM_SEC + 1 - M41T62_REG_ALARM_MON)
45 #define M41T62_SEC_ST (1 << 7) /* ST: Stop Bit */
46 #define M41T62_ALMON_AFE (1 << 7) /* AFE: AF Enable Bit */
47 #define M41T62_ALMON_SQWE (1 << 6) /* SQWE: SQW Enable Bit */
48 #define M41T62_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
49 #define M41T62_FLAGS_AF (1 << 6) /* AF: Alarm Flag Bit */
50 #define M41T62_FLAGS_BATT_LOW (1 << 4) /* BL: Battery Low Bit */
52 #define M41T62_FEATURE_HT (1 << 0)
53 #define M41T62_FEATURE_BL (1 << 1)
55 #define M41T80_ALHOUR_HT (1 << 6) /* HT: Halt Update Bit */
57 static void m41t62_update_rtc_time(struct rtc_time *tm, u8 *buf)
59 debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
60 "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
62 buf[0], buf[1], buf[2], buf[3],
63 buf[4], buf[5], buf[6], buf[7]);
65 tm->tm_sec = bcd2bin(buf[M41T62_REG_SEC] & 0x7f);
66 tm->tm_min = bcd2bin(buf[M41T62_REG_MIN] & 0x7f);
67 tm->tm_hour = bcd2bin(buf[M41T62_REG_HOUR] & 0x3f);
68 tm->tm_mday = bcd2bin(buf[M41T62_REG_DAY] & 0x3f);
69 tm->tm_wday = buf[M41T62_REG_WDAY] & 0x07;
70 tm->tm_mon = bcd2bin(buf[M41T62_REG_MON] & 0x1f);
72 /* assume 20YY not 19YY, and ignore the Century Bit */
73 /* U-Boot needs to add 1900 here */
74 tm->tm_year = bcd2bin(buf[M41T62_REG_YEAR]) + 100 + 1900;
76 debug("%s: tm is secs=%d, mins=%d, hours=%d, "
77 "mday=%d, mon=%d, year=%d, wday=%d\n",
79 tm->tm_sec, tm->tm_min, tm->tm_hour,
80 tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
83 static void m41t62_set_rtc_buf(const struct rtc_time *tm, u8 *buf)
85 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
86 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
87 tm->tm_hour, tm->tm_min, tm->tm_sec);
89 /* Merge time-data and register flags into buf[0..7] */
90 buf[M41T62_REG_SSEC] = 0;
92 bin2bcd(tm->tm_sec) | (buf[M41T62_REG_SEC] & ~0x7f);
94 bin2bcd(tm->tm_min) | (buf[M41T62_REG_MIN] & ~0x7f);
95 buf[M41T62_REG_HOUR] =
96 bin2bcd(tm->tm_hour) | (buf[M41T62_REG_HOUR] & ~0x3f) ;
97 buf[M41T62_REG_WDAY] =
98 (tm->tm_wday & 0x07) | (buf[M41T62_REG_WDAY] & ~0x07);
100 bin2bcd(tm->tm_mday) | (buf[M41T62_REG_DAY] & ~0x3f);
101 buf[M41T62_REG_MON] =
102 bin2bcd(tm->tm_mon) | (buf[M41T62_REG_MON] & ~0x1f);
103 /* assume 20YY not 19YY */
104 buf[M41T62_REG_YEAR] = bin2bcd(tm->tm_year % 100);
108 static int m41t62_rtc_get(struct udevice *dev, struct rtc_time *tm)
110 u8 buf[M41T62_DATETIME_REG_SIZE];
113 ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
117 m41t62_update_rtc_time(tm, buf);
122 static int m41t62_rtc_set(struct udevice *dev, const struct rtc_time *tm)
124 u8 buf[M41T62_DATETIME_REG_SIZE];
127 ret = dm_i2c_read(dev, 0, buf, sizeof(buf));
131 m41t62_set_rtc_buf(tm, buf);
133 ret = dm_i2c_write(dev, 0, buf, sizeof(buf));
135 printf("I2C write failed in %s()\n", __func__);
142 static int m41t62_rtc_reset(struct udevice *dev)
147 * M41T82: Make sure HT (Halt Update) bit is cleared.
148 * This bit is 0 in M41T62 so its save to clear it always.
151 int ret = dm_i2c_read(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
153 val &= ~M41T80_ALHOUR_HT;
154 ret |= dm_i2c_write(dev, M41T62_REG_ALARM_HOUR, &val, sizeof(val));
160 * Make sure HT bit is cleared. This bit is set on entering battery backup
161 * mode, so do this before the first read access.
163 static int m41t62_rtc_probe(struct udevice *dev)
165 return m41t62_rtc_reset(dev);
168 static const struct rtc_ops m41t62_rtc_ops = {
169 .get = m41t62_rtc_get,
170 .set = m41t62_rtc_set,
171 .reset = m41t62_rtc_reset,
174 static const struct udevice_id m41t62_rtc_ids[] = {
175 { .compatible = "st,m41t62" },
176 { .compatible = "st,m41t82" },
177 { .compatible = "st,m41st87" },
178 { .compatible = "microcrystal,rv4162" },
182 U_BOOT_DRIVER(rtc_m41t62) = {
183 .name = "rtc-m41t62",
185 .of_match = m41t62_rtc_ids,
186 .ops = &m41t62_rtc_ops,
187 .probe = &m41t62_rtc_probe,
190 #else /* NON DM RTC code - will be removed */
191 int rtc_get(struct rtc_time *tm)
193 u8 buf[M41T62_DATETIME_REG_SIZE];
195 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
196 m41t62_update_rtc_time(tm, buf);
201 int rtc_set(struct rtc_time *tm)
203 u8 buf[M41T62_DATETIME_REG_SIZE];
205 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf, M41T62_DATETIME_REG_SIZE);
206 m41t62_set_rtc_buf(tm, buf);
208 if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, buf,
209 M41T62_DATETIME_REG_SIZE)) {
210 printf("I2C write failed in %s()\n", __func__);
222 * M41T82: Make sure HT (Halt Update) bit is cleared.
223 * This bit is 0 in M41T62 so its save to clear it always.
225 i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
226 val &= ~M41T80_ALHOUR_HT;
227 i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T62_REG_ALARM_HOUR, 1, &val, 1);
229 #endif /* CONFIG_DM_RTC */