1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
5 #include <asm/arch-rockchip/hardware.h>
9 #include <linux/bitops.h>
10 #include <linux/iopoll.h>
11 #include <linux/string.h>
14 #define RK_HW_RNG_MAX 32
16 #define _SBF(s, v) ((v) << (s))
18 /* start of CRYPTO V1 register define */
19 #define CRYPTO_V1_CTRL 0x0008
20 #define CRYPTO_V1_RNG_START BIT(8)
21 #define CRYPTO_V1_RNG_FLUSH BIT(9)
23 #define CRYPTO_V1_TRNG_CTRL 0x0200
24 #define CRYPTO_V1_OSC_ENABLE BIT(16)
25 #define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
27 #define CRYPTO_V1_TRNG_DOUT_0 0x0204
28 /* end of CRYPTO V1 register define */
30 /* start of CRYPTO V2 register define */
31 #define CRYPTO_V2_RNG_CTL 0x0400
32 #define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
33 #define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
34 #define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
35 #define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
36 #define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
37 #define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
38 #define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
39 #define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
40 #define CRYPTO_V2_RNG_ENABLE BIT(1)
41 #define CRYPTO_V2_RNG_START BIT(0)
42 #define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
43 #define CRYPTO_V2_RNG_DOUT_0 0x0410
44 /* end of CRYPTO V2 register define */
46 #define RK_RNG_TIME_OUT 50000 /* max 50ms */
48 struct rk_rng_soc_data {
49 int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
52 struct rk_rng_platdata {
54 struct rk_rng_soc_data *soc_data;
57 static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
59 u32 count = RK_HW_RNG_MAX / sizeof(u32);
62 if (size > RK_HW_RNG_MAX)
65 while (size && count) {
67 tmp_len = min(size, sizeof(u32));
68 memcpy(buf, ®, tmp_len);
78 static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
80 struct rk_rng_platdata *pdata = dev_get_priv(dev);
84 if (len > RK_HW_RNG_MAX)
87 /* enable osc_ring to get entropy, sample period is set as 100 */
88 writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100),
89 pdata->base + CRYPTO_V1_TRNG_CTRL);
91 rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START,
94 retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg,
95 !(reg & CRYPTO_V1_RNG_START),
100 rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len);
104 rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START);
109 static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
111 struct rk_rng_platdata *pdata = dev_get_priv(dev);
115 if (len > RK_HW_RNG_MAX)
118 /* enable osc_ring to get entropy, sample period is set as 100 */
119 writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT);
121 reg |= CRYPTO_V2_RNG_256_BIT_LEN;
122 reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
123 reg |= CRYPTO_V2_RNG_ENABLE;
124 reg |= CRYPTO_V2_RNG_START;
126 rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg);
128 retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg,
129 !(reg & CRYPTO_V2_RNG_START),
134 rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len);
138 rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff);
143 static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
145 unsigned char *buf = data;
149 struct rk_rng_platdata *pdata = dev_get_priv(dev);
154 if (!pdata->soc_data || !pdata->soc_data->rk_rng_read)
157 for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) {
158 ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX);
163 if (len % RK_HW_RNG_MAX)
164 ret = pdata->soc_data->rk_rng_read(dev, buf,
165 len % RK_HW_RNG_MAX);
171 static int rockchip_rng_ofdata_to_platdata(struct udevice *dev)
173 struct rk_rng_platdata *pdata = dev_get_priv(dev);
175 memset(pdata, 0x00, sizeof(*pdata));
177 pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev);
184 static int rockchip_rng_probe(struct udevice *dev)
186 struct rk_rng_platdata *pdata = dev_get_priv(dev);
188 pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
193 static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
194 .rk_rng_read = rk_v1_rng_read,
197 static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
198 .rk_rng_read = rk_v2_rng_read,
201 static const struct dm_rng_ops rockchip_rng_ops = {
202 .read = rockchip_rng_read,
205 static const struct udevice_id rockchip_rng_match[] = {
207 .compatible = "rockchip,cryptov1-rng",
208 .data = (ulong)&rk_rng_v1_soc_data,
211 .compatible = "rockchip,cryptov2-rng",
212 .data = (ulong)&rk_rng_v2_soc_data,
217 U_BOOT_DRIVER(rockchip_rng) = {
218 .name = "rockchip-rng",
220 .of_match = rockchip_rng_match,
221 .ops = &rockchip_rng_ops,
222 .probe = rockchip_rng_probe,
223 .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata,
224 .priv_auto_alloc_size = sizeof(struct rk_rng_platdata),