3 * Patrice Chotard <patrice.chotard@st.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <reset-uclass.h>
15 #include <dt-bindings/reset/stih407-resets.h>
17 DECLARE_GLOBAL_DATA_PTR;
20 const struct syscfg_reset_controller_data *data;
24 * Reset channel description for a system configuration register based
27 * @compatible: Compatible string of the syscon containing this
28 * channel's control and ack (status) bits.
29 * @reset_offset: Reset register offset in sysconf bank.
30 * @reset_bit: Bit number in reset register.
31 * @ack_offset: Ack reset register offset in syscon bank.
32 * @ack_bit: Bit number in Ack reset register.
35 struct syscfg_reset_channel_data {
36 const char *compatible;
44 * Description of a system configuration register based reset controller.
46 * @wait_for_ack: The controller will wait for reset assert and de-assert to
47 * be "ack'd" in a channel's ack field.
48 * @active_low: Are the resets in this controller active low, i.e. clearing
49 * the reset bit puts the hardware into reset.
50 * @nr_channels: The number of reset channels in this controller.
51 * @channels: An array of reset channel descriptions.
53 struct syscfg_reset_controller_data {
57 const struct syscfg_reset_channel_data *channels;
60 /* STiH407 Peripheral powerdown definitions. */
61 static const char stih407_core[] = "st,stih407-core-syscfg";
62 static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
63 static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
65 #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
67 .reset_offset = _rr, \
72 #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
74 .reset_offset = _rr, \
77 #define STIH407_SRST_CORE(_reg, _bit) \
78 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
80 #define STIH407_SRST_SBC(_reg, _bit) \
81 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
83 #define STIH407_SRST_LPM(_reg, _bit) \
84 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
86 #define STIH407_PDN_0(_bit) \
87 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
88 #define STIH407_PDN_1(_bit) \
89 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
90 #define STIH407_PDN_ETH(_bit, _stat) \
91 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
93 /* Powerdown requests control 0 */
94 #define SYSCFG_5000 0x0
95 #define SYSSTAT_5500 0x7d0
96 /* Powerdown requests control 1 (High Speed Links) */
97 #define SYSCFG_5001 0x4
98 #define SYSSTAT_5501 0x7d4
100 /* Ethernet powerdown/status/reset */
101 #define SYSCFG_4032 0x80
102 #define SYSSTAT_4520 0x820
103 #define SYSCFG_4002 0x8
105 static const struct syscfg_reset_channel_data stih407_powerdowns[] = {
106 [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
107 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
108 [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
109 [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
110 [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
111 [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
112 [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
113 [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
114 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
115 [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
118 /* Reset Generator control 0/1 */
119 #define SYSCFG_5128 0x200
120 #define SYSCFG_5131 0x20c
121 #define SYSCFG_5132 0x210
123 #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
125 static const struct syscfg_reset_channel_data stih407_softresets[] = {
126 [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
127 [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
128 [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
129 [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
130 [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
131 [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
132 [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
133 [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
134 [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
135 [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
136 [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
137 [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
138 [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
139 [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
140 [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
141 [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
142 [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
143 [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
144 [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
145 [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
146 [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
147 [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
148 [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
149 [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
150 [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
151 [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
152 [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
153 [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
154 [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
155 [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
156 [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
157 [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
158 [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
161 /* PicoPHY reset/control */
162 #define SYSCFG_5061 0x0f4
164 static const struct syscfg_reset_channel_data stih407_picophyresets[] = {
165 [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
166 [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
167 [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
171 syscfg_reset_controller_data stih407_powerdown_controller = {
172 .wait_for_ack = true,
173 .nr_channels = ARRAY_SIZE(stih407_powerdowns),
174 .channels = stih407_powerdowns,
178 syscfg_reset_controller_data stih407_softreset_controller = {
179 .wait_for_ack = false,
181 .nr_channels = ARRAY_SIZE(stih407_softresets),
182 .channels = stih407_softresets,
186 syscfg_reset_controller_data stih407_picophyreset_controller = {
187 .wait_for_ack = false,
188 .nr_channels = ARRAY_SIZE(stih407_picophyresets),
189 .channels = stih407_picophyresets,
192 phys_addr_t sti_reset_get_regmap(const char *compatible)
194 struct udevice *syscon;
195 struct regmap *regmap;
198 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
201 error("unable to find %s node\n", compatible);
205 ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
207 error("%s: uclass_get_device_by_of_offset failed: %d\n",
212 regmap = syscon_get_regmap(syscon);
214 error("unable to get regmap for %s\n", syscon->name);
221 static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
223 struct udevice *dev = reset_ctl->dev;
224 struct syscfg_reset_controller_data *reset_desc =
225 (struct syscfg_reset_controller_data *)(dev->driver_data);
226 struct syscfg_reset_channel_data ch;
228 u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
231 /* check if reset id is inside available range */
232 if (reset_ctl->id >= reset_desc->nr_channels)
235 /* get reset sysconf register base address */
236 base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
238 ch = reset_desc->channels[reset_ctl->id];
239 reg = (void __iomem *)base + ch.reset_offset;
242 generic_set_bit(ch.reset_bit, reg);
244 generic_clear_bit(ch.reset_bit, reg);
246 if (!reset_desc->wait_for_ack)
249 reg = (void __iomem *)base + ch.ack_offset;
250 if (wait_for_bit(__func__, reg, BIT(ch.ack_bit), ctrl_val,
252 error("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
253 reset_ctl, reset_ctl->dev, reset_ctl->id);
261 static int sti_reset_request(struct reset_ctl *reset_ctl)
266 static int sti_reset_free(struct reset_ctl *reset_ctl)
271 static int sti_reset_assert(struct reset_ctl *reset_ctl)
273 return sti_reset_program_hw(reset_ctl, true);
276 static int sti_reset_deassert(struct reset_ctl *reset_ctl)
278 return sti_reset_program_hw(reset_ctl, false);
281 struct reset_ops sti_reset_ops = {
282 .request = sti_reset_request,
283 .free = sti_reset_free,
284 .rst_assert = sti_reset_assert,
285 .rst_deassert = sti_reset_deassert,
288 static int sti_reset_probe(struct udevice *dev)
290 struct sti_reset *priv = dev_get_priv(dev);
292 priv->data = (void *)dev_get_driver_data(dev);
297 static const struct udevice_id sti_reset_ids[] = {
299 .compatible = "st,stih407-picophyreset",
300 .data = (ulong)&stih407_picophyreset_controller,
303 .compatible = "st,stih407-powerdown",
304 .data = (ulong)&stih407_powerdown_controller,
307 .compatible = "st,stih407-softreset",
308 .data = (ulong)&stih407_softreset_controller,
313 U_BOOT_DRIVER(sti_reset) = {
316 .of_match = sti_reset_ids,
317 .probe = sti_reset_probe,
318 .priv_auto_alloc_size = sizeof(struct sti_reset),
319 .ops = &sti_reset_ops,