1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
13 #include <reset-uclass.h>
16 #include <dt-bindings/reset/stih407-resets.h>
17 #include <linux/bitops.h>
19 DECLARE_GLOBAL_DATA_PTR;
22 const struct syscfg_reset_controller_data *data;
26 * Reset channel description for a system configuration register based
29 * @compatible: Compatible string of the syscon containing this
30 * channel's control and ack (status) bits.
31 * @reset_offset: Reset register offset in sysconf bank.
32 * @reset_bit: Bit number in reset register.
33 * @ack_offset: Ack reset register offset in syscon bank.
34 * @ack_bit: Bit number in Ack reset register.
35 * @deassert_cnt: incremented when reset is deasserted, reset can only be
36 * asserted when equal to 0
39 struct syscfg_reset_channel_data {
40 const char *compatible;
49 * Description of a system configuration register based reset controller.
51 * @wait_for_ack: The controller will wait for reset assert and de-assert to
52 * be "ack'd" in a channel's ack field.
53 * @active_low: Are the resets in this controller active low, i.e. clearing
54 * the reset bit puts the hardware into reset.
55 * @nr_channels: The number of reset channels in this controller.
56 * @channels: An array of reset channel descriptions.
58 struct syscfg_reset_controller_data {
62 struct syscfg_reset_channel_data *channels;
65 /* STiH407 Peripheral powerdown definitions. */
66 static const char stih407_core[] = "st,stih407-core-syscfg";
67 static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
68 static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
70 #define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
72 .reset_offset = _rr, \
77 #define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
79 .reset_offset = _rr, \
82 #define STIH407_SRST_CORE(_reg, _bit) \
83 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
85 #define STIH407_SRST_SBC(_reg, _bit) \
86 _SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
88 #define STIH407_SRST_LPM(_reg, _bit) \
89 _SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
91 #define STIH407_PDN_0(_bit) \
92 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
93 #define STIH407_PDN_1(_bit) \
94 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
95 #define STIH407_PDN_ETH(_bit, _stat) \
96 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
98 /* Powerdown requests control 0 */
99 #define SYSCFG_5000 0x0
100 #define SYSSTAT_5500 0x7d0
101 /* Powerdown requests control 1 (High Speed Links) */
102 #define SYSCFG_5001 0x4
103 #define SYSSTAT_5501 0x7d4
105 /* Ethernet powerdown/status/reset */
106 #define SYSCFG_4032 0x80
107 #define SYSSTAT_4520 0x820
108 #define SYSCFG_4002 0x8
110 static struct syscfg_reset_channel_data stih407_powerdowns[] = {
111 [STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
112 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
113 [STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
114 [STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
115 [STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
116 [STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
117 [STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
118 [STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
119 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
120 [STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
123 /* Reset Generator control 0/1 */
124 #define SYSCFG_5128 0x200
125 #define SYSCFG_5131 0x20c
126 #define SYSCFG_5132 0x210
128 #define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
130 static struct syscfg_reset_channel_data stih407_softresets[] = {
131 [STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
132 [STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
133 [STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
134 [STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
135 [STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
136 [STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
137 [STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
138 [STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
139 [STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
140 [STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
141 [STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
142 [STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
143 [STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
144 [STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
145 [STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
146 [STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
147 [STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
148 [STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
149 [STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
150 [STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
151 [STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
152 [STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
153 [STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
154 [STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
155 [STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
156 [STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
157 [STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
158 [STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
159 [STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
160 [STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
161 [STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
162 [STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
163 [STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
166 /* PicoPHY reset/control */
167 #define SYSCFG_5061 0x0f4
169 static struct syscfg_reset_channel_data stih407_picophyresets[] = {
170 [STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
171 [STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
172 [STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
176 syscfg_reset_controller_data stih407_powerdown_controller = {
177 .wait_for_ack = true,
178 .nr_channels = ARRAY_SIZE(stih407_powerdowns),
179 .channels = stih407_powerdowns,
183 syscfg_reset_controller_data stih407_softreset_controller = {
184 .wait_for_ack = false,
186 .nr_channels = ARRAY_SIZE(stih407_softresets),
187 .channels = stih407_softresets,
191 syscfg_reset_controller_data stih407_picophyreset_controller = {
192 .wait_for_ack = false,
193 .nr_channels = ARRAY_SIZE(stih407_picophyresets),
194 .channels = stih407_picophyresets,
197 phys_addr_t sti_reset_get_regmap(const char *compatible)
199 struct udevice *syscon;
200 struct regmap *regmap;
203 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
206 pr_err("unable to find %s node\n", compatible);
210 ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
212 pr_err("%s: uclass_get_device_by_of_offset failed: %d\n",
217 regmap = syscon_get_regmap(syscon);
219 pr_err("unable to get regmap for %s\n", syscon->name);
223 return regmap->ranges[0].start;
226 static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
228 struct udevice *dev = reset_ctl->dev;
229 struct syscfg_reset_controller_data *reset_desc =
230 (struct syscfg_reset_controller_data *)(dev->driver_data);
231 struct syscfg_reset_channel_data *ch;
233 u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
236 /* check if reset id is inside available range */
237 if (reset_ctl->id >= reset_desc->nr_channels)
240 /* get reset sysconf register base address */
241 base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
243 ch = &reset_desc->channels[reset_ctl->id];
245 /* check the deassert counter to assert reset when it reaches 0 */
248 if (ch->deassert_cnt > 1)
251 if (ch->deassert_cnt > 0) {
253 if (ch->deassert_cnt > 0)
256 pr_err("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n",
257 reset_ctl, reset_ctl->dev, reset_ctl->id);
260 reg = (void __iomem *)base + ch->reset_offset;
263 generic_set_bit(ch->reset_bit, reg);
265 generic_clear_bit(ch->reset_bit, reg);
267 if (!reset_desc->wait_for_ack)
270 reg = (void __iomem *)base + ch->ack_offset;
271 if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val,
273 pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
274 reset_ctl, reset_ctl->dev, reset_ctl->id);
282 static int sti_reset_request(struct reset_ctl *reset_ctl)
287 static int sti_reset_free(struct reset_ctl *reset_ctl)
292 static int sti_reset_assert(struct reset_ctl *reset_ctl)
294 return sti_reset_program_hw(reset_ctl, true);
297 static int sti_reset_deassert(struct reset_ctl *reset_ctl)
299 return sti_reset_program_hw(reset_ctl, false);
302 struct reset_ops sti_reset_ops = {
303 .request = sti_reset_request,
304 .rfree = sti_reset_free,
305 .rst_assert = sti_reset_assert,
306 .rst_deassert = sti_reset_deassert,
309 static int sti_reset_probe(struct udevice *dev)
311 struct sti_reset *priv = dev_get_priv(dev);
313 priv->data = (void *)dev_get_driver_data(dev);
318 static const struct udevice_id sti_reset_ids[] = {
320 .compatible = "st,stih407-picophyreset",
321 .data = (ulong)&stih407_picophyreset_controller,
324 .compatible = "st,stih407-powerdown",
325 .data = (ulong)&stih407_powerdown_controller,
328 .compatible = "st,stih407-softreset",
329 .data = (ulong)&stih407_softreset_controller,
334 U_BOOT_DRIVER(sti_reset) = {
337 .of_match = sti_reset_ids,
338 .probe = sti_reset_probe,
339 .priv_auto_alloc_size = sizeof(struct sti_reset),
340 .ops = &sti_reset_ops,