1 // SPDX-License-Identifier: GPL-2.0+
3 * Socfpga Reset Controller Driver
5 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
8 * Allwinner SoCs Reset Controller driver
10 * Copyright 2013 Maxime Ripard
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 #include <dm/of_access.h>
19 #include <reset-uclass.h>
20 #include <linux/bitops.h>
22 #include <linux/sizes.h>
24 #define BANK_INCREMENT 4
27 struct socfpga_reset_data {
28 void __iomem *modrst_base;
32 * For compatibility with Kernels that don't support peripheral reset, this
33 * driver can keep the old behaviour of not asserting peripheral reset before
34 * starting the OS and deasserting all peripheral resets (enabling all
37 * For that, the reset driver checks the environment variable
38 * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
39 * reset again once taken out of reset and all peripherals in 'permodrst' are
40 * taken out of reset before booting into the OS.
41 * Note that this should be required for gen5 systems only that are running
42 * Linux kernels without proper peripheral reset support for all drivers used.
44 static bool socfpga_reset_keep_enabled(void)
46 #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
50 env_str = env_get("socfpga_legacy_reset_compat");
52 val = simple_strtol(env_str, NULL, 0);
61 static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
63 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
64 int id = reset_ctl->id;
65 int reg_width = sizeof(u32);
66 int bank = id / (reg_width * BITS_PER_BYTE);
67 int offset = id % (reg_width * BITS_PER_BYTE);
69 setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
73 static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
75 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
76 int id = reset_ctl->id;
77 int reg_width = sizeof(u32);
78 int bank = id / (reg_width * BITS_PER_BYTE);
79 int offset = id % (reg_width * BITS_PER_BYTE);
81 clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
85 static int socfpga_reset_request(struct reset_ctl *reset_ctl)
87 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
88 reset_ctl, reset_ctl->dev, reset_ctl->id);
93 static int socfpga_reset_free(struct reset_ctl *reset_ctl)
95 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
96 reset_ctl->dev, reset_ctl->id);
101 static const struct reset_ops socfpga_reset_ops = {
102 .request = socfpga_reset_request,
103 .free = socfpga_reset_free,
104 .rst_assert = socfpga_reset_assert,
105 .rst_deassert = socfpga_reset_deassert,
108 static int socfpga_reset_probe(struct udevice *dev)
110 struct socfpga_reset_data *data = dev_get_priv(dev);
112 void __iomem *membase;
114 membase = devfdt_get_addr_ptr(dev);
116 modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
117 data->modrst_base = membase + modrst_offset;
122 static int socfpga_reset_remove(struct udevice *dev)
124 struct socfpga_reset_data *data = dev_get_priv(dev);
126 if (socfpga_reset_keep_enabled()) {
127 puts("Deasserting all peripheral resets\n");
128 writel(0, data->modrst_base + 4);
134 static int socfpga_reset_bind(struct udevice *dev)
137 struct udevice *sys_child;
140 * The sysreset driver does not have a device node, so bind it here.
141 * Bind it to the node, too, so that it can get its base address.
143 ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
144 dev->node, &sys_child);
146 debug("Warning: No sysreset driver: ret=%d\n", ret);
151 static const struct udevice_id socfpga_reset_match[] = {
152 { .compatible = "altr,rst-mgr" },
156 U_BOOT_DRIVER(socfpga_reset) = {
157 .name = "socfpga-reset",
159 .of_match = socfpga_reset_match,
160 .bind = socfpga_reset_bind,
161 .probe = socfpga_reset_probe,
162 .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
163 .ops = &socfpga_reset_ops,
164 .remove = socfpga_reset_remove,
165 .flags = DM_FLAG_OS_PREPARE,