1 // SPDX-License-Identifier: GPL-2.0+
3 * Socfpga Reset Controller Driver
5 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
8 * Allwinner SoCs Reset Controller driver
10 * Copyright 2013 Maxime Ripard
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
18 #include <dm/of_access.h>
20 #include <reset-uclass.h>
21 #include <linux/bitops.h>
23 #include <linux/sizes.h>
25 #define BANK_INCREMENT 4
28 struct socfpga_reset_data {
29 void __iomem *modrst_base;
33 * For compatibility with Kernels that don't support peripheral reset, this
34 * driver can keep the old behaviour of not asserting peripheral reset before
35 * starting the OS and deasserting all peripheral resets (enabling all
38 * For that, the reset driver checks the environment variable
39 * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
40 * reset again once taken out of reset and all peripherals in 'permodrst' are
41 * taken out of reset before booting into the OS.
42 * Note that this should be required for gen5 systems only that are running
43 * Linux kernels without proper peripheral reset support for all drivers used.
45 static bool socfpga_reset_keep_enabled(void)
47 #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
51 env_str = env_get("socfpga_legacy_reset_compat");
53 val = simple_strtol(env_str, NULL, 0);
62 static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
64 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
65 int id = reset_ctl->id;
66 int reg_width = sizeof(u32);
67 int bank = id / (reg_width * BITS_PER_BYTE);
68 int offset = id % (reg_width * BITS_PER_BYTE);
70 setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
74 static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
76 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
77 int id = reset_ctl->id;
78 int reg_width = sizeof(u32);
79 int bank = id / (reg_width * BITS_PER_BYTE);
80 int offset = id % (reg_width * BITS_PER_BYTE);
82 clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
86 static int socfpga_reset_request(struct reset_ctl *reset_ctl)
88 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
89 reset_ctl, reset_ctl->dev, reset_ctl->id);
94 static int socfpga_reset_free(struct reset_ctl *reset_ctl)
96 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
97 reset_ctl->dev, reset_ctl->id);
102 static const struct reset_ops socfpga_reset_ops = {
103 .request = socfpga_reset_request,
104 .free = socfpga_reset_free,
105 .rst_assert = socfpga_reset_assert,
106 .rst_deassert = socfpga_reset_deassert,
109 static int socfpga_reset_probe(struct udevice *dev)
111 struct socfpga_reset_data *data = dev_get_priv(dev);
113 void __iomem *membase;
115 membase = devfdt_get_addr_ptr(dev);
117 modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
118 data->modrst_base = membase + modrst_offset;
123 static int socfpga_reset_remove(struct udevice *dev)
125 struct socfpga_reset_data *data = dev_get_priv(dev);
127 if (socfpga_reset_keep_enabled()) {
128 puts("Deasserting all peripheral resets\n");
129 writel(0, data->modrst_base + 4);
135 static int socfpga_reset_bind(struct udevice *dev)
138 struct udevice *sys_child;
141 * The sysreset driver does not have a device node, so bind it here.
142 * Bind it to the node, too, so that it can get its base address.
144 ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
145 dev->node, &sys_child);
147 debug("Warning: No sysreset driver: ret=%d\n", ret);
152 static const struct udevice_id socfpga_reset_match[] = {
153 { .compatible = "altr,rst-mgr" },
157 U_BOOT_DRIVER(socfpga_reset) = {
158 .name = "socfpga-reset",
160 .of_match = socfpga_reset_match,
161 .bind = socfpga_reset_bind,
162 .probe = socfpga_reset_probe,
163 .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
164 .ops = &socfpga_reset_ops,
165 .remove = socfpga_reset_remove,
166 .flags = DM_FLAG_OS_PREPARE,