1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 #include "stm32mp1_ddr.h"
15 static const char *const clkname[] = {
20 "ddrphyc" /* LAST clock => used for get_rate() */
23 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
25 unsigned long ddrphy_clk;
26 unsigned long ddr_clk;
31 for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
32 ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
35 ret = clk_enable(&clk);
38 printf("error for %s : %d\n", clkname[idx], ret);
44 ddrphy_clk = clk_get_rate(&priv->clk);
46 debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
47 mem_speed, (u32)(ddrphy_clk / 1000));
48 /* max 10% frequency delta */
49 ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
50 if (ddr_clk > (mem_speed * 100)) {
51 pr_err("DDR expected freq %d kHz, current is %d kHz\n",
52 mem_speed, (u32)(ddrphy_clk / 1000));
59 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
61 struct ddr_info *priv = dev_get_priv(dev);
65 struct stm32mp1_ddr_config config;
69 offsetof(struct stm32mp1_ddr_config, y),\
70 sizeof(config.y) / sizeof(u32)}
72 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x)
73 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x)
76 const char *name; /* name in DT */
77 const u32 offset; /* offset in config struct */
78 const u32 size; /* size of parameters */
89 config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0);
90 config.info.size = dev_read_u32_default(dev, "st,mem-size", 0);
91 config.info.name = dev_read_string(dev, "st,mem-name");
92 if (!config.info.name) {
93 debug("%s: no st,mem-name\n", __func__);
96 printf("RAM: %s\n", config.info.name);
98 for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
99 ret = dev_read_u32_array(dev, param[idx].name,
100 (void *)((u32)&config +
103 debug("%s: %s[0x%x] = %d\n", __func__,
104 param[idx].name, param[idx].size, ret);
106 pr_err("%s: Cannot read %s, error=%d\n",
107 __func__, param[idx].name, ret);
112 ret = clk_get_by_name(dev, "axidcg", &axidcg);
114 debug("%s: Cannot found axidcg\n", __func__);
117 clk_disable(&axidcg); /* disable clock gating during init */
119 stm32mp1_ddr_init(priv, &config);
121 clk_enable(&axidcg); /* enable clock gating */
124 debug("%s : get_ram_size(%x, %x)\n", __func__,
125 (u32)priv->info.base, (u32)STM32_DDR_SIZE);
127 priv->info.size = get_ram_size((long *)priv->info.base,
130 debug("%s : %x\n", __func__, (u32)priv->info.size);
132 /* check memory access for all memory */
133 if (config.info.size != priv->info.size) {
134 printf("DDR invalid size : 0x%x, expected 0x%x\n",
135 priv->info.size, config.info.size);
141 static int stm32mp1_ddr_probe(struct udevice *dev)
143 struct ddr_info *priv = dev_get_priv(dev);
147 debug("STM32MP1 DDR probe\n");
150 ret = regmap_init_mem(dev_ofnode(dev), &map);
154 priv->ctl = regmap_get_range(map, 0);
155 priv->phy = regmap_get_range(map, 1);
157 priv->rcc = STM32_RCC_BASE;
159 priv->info.base = STM32_DDR_BASE;
161 #if !defined(CONFIG_STM32MP1_TRUSTED) && \
162 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
164 return stm32mp1_ddr_setup(dev);
166 priv->info.size = dev_read_u32_default(dev, "st,mem-size", 0);
171 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
173 struct ddr_info *priv = dev_get_priv(dev);
180 static struct ram_ops stm32mp1_ddr_ops = {
181 .get_info = stm32mp1_ddr_get_info,
184 static const struct udevice_id stm32mp1_ddr_ids[] = {
185 { .compatible = "st,stm32mp1-ddr" },
189 U_BOOT_DRIVER(ddr_stm32mp1) = {
190 .name = "stm32mp1_ddr",
192 .of_match = stm32mp1_ddr_ids,
193 .ops = &stm32mp1_ddr_ops,
194 .probe = stm32mp1_ddr_probe,
195 .priv_auto_alloc_size = sizeof(struct ddr_info),