drivers/ram/stm32mp1/stm32mp1_ram.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <log.h>
  11 #include <ram.h>
  12 #include <regmap.h>
  13 #include <syscon.h>
  14 #include <asm/io.h>
  15 #include "stm32mp1_ddr.h"
  16
  17 static const char *const clkname[] = {
  18         "ddrc1",
  19         "ddrc2",
  20         "ddrcapb",
  21         "ddrphycapb",
  22         "ddrphyc" /* LAST clock => used for get_rate() */
  23 };
  24
  25 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
  26 {
  27         unsigned long ddrphy_clk;
  28         unsigned long ddr_clk;
  29         struct clk clk;
  30         int ret;
  31         unsigned int idx;
  32
  33         for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
  34                 ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
  35
  36                 if (!ret)
  37                         ret = clk_enable(&clk);
  38
  39                 if (ret) {
  40                         printf("error for %s : %d\n", clkname[idx], ret);
  41                         return ret;
  42                 }
  43         }
  44
  45         priv->clk = clk;
  46         ddrphy_clk = clk_get_rate(&priv->clk);
  47
  48         debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
  49               mem_speed, (u32)(ddrphy_clk / 1000));
  50         /* max 10% frequency delta */
  51         ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
  52         if (ddr_clk > (mem_speed * 100)) {
  53                 pr_err("DDR expected freq %d kHz, current is %d kHz\n",
  54                        mem_speed, (u32)(ddrphy_clk / 1000));
  55                 return -EINVAL;
  56         }
  57
  58         return 0;
  59 }
  60
  61 __weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
  62                                                 const char *name)
  63 {
  64         return 0;       /* Always match */
  65 }
  66
  67 static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev)
  68 {
  69         const char *name;
  70         ofnode node;
  71
  72         dev_for_each_subnode(node, dev) {
  73                 name = ofnode_get_property(node, "compatible", NULL);
  74
  75                 if (!board_stm32mp1_ddr_config_name_match(dev, name))
  76                         return node;
  77         }
  78
  79         return dev_ofnode(dev);
  80 }
  81
  82 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
  83 {
  84         struct ddr_info *priv = dev_get_priv(dev);
  85         int ret;
  86         unsigned int idx;
  87         struct clk axidcg;
  88         struct stm32mp1_ddr_config config;
  89         ofnode node = stm32mp1_ddr_get_ofnode(dev);
  90
  91 #define PARAM(x, y, z)                                                  \
  92         {       .name = x,                                              \
  93                 .offset = offsetof(struct stm32mp1_ddr_config, y),      \
  94                 .size = sizeof(config.y) / sizeof(u32),                 \
  95                 .present = z,                                           \
  96         }
  97
  98 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
  99 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
 100 #define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
 101
 102         const struct {
 103                 const char *name; /* name in DT */
 104                 const u32 offset; /* offset in config struct */
 105                 const u32 size;   /* size of parameters */
 106                 bool * const present;  /* presence indication for opt */
 107         } param[] = {
 108                 CTL_PARAM(reg),
 109                 CTL_PARAM(timing),
 110                 CTL_PARAM(map),
 111                 CTL_PARAM(perf),
 112                 PHY_PARAM(reg),
 113                 PHY_PARAM(timing),
 114                 PHY_PARAM_OPT(cal)
 115         };
 116
 117         config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
 118         config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 119         config.info.name = ofnode_read_string(node, "st,mem-name");
 120         if (!config.info.name) {
 121                 debug("%s: no st,mem-name\n", __func__);
 122                 return -EINVAL;
 123         }
 124         printf("RAM: %s\n", config.info.name);
 125
 126         for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
 127                 ret = ofnode_read_u32_array(node, param[idx].name,
 128                                          (void *)((u32)&config +
 129                                                   param[idx].offset),
 130                                          param[idx].size);
 131                 debug("%s: %s[0x%x] = %d\n", __func__,
 132                       param[idx].name, param[idx].size, ret);
 133                 if (ret &&
 134                     (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
 135                         pr_err("%s: Cannot read %s, error=%d\n",
 136                                __func__, param[idx].name, ret);
 137                         return -EINVAL;
 138                 }
 139                 if (param[idx].present) {
 140                         /* save presence of optional parameters */
 141                         *param[idx].present = true;
 142                         if (ret == -FDT_ERR_NOTFOUND) {
 143                                 *param[idx].present = false;
 144 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 145                                 /* reset values if used later */
 146                                 memset((void *)((u32)&config +
 147                                                 param[idx].offset),
 148                                         0, param[idx].size * sizeof(u32));
 149 #endif
 150                         }
 151                 }
 152         }
 153
 154         ret = clk_get_by_name(dev, "axidcg", &axidcg);
 155         if (ret) {
 156                 debug("%s: Cannot found axidcg\n", __func__);
 157                 return -EINVAL;
 158         }
 159         clk_disable(&axidcg); /* disable clock gating during init */
 160
 161         stm32mp1_ddr_init(priv, &config);
 162
 163         clk_enable(&axidcg); /* enable clock gating */
 164
 165         /* check size */
 166         debug("%s : get_ram_size(%x, %x)\n", __func__,
 167               (u32)priv->info.base, (u32)STM32_DDR_SIZE);
 168
 169         priv->info.size = get_ram_size((long *)priv->info.base,
 170                                        STM32_DDR_SIZE);
 171
 172         debug("%s : %x\n", __func__, (u32)priv->info.size);
 173
 174         /* check memory access for all memory */
 175         if (config.info.size != priv->info.size) {
 176                 printf("DDR invalid size : 0x%x, expected 0x%x\n",
 177                        priv->info.size, config.info.size);
 178                 return -EINVAL;
 179         }
 180         return 0;
 181 }
 182
 183 static int stm32mp1_ddr_probe(struct udevice *dev)
 184 {
 185         struct ddr_info *priv = dev_get_priv(dev);
 186         struct regmap *map;
 187         int ret;
 188
 189         debug("STM32MP1 DDR probe\n");
 190         priv->dev = dev;
 191
 192         ret = regmap_init_mem(dev_ofnode(dev), &map);
 193         if (ret)
 194                 return ret;
 195
 196         priv->ctl = regmap_get_range(map, 0);
 197         priv->phy = regmap_get_range(map, 1);
 198
 199         priv->rcc = STM32_RCC_BASE;
 200
 201         priv->info.base = STM32_DDR_BASE;
 202
 203 #if !defined(CONFIG_TFABOOT) && \
 204         (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 205         priv->info.size = 0;
 206         return stm32mp1_ddr_setup(dev);
 207 #else
 208         ofnode node = stm32mp1_ddr_get_ofnode(dev);
 209         priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 210         return 0;
 211 #endif
 212 }
 213
 214 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
 215 {
 216         struct ddr_info *priv = dev_get_priv(dev);
 217
 218         *info = priv->info;
 219
 220         return 0;
 221 }
 222
 223 static struct ram_ops stm32mp1_ddr_ops = {
 224         .get_info = stm32mp1_ddr_get_info,
 225 };
 226
 227 static const struct udevice_id stm32mp1_ddr_ids[] = {
 228         { .compatible = "st,stm32mp1-ddr" },
 229         { }
 230 };
 231
 232 U_BOOT_DRIVER(ddr_stm32mp1) = {
 233         .name = "stm32mp1_ddr",
 234         .id = UCLASS_RAM,
 235         .of_match = stm32mp1_ddr_ids,
 236         .ops = &stm32mp1_ddr_ops,
 237         .probe = stm32mp1_ddr_probe,
 238         .priv_auto_alloc_size = sizeof(struct ddr_info),
 239 };