drivers/ram/stm32mp1/stm32mp1_ram.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #include <common.h>
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <init.h>
  10 #include <ram.h>
  11 #include <regmap.h>
  12 #include <syscon.h>
  13 #include <asm/io.h>
  14 #include "stm32mp1_ddr.h"
  15
  16 static const char *const clkname[] = {
  17         "ddrc1",
  18         "ddrc2",
  19         "ddrcapb",
  20         "ddrphycapb",
  21         "ddrphyc" /* LAST clock => used for get_rate() */
  22 };
  23
  24 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
  25 {
  26         unsigned long ddrphy_clk;
  27         unsigned long ddr_clk;
  28         struct clk clk;
  29         int ret;
  30         unsigned int idx;
  31
  32         for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
  33                 ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
  34
  35                 if (!ret)
  36                         ret = clk_enable(&clk);
  37
  38                 if (ret) {
  39                         printf("error for %s : %d\n", clkname[idx], ret);
  40                         return ret;
  41                 }
  42         }
  43
  44         priv->clk = clk;
  45         ddrphy_clk = clk_get_rate(&priv->clk);
  46
  47         debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
  48               mem_speed, (u32)(ddrphy_clk / 1000));
  49         /* max 10% frequency delta */
  50         ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
  51         if (ddr_clk > (mem_speed * 100)) {
  52                 pr_err("DDR expected freq %d kHz, current is %d kHz\n",
  53                        mem_speed, (u32)(ddrphy_clk / 1000));
  54                 return -EINVAL;
  55         }
  56
  57         return 0;
  58 }
  59
  60 __weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
  61                                                 const char *name)
  62 {
  63         return 0;       /* Always match */
  64 }
  65
  66 static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev)
  67 {
  68         const char *name;
  69         ofnode node;
  70
  71         dev_for_each_subnode(node, dev) {
  72                 name = ofnode_get_property(node, "compatible", NULL);
  73
  74                 if (!board_stm32mp1_ddr_config_name_match(dev, name))
  75                         return node;
  76         }
  77
  78         return dev_ofnode(dev);
  79 }
  80
  81 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
  82 {
  83         struct ddr_info *priv = dev_get_priv(dev);
  84         int ret;
  85         unsigned int idx;
  86         struct clk axidcg;
  87         struct stm32mp1_ddr_config config;
  88         ofnode node = stm32mp1_ddr_get_ofnode(dev);
  89
  90 #define PARAM(x, y, z)                                                  \
  91         {       .name = x,                                              \
  92                 .offset = offsetof(struct stm32mp1_ddr_config, y),      \
  93                 .size = sizeof(config.y) / sizeof(u32),                 \
  94                 .present = z,                                           \
  95         }
  96
  97 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
  98 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
  99 #define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
 100
 101         const struct {
 102                 const char *name; /* name in DT */
 103                 const u32 offset; /* offset in config struct */
 104                 const u32 size;   /* size of parameters */
 105                 bool * const present;  /* presence indication for opt */
 106         } param[] = {
 107                 CTL_PARAM(reg),
 108                 CTL_PARAM(timing),
 109                 CTL_PARAM(map),
 110                 CTL_PARAM(perf),
 111                 PHY_PARAM(reg),
 112                 PHY_PARAM(timing),
 113                 PHY_PARAM_OPT(cal)
 114         };
 115
 116         config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
 117         config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 118         config.info.name = ofnode_read_string(node, "st,mem-name");
 119         if (!config.info.name) {
 120                 debug("%s: no st,mem-name\n", __func__);
 121                 return -EINVAL;
 122         }
 123         printf("RAM: %s\n", config.info.name);
 124
 125         for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
 126                 ret = ofnode_read_u32_array(node, param[idx].name,
 127                                          (void *)((u32)&config +
 128                                                   param[idx].offset),
 129                                          param[idx].size);
 130                 debug("%s: %s[0x%x] = %d\n", __func__,
 131                       param[idx].name, param[idx].size, ret);
 132                 if (ret &&
 133                     (ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
 134                         pr_err("%s: Cannot read %s, error=%d\n",
 135                                __func__, param[idx].name, ret);
 136                         return -EINVAL;
 137                 }
 138                 if (param[idx].present) {
 139                         /* save presence of optional parameters */
 140                         *param[idx].present = true;
 141                         if (ret == -FDT_ERR_NOTFOUND) {
 142                                 *param[idx].present = false;
 143 #ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
 144                                 /* reset values if used later */
 145                                 memset((void *)((u32)&config +
 146                                                 param[idx].offset),
 147                                         0, param[idx].size * sizeof(u32));
 148 #endif
 149                         }
 150                 }
 151         }
 152
 153         ret = clk_get_by_name(dev, "axidcg", &axidcg);
 154         if (ret) {
 155                 debug("%s: Cannot found axidcg\n", __func__);
 156                 return -EINVAL;
 157         }
 158         clk_disable(&axidcg); /* disable clock gating during init */
 159
 160         stm32mp1_ddr_init(priv, &config);
 161
 162         clk_enable(&axidcg); /* enable clock gating */
 163
 164         /* check size */
 165         debug("%s : get_ram_size(%x, %x)\n", __func__,
 166               (u32)priv->info.base, (u32)STM32_DDR_SIZE);
 167
 168         priv->info.size = get_ram_size((long *)priv->info.base,
 169                                        STM32_DDR_SIZE);
 170
 171         debug("%s : %x\n", __func__, (u32)priv->info.size);
 172
 173         /* check memory access for all memory */
 174         if (config.info.size != priv->info.size) {
 175                 printf("DDR invalid size : 0x%x, expected 0x%x\n",
 176                        priv->info.size, config.info.size);
 177                 return -EINVAL;
 178         }
 179         return 0;
 180 }
 181
 182 static int stm32mp1_ddr_probe(struct udevice *dev)
 183 {
 184         struct ddr_info *priv = dev_get_priv(dev);
 185         struct regmap *map;
 186         int ret;
 187
 188         debug("STM32MP1 DDR probe\n");
 189         priv->dev = dev;
 190
 191         ret = regmap_init_mem(dev_ofnode(dev), &map);
 192         if (ret)
 193                 return ret;
 194
 195         priv->ctl = regmap_get_range(map, 0);
 196         priv->phy = regmap_get_range(map, 1);
 197
 198         priv->rcc = STM32_RCC_BASE;
 199
 200         priv->info.base = STM32_DDR_BASE;
 201
 202 #if !defined(CONFIG_TFABOOT) && \
 203         (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
 204         priv->info.size = 0;
 205         return stm32mp1_ddr_setup(dev);
 206 #else
 207         ofnode node = stm32mp1_ddr_get_ofnode(dev);
 208         priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 209         return 0;
 210 #endif
 211 }
 212
 213 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
 214 {
 215         struct ddr_info *priv = dev_get_priv(dev);
 216
 217         *info = priv->info;
 218
 219         return 0;
 220 }
 221
 222 static struct ram_ops stm32mp1_ddr_ops = {
 223         .get_info = stm32mp1_ddr_get_info,
 224 };
 225
 226 static const struct udevice_id stm32mp1_ddr_ids[] = {
 227         { .compatible = "st,stm32mp1-ddr" },
 228         { }
 229 };
 230
 231 U_BOOT_DRIVER(ddr_stm32mp1) = {
 232         .name = "stm32mp1_ddr",
 233         .id = UCLASS_RAM,
 234         .of_match = stm32mp1_ddr_ids,
 235         .ops = &stm32mp1_ddr_ops,
 236         .probe = stm32mp1_ddr_probe,
 237         .priv_auto_alloc_size = sizeof(struct ddr_info),
 238 };