1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
4 * Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
14 #include <dm/device_compat.h>
15 #include <linux/bitops.h>
16 #include <linux/delay.h>
18 #define MEM_MODE_MASK GENMASK(2, 0)
19 #define SWP_FMC_OFFSET 10
20 #define SWP_FMC_MASK GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
21 #define NOT_FOUND 0xff
23 struct stm32_fmc_regs {
25 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
26 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
27 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
28 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
29 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
30 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
31 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
32 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
36 u32 pcr; /* NAND Flash control register */
37 u32 sr; /* FIFO status and interrupt register */
38 u32 pmem; /* Common memory space timing register */
39 u32 patt; /* Attribute memory space timing registers */
41 u32 eccr; /* ECC result registers */
45 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
47 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
49 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
51 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
55 u32 sdcr1; /* SDRAM Control register 1 */
56 u32 sdcr2; /* SDRAM Control register 2 */
57 u32 sdtr1; /* SDRAM Timing register 1 */
58 u32 sdtr2; /* SDRAM Timing register 2 */
59 u32 sdcmr; /* SDRAM Mode register */
60 u32 sdrtr; /* SDRAM Refresh timing register */
61 u32 sdsr; /* SDRAM Status register */
65 * NOR/PSRAM Control register BCR1
66 * FMC controller Enable, only availabe for H7
68 #define FMC_BCR1_FMCEN BIT(31)
70 /* Control register SDCR */
71 #define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
72 #define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
73 #define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
74 #define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
75 #define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
76 #define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
77 #define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
78 #define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
79 #define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
81 /* Timings register SDTR */
82 #define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
83 #define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
84 #define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
85 #define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
86 #define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
87 #define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
88 #define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
90 #define FMC_SDCMR_NRFS_SHIFT 5
92 #define FMC_SDCMR_MODE_NORMAL 0
93 #define FMC_SDCMR_MODE_START_CLOCK 1
94 #define FMC_SDCMR_MODE_PRECHARGE 2
95 #define FMC_SDCMR_MODE_AUTOREFRESH 3
96 #define FMC_SDCMR_MODE_WRITE_MODE 4
97 #define FMC_SDCMR_MODE_SELFREFRESH 5
98 #define FMC_SDCMR_MODE_POWERDOWN 6
100 #define FMC_SDCMR_BANK_1 BIT(4)
101 #define FMC_SDCMR_BANK_2 BIT(3)
103 #define FMC_SDCMR_MODE_REGISTER_SHIFT 9
105 #define FMC_SDSR_BUSY BIT(5)
107 #define FMC_BUSY_WAIT(regs) do { \
108 __asm__ __volatile__ ("dsb" : : : "memory"); \
109 while (regs->sdsr & FMC_SDSR_BUSY) \
113 struct stm32_sdram_control {
124 struct stm32_sdram_timing {
133 enum stm32_fmc_bank {
139 enum stm32_fmc_family {
145 struct stm32_sdram_control *sdram_control;
146 struct stm32_sdram_timing *sdram_timing;
148 enum stm32_fmc_bank target_bank;
151 struct stm32_sdram_params {
152 struct stm32_fmc_regs *base;
154 struct bank_params bank_params[MAX_SDRAM_BANK];
155 enum stm32_fmc_family family;
158 #define SDRAM_MODE_BL_SHIFT 0
159 #define SDRAM_MODE_CAS_SHIFT 4
160 #define SDRAM_MODE_BL 0
162 int stm32_sdram_init(struct udevice *dev)
164 struct stm32_sdram_params *params = dev_get_platdata(dev);
165 struct stm32_sdram_control *control;
166 struct stm32_sdram_timing *timing;
167 struct stm32_fmc_regs *regs = params->base;
168 enum stm32_fmc_bank target_bank;
169 u32 ctb; /* SDCMR register: Command Target Bank */
173 /* disable the FMC controller */
174 if (params->family == STM32H7_FMC)
175 clrbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
177 for (i = 0; i < params->no_sdram_banks; i++) {
178 control = params->bank_params[i].sdram_control;
179 timing = params->bank_params[i].sdram_timing;
180 target_bank = params->bank_params[i].target_bank;
181 ref_count = params->bank_params[i].sdram_ref_count;
183 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
184 | control->cas_latency << FMC_SDCR_CAS_SHIFT
185 | control->no_banks << FMC_SDCR_NB_SHIFT
186 | control->memory_width << FMC_SDCR_MWID_SHIFT
187 | control->no_rows << FMC_SDCR_NR_SHIFT
188 | control->no_columns << FMC_SDCR_NC_SHIFT
189 | control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
190 | control->rd_burst << FMC_SDCR_RBURST_SHIFT,
193 if (target_bank == SDRAM_BANK2)
194 writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
195 | control->no_banks << FMC_SDCR_NB_SHIFT
196 | control->memory_width << FMC_SDCR_MWID_SHIFT
197 | control->no_rows << FMC_SDCR_NR_SHIFT
198 | control->no_columns << FMC_SDCR_NC_SHIFT,
201 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
202 | timing->trp << FMC_SDTR_TRP_SHIFT
203 | timing->twr << FMC_SDTR_TWR_SHIFT
204 | timing->trc << FMC_SDTR_TRC_SHIFT
205 | timing->tras << FMC_SDTR_TRAS_SHIFT
206 | timing->txsr << FMC_SDTR_TXSR_SHIFT
207 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
210 if (target_bank == SDRAM_BANK2)
211 writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
212 | timing->trp << FMC_SDTR_TRP_SHIFT
213 | timing->twr << FMC_SDTR_TWR_SHIFT
214 | timing->trc << FMC_SDTR_TRC_SHIFT
215 | timing->tras << FMC_SDTR_TRAS_SHIFT
216 | timing->txsr << FMC_SDTR_TXSR_SHIFT
217 | timing->tmrd << FMC_SDTR_TMRD_SHIFT,
220 if (target_bank == SDRAM_BANK1)
221 ctb = FMC_SDCMR_BANK_1;
223 ctb = FMC_SDCMR_BANK_2;
225 writel(ctb | FMC_SDCMR_MODE_START_CLOCK, ®s->sdcmr);
226 udelay(200); /* 200 us delay, page 10, "Power-Up" */
229 writel(ctb | FMC_SDCMR_MODE_PRECHARGE, ®s->sdcmr);
233 writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
238 writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
239 | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
240 << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
245 writel(ctb | FMC_SDCMR_MODE_NORMAL, ®s->sdcmr);
249 writel(ref_count << 1, ®s->sdrtr);
252 /* enable the FMC controller */
253 if (params->family == STM32H7_FMC)
254 setbits_le32(®s->bcr1, FMC_BCR1_FMCEN);
259 static int stm32_fmc_ofdata_to_platdata(struct udevice *dev)
261 struct stm32_sdram_params *params = dev_get_platdata(dev);
262 struct bank_params *bank_params;
263 struct ofnode_phandle_args args;
272 ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
275 dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret);
277 syscfg_base = (u32 *)ofnode_get_addr(args.node);
279 mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
280 if (mem_remap != NOT_FOUND) {
281 /* set memory mapping selection */
282 clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
284 dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__);
287 swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
288 if (swp_fmc != NOT_FOUND) {
289 /* set fmc swapping selection */
290 clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
292 dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__);
295 dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
298 dev_for_each_subnode(bank_node, dev) {
299 /* extract the bank index from DT */
300 bank_name = (char *)ofnode_get_name(bank_node);
301 strsep(&bank_name, "@");
303 pr_err("missing sdram bank index");
307 bank_params = ¶ms->bank_params[bank];
308 strict_strtoul(bank_name, 10,
309 (long unsigned int *)&bank_params->target_bank);
311 if (bank_params->target_bank >= MAX_SDRAM_BANK) {
312 pr_err("Found bank %d , but only bank 0 and 1 are supported",
313 bank_params->target_bank);
317 debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
319 params->bank_params[bank].sdram_control =
320 (struct stm32_sdram_control *)
321 ofnode_read_u8_array_ptr(bank_node,
323 sizeof(struct stm32_sdram_control));
325 if (!params->bank_params[bank].sdram_control) {
326 pr_err("st,sdram-control not found for %s",
327 ofnode_get_name(bank_node));
332 params->bank_params[bank].sdram_timing =
333 (struct stm32_sdram_timing *)
334 ofnode_read_u8_array_ptr(bank_node,
336 sizeof(struct stm32_sdram_timing));
338 if (!params->bank_params[bank].sdram_timing) {
339 pr_err("st,sdram-timing not found for %s",
340 ofnode_get_name(bank_node));
345 bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
346 "st,sdram-refcount", 8196);
350 params->no_sdram_banks = bank;
351 debug("%s, no of banks = %d\n", __func__, params->no_sdram_banks);
356 static int stm32_fmc_probe(struct udevice *dev)
358 struct stm32_sdram_params *params = dev_get_platdata(dev);
362 addr = dev_read_addr(dev);
363 if (addr == FDT_ADDR_T_NONE)
366 params->base = (struct stm32_fmc_regs *)addr;
367 params->family = dev_get_driver_data(dev);
372 ret = clk_get_by_index(dev, 0, &clk);
376 ret = clk_enable(&clk);
379 dev_err(dev, "failed to enable clock\n");
383 ret = stm32_sdram_init(dev);
390 static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
395 static struct ram_ops stm32_fmc_ops = {
396 .get_info = stm32_fmc_get_info,
399 static const struct udevice_id stm32_fmc_ids[] = {
400 { .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
401 { .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
405 U_BOOT_DRIVER(stm32_fmc) = {
408 .of_match = stm32_fmc_ids,
409 .ops = &stm32_fmc_ops,
410 .ofdata_to_platdata = stm32_fmc_ofdata_to_platdata,
411 .probe = stm32_fmc_probe,
412 .platdata_auto_alloc_size = sizeof(struct stm32_sdram_params),