drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/pmu_rk3399.h>
  20 #include <asm/arch-rockchip/hardware.h>
  21 #include <asm/arch-rockchip/sdram.h>
  22 #include <asm/arch-rockchip/sdram_rk3399.h>
  23 #include <linux/err.h>
  24 #include <time.h>
  25
  26 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  27 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  28 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  29
  30 #define PHY_DRV_ODT_HI_Z        0x0
  31 #define PHY_DRV_ODT_240         0x1
  32 #define PHY_DRV_ODT_120         0x8
  33 #define PHY_DRV_ODT_80          0x9
  34 #define PHY_DRV_ODT_60          0xc
  35 #define PHY_DRV_ODT_48          0xd
  36 #define PHY_DRV_ODT_40          0xe
  37 #define PHY_DRV_ODT_34_3        0xf
  38
  39 #define PHY_BOOSTP_EN           0x1
  40 #define PHY_BOOSTN_EN           0x1
  41 #define PHY_SLEWP_EN            0x1
  42 #define PHY_SLEWN_EN            0x1
  43 #define PHY_RX_CM_INPUT         0x1
  44 #define CS0_MR22_VAL            0
  45 #define CS1_MR22_VAL            3
  46
  47 #define CRU_SFTRST_DDR_CTRL(ch, n)      ((0x1 << (8 + 16 + (ch) * 4)) | \
  48                                         ((n) << (8 + (ch) * 4)))
  49 #define CRU_SFTRST_DDR_PHY(ch, n)       ((0x1 << (9 + 16 + (ch) * 4)) | \
  50                                         ((n) << (9 + (ch) * 4)))
  51 struct chan_info {
  52         struct rk3399_ddr_pctl_regs *pctl;
  53         struct rk3399_ddr_pi_regs *pi;
  54         struct rk3399_ddr_publ_regs *publ;
  55         struct msch_regs *msch;
  56 };
  57
  58 struct dram_info {
  59 #if defined(CONFIG_TPL_BUILD) || \
  60         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  61         u32 pwrup_srefresh_exit[2];
  62         struct chan_info chan[2];
  63         struct clk ddr_clk;
  64         struct rk3399_cru *cru;
  65         struct rk3399_grf_regs *grf;
  66         struct rk3399_pmu_regs *pmu;
  67         struct rk3399_pmucru *pmucru;
  68         struct rk3399_pmusgrf_regs *pmusgrf;
  69         struct rk3399_ddr_cic_regs *cic;
  70         const struct sdram_rk3399_ops *ops;
  71 #endif
  72         struct ram_info info;
  73         struct rk3399_pmugrf_regs *pmugrf;
  74 };
  75
  76 struct sdram_rk3399_ops {
  77         int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank,
  78                                    struct rk3399_sdram_params *sdram);
  79         int (*set_rate_index)(struct dram_info *dram,
  80                               struct rk3399_sdram_params *params);
  81         void (*modify_param)(const struct chan_info *chan,
  82                              struct rk3399_sdram_params *params);
  83         struct rk3399_sdram_params *
  84                 (*get_phy_index_params)(u32 phy_fn,
  85                                         struct rk3399_sdram_params *params);
  86 };
  87
  88 #if defined(CONFIG_TPL_BUILD) || \
  89         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  90
  91 struct rockchip_dmc_plat {
  92 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  93         struct dtd_rockchip_rk3399_dmc dtplat;
  94 #else
  95         struct rk3399_sdram_params sdram_params;
  96 #endif
  97         struct regmap *map;
  98 };
  99
 100 struct io_setting {
 101         u32 mhz;
 102         u32 mr5;
 103         /* dram side */
 104         u32 dq_odt;
 105         u32 ca_odt;
 106         u32 pdds;
 107         u32 dq_vref;
 108         u32 ca_vref;
 109         /* phy side */
 110         u32 rd_odt;
 111         u32 wr_dq_drv;
 112         u32 wr_ca_drv;
 113         u32 wr_ckcs_drv;
 114         u32 rd_odt_en;
 115         u32 rd_vref;
 116 } lpddr4_io_setting[] = {
 117         {
 118                 50 * MHz,
 119                 0,
 120                 /* dram side */
 121                 0,      /* dq_odt; */
 122                 0,      /* ca_odt; */
 123                 6,      /* pdds; */
 124                 0x72,   /* dq_vref; */
 125                 0x72,   /* ca_vref; */
 126                 /* phy side */
 127                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 128                 PHY_DRV_ODT_40, /* wr_dq_drv; */
 129                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 130                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 131                 0,      /* rd_odt_en;*/
 132                 41,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 133         },
 134         {
 135                 600 * MHz,
 136                 0,
 137                 /* dram side */
 138                 1,      /* dq_odt; */
 139                 0,      /* ca_odt; */
 140                 6,      /* pdds; */
 141                 0x72,   /* dq_vref; */
 142                 0x72,   /* ca_vref; */
 143                 /* phy side */
 144                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 145                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 146                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 147                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 148                 0,      /* rd_odt_en; */
 149                 32,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 150         },
 151         {
 152                 933 * MHz,
 153                 0,
 154                 /* dram side */
 155                 1,      /* dq_odt; */
 156                 0,      /* ca_odt; */
 157                 3,      /* pdds; */
 158                 0x72,   /* dq_vref; */
 159                 0x72,   /* ca_vref; */
 160                 /* phy side */
 161                 PHY_DRV_ODT_80, /* rd_odt; */
 162                 PHY_DRV_ODT_40, /* wr_dq_drv; */
 163                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 164                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 165                 1,      /* rd_odt_en; */
 166                 20,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 167         },
 168         {
 169                 1066 * MHz,
 170                 0,
 171                 /* dram side */
 172                 6,      /* dq_odt; */
 173                 0,      /* ca_odt; */
 174                 3,      /* pdds; */
 175                 0x10,   /* dq_vref; */
 176                 0x72,   /* ca_vref; */
 177                 /* phy side */
 178                 PHY_DRV_ODT_80, /* rd_odt; */
 179                 PHY_DRV_ODT_60, /* wr_dq_drv; */
 180                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 181                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 182                 1,      /* rd_odt_en; */
 183                 20,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 184         },
 185 };
 186
 187 static struct io_setting *
 188 lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
 189 {
 190         struct io_setting *io = NULL;
 191         u32 n;
 192
 193         for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
 194                 io = &lpddr4_io_setting[n];
 195
 196                 if (io->mr5 != 0) {
 197                         if (io->mhz >= params->base.ddr_freq &&
 198                             io->mr5 == mr5)
 199                                 break;
 200                 } else {
 201                         if (io->mhz >= params->base.ddr_freq)
 202                                 break;
 203                 }
 204         }
 205
 206         return io;
 207 }
 208
 209 static void *get_denali_ctl(const struct chan_info *chan,
 210                             struct rk3399_sdram_params *params, bool reg)
 211 {
 212         return reg ? &chan->pctl->denali_ctl : &params->pctl_regs.denali_ctl;
 213 }
 214
 215 static void *get_denali_phy(const struct chan_info *chan,
 216                             struct rk3399_sdram_params *params, bool reg)
 217 {
 218         return reg ? &chan->publ->denali_phy : &params->phy_regs.denali_phy;
 219 }
 220
 221 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
 222 {
 223         return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
 224 }
 225
 226 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
 227                             u32 phy)
 228 {
 229         channel &= 0x1;
 230         ctl &= 0x1;
 231         phy &= 0x1;
 232         writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
 233                                    CRU_SFTRST_DDR_PHY(channel, phy),
 234                                    &cru->softrst_con[4]);
 235 }
 236
 237 static void phy_pctrl_reset(struct rk3399_cru *cru,  u32 channel)
 238 {
 239         rkclk_ddr_reset(cru, channel, 1, 1);
 240         udelay(10);
 241
 242         rkclk_ddr_reset(cru, channel, 1, 0);
 243         udelay(10);
 244
 245         rkclk_ddr_reset(cru, channel, 0, 0);
 246         udelay(10);
 247 }
 248
 249 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
 250                                u32 freq)
 251 {
 252         u32 *denali_phy = ddr_publ_regs->denali_phy;
 253
 254         /* From IP spec, only freq small than 125 can enter dll bypass mode */
 255         if (freq <= 125) {
 256                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 257                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 258                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 259                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 260                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 261
 262                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 263                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 264                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 265                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 266         } else {
 267                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 268                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 269                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 270                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 271                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 272
 273                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 274                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 275                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 276                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 277         }
 278 }
 279
 280 static void set_memory_map(const struct chan_info *chan, u32 channel,
 281                            const struct rk3399_sdram_params *params)
 282 {
 283         const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
 284         u32 *denali_ctl = chan->pctl->denali_ctl;
 285         u32 *denali_pi = chan->pi->denali_pi;
 286         u32 cs_map;
 287         u32 reduc;
 288         u32 row;
 289
 290         /* Get row number from ddrconfig setting */
 291         if (sdram_ch->cap_info.ddrconfig < 2 ||
 292             sdram_ch->cap_info.ddrconfig == 4)
 293                 row = 16;
 294         else if (sdram_ch->cap_info.ddrconfig == 3)
 295                 row = 14;
 296         else
 297                 row = 15;
 298
 299         cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
 300         reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
 301
 302         /* Set the dram configuration to ctrl */
 303         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
 304         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 305                         ((3 - sdram_ch->cap_info.bk) << 16) |
 306                         ((16 - row) << 24));
 307
 308         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 309                         cs_map | (reduc << 16));
 310
 311         /* PI_199 PI_COL_DIFF:RW:0:4 */
 312         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
 313
 314         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 315         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 316                         ((3 - sdram_ch->cap_info.bk) << 16) |
 317                         ((16 - row) << 24));
 318
 319         if (params->base.dramtype == LPDDR4) {
 320                 if (cs_map == 1)
 321                         cs_map = 0x5;
 322                 else if (cs_map == 2)
 323                         cs_map = 0xa;
 324                 else
 325                         cs_map = 0xF;
 326         }
 327
 328         /* PI_41 PI_CS_MAP:RW:24:4 */
 329         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 330         if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
 331                 writel(0x2EC7FFFF, &denali_pi[34]);
 332 }
 333
 334 static int phy_io_config(const struct chan_info *chan,
 335                          const struct rk3399_sdram_params *params, u32 mr5)
 336 {
 337         u32 *denali_phy = chan->publ->denali_phy;
 338         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 339         u32 mode_sel;
 340         u32 reg_value;
 341         u32 drv_value, odt_value;
 342         u32 speed;
 343
 344         /* vref setting & mode setting */
 345         if (params->base.dramtype == LPDDR4) {
 346                 struct io_setting *io = lpddr4_get_io_settings(params, mr5);
 347                 u32 rd_vref = io->rd_vref * 1000;
 348
 349                 if (rd_vref < 36700) {
 350                         /* MODE_LV[2:0] = LPDDR4 (Range 2)*/
 351                         vref_mode_dq = 0x7;
 352                         /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
 353                         mode_sel = 0x5;
 354                         vref_value_dq = (rd_vref - 3300) / 521;
 355                 } else {
 356                         /* MODE_LV[2:0] = LPDDR4 (Range 1)*/
 357                         vref_mode_dq = 0x6;
 358                         /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
 359                         mode_sel = 0x4;
 360                         vref_value_dq = (rd_vref - 15300) / 521;
 361                 }
 362                 vref_mode_ac = 0x6;
 363                 /* VDDQ/3/2=16.8% */
 364                 vref_value_ac = 0x3;
 365         } else if (params->base.dramtype == LPDDR3) {
 366                 if (params->base.odt == 1) {
 367                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 368                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 369                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 370                         if (drv_value == PHY_DRV_ODT_48) {
 371                                 switch (odt_value) {
 372                                 case PHY_DRV_ODT_240:
 373                                         vref_value_dq = 0x16;
 374                                         break;
 375                                 case PHY_DRV_ODT_120:
 376                                         vref_value_dq = 0x26;
 377                                         break;
 378                                 case PHY_DRV_ODT_60:
 379                                         vref_value_dq = 0x36;
 380                                         break;
 381                                 default:
 382                                         debug("Invalid ODT value.\n");
 383                                         return -EINVAL;
 384                                 }
 385                         } else if (drv_value == PHY_DRV_ODT_40) {
 386                                 switch (odt_value) {
 387                                 case PHY_DRV_ODT_240:
 388                                         vref_value_dq = 0x19;
 389                                         break;
 390                                 case PHY_DRV_ODT_120:
 391                                         vref_value_dq = 0x23;
 392                                         break;
 393                                 case PHY_DRV_ODT_60:
 394                                         vref_value_dq = 0x31;
 395                                         break;
 396                                 default:
 397                                         debug("Invalid ODT value.\n");
 398                                         return -EINVAL;
 399                                 }
 400                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 401                                 switch (odt_value) {
 402                                 case PHY_DRV_ODT_240:
 403                                         vref_value_dq = 0x17;
 404                                         break;
 405                                 case PHY_DRV_ODT_120:
 406                                         vref_value_dq = 0x20;
 407                                         break;
 408                                 case PHY_DRV_ODT_60:
 409                                         vref_value_dq = 0x2e;
 410                                         break;
 411                                 default:
 412                                         debug("Invalid ODT value.\n");
 413                                         return -EINVAL;
 414                                 }
 415                         } else {
 416                                 debug("Invalid DRV value.\n");
 417                                 return -EINVAL;
 418                         }
 419                 } else {
 420                         vref_mode_dq = 0x2;  /* LPDDR3 */
 421                         vref_value_dq = 0x1f;
 422                 }
 423                 vref_mode_ac = 0x2;
 424                 vref_value_ac = 0x1f;
 425                 mode_sel = 0x0;
 426         } else if (params->base.dramtype == DDR3) {
 427                 /* DDR3L */
 428                 vref_mode_dq = 0x1;
 429                 vref_value_dq = 0x1f;
 430                 vref_mode_ac = 0x1;
 431                 vref_value_ac = 0x1f;
 432                 mode_sel = 0x1;
 433         } else {
 434                 debug("Unknown DRAM type.\n");
 435                 return -EINVAL;
 436         }
 437
 438         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 439
 440         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 441         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 442         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 443         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 444         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 445         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 446         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 447         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 448
 449         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 450
 451         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 452         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 453
 454         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 455         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 456         /* PHY_926 PHY_PAD_DATA_DRIVE */
 457         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 458         /* PHY_927 PHY_PAD_DQS_DRIVE */
 459         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 460         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 461         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 462         /* PHY_929 PHY_PAD_CLK_DRIVE */
 463         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 464         /* PHY_935 PHY_PAD_CKE_DRIVE */
 465         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 466         /* PHY_937 PHY_PAD_RST_DRIVE */
 467         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 468         /* PHY_939 PHY_PAD_CS_DRIVE */
 469         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 470
 471         if (params->base.dramtype == LPDDR4) {
 472                 /* BOOSTP_EN & BOOSTN_EN */
 473                 reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
 474                 /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
 475                 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
 476                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 477                 clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
 478                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 479                 clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
 480                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 481                 clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
 482                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 483                 clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
 484                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 485                 clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
 486                 /* PHY_937 PHY_PAD_RST_DRIVE */
 487                 clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
 488                 /* PHY_939 PHY_PAD_CS_DRIVE */
 489                 clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
 490
 491                 /* SLEWP_EN & SLEWN_EN */
 492                 reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
 493                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 494                 clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
 495                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 496                 clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
 497                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 498                 clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
 499                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 500                 clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
 501                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 502                 clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
 503                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 504                 clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
 505                 /* PHY_937 PHY_PAD_RST_DRIVE */
 506                 clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
 507                 /* PHY_939 PHY_PAD_CS_DRIVE */
 508                 clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
 509         }
 510
 511         /* speed setting */
 512         if (params->base.ddr_freq < 400)
 513                 speed = 0x0;
 514         else if (params->base.ddr_freq < 800)
 515                 speed = 0x1;
 516         else if (params->base.ddr_freq < 1200)
 517                 speed = 0x2;
 518         else
 519                 speed = 0x3;
 520
 521         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 522         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 523         /* PHY_926 PHY_PAD_DATA_DRIVE */
 524         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 525         /* PHY_927 PHY_PAD_DQS_DRIVE */
 526         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 527         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 528         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 529         /* PHY_929 PHY_PAD_CLK_DRIVE */
 530         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 531         /* PHY_935 PHY_PAD_CKE_DRIVE */
 532         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 533         /* PHY_937 PHY_PAD_RST_DRIVE */
 534         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 535         /* PHY_939 PHY_PAD_CS_DRIVE */
 536         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 537
 538         if (params->base.dramtype == LPDDR4) {
 539                 /* RX_CM_INPUT */
 540                 reg_value = PHY_RX_CM_INPUT;
 541                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 542                 clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
 543                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 544                 clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
 545                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 546                 clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
 547                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 548                 clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
 549                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 550                 clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
 551                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 552                 clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
 553                 /* PHY_937 PHY_PAD_RST_DRIVE */
 554                 clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
 555                 /* PHY_939 PHY_PAD_CS_DRIVE */
 556                 clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
 557         }
 558
 559         return 0;
 560 }
 561
 562 static void set_ds_odt(const struct chan_info *chan,
 563                        struct rk3399_sdram_params *params,
 564                        bool ctl_phy_reg, u32 mr5)
 565 {
 566         u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg);
 567         u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
 568         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 569         u32 tsel_idle_select_p, tsel_rd_select_p;
 570         u32 tsel_idle_select_n, tsel_rd_select_n;
 571         u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 572         u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 573         u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
 574         struct io_setting *io = NULL;
 575         u32 soc_odt = 0;
 576         u32 reg_value;
 577
 578         if (params->base.dramtype == LPDDR4) {
 579                 io = lpddr4_get_io_settings(params, mr5);
 580
 581                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 582                 tsel_rd_select_n = io->rd_odt;
 583
 584                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 585                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 586
 587                 tsel_wr_select_dq_p = io->wr_dq_drv;
 588                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 589
 590                 tsel_wr_select_ca_p = io->wr_ca_drv;
 591                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 592
 593                 tsel_ckcs_select_p = io->wr_ckcs_drv;
 594                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 595
 596                 switch (tsel_rd_select_n) {
 597                 case PHY_DRV_ODT_240:
 598                         soc_odt = 1;
 599                         break;
 600                 case PHY_DRV_ODT_120:
 601                         soc_odt = 2;
 602                         break;
 603                 case PHY_DRV_ODT_80:
 604                         soc_odt = 3;
 605                         break;
 606                 case PHY_DRV_ODT_60:
 607                         soc_odt = 4;
 608                         break;
 609                 case PHY_DRV_ODT_48:
 610                         soc_odt = 5;
 611                         break;
 612                 case PHY_DRV_ODT_40:
 613                         soc_odt = 6;
 614                         break;
 615                 case PHY_DRV_ODT_34_3:
 616                         soc_odt = 6;
 617                         printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
 618                                __func__);
 619                         break;
 620                 case PHY_DRV_ODT_HI_Z:
 621                 default:
 622                         soc_odt = 0;
 623                         break;
 624                 }
 625         } else if (params->base.dramtype == LPDDR3) {
 626                 tsel_rd_select_p = PHY_DRV_ODT_240;
 627                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 628
 629                 tsel_idle_select_p = PHY_DRV_ODT_240;
 630                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 631
 632                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 633                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 634
 635                 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 636                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 637
 638                 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
 639                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 640         } else {
 641                 tsel_rd_select_p = PHY_DRV_ODT_240;
 642                 tsel_rd_select_n = PHY_DRV_ODT_240;
 643
 644                 tsel_idle_select_p = PHY_DRV_ODT_240;
 645                 tsel_idle_select_n = PHY_DRV_ODT_240;
 646
 647                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 648                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 649
 650                 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 651                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 652
 653                 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
 654                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 655         }
 656
 657         if (params->base.odt == 1) {
 658                 tsel_rd_en = 1;
 659
 660                 if (params->base.dramtype == LPDDR4)
 661                         tsel_rd_en = io->rd_odt_en;
 662         } else {
 663                 tsel_rd_en = 0;
 664         }
 665
 666         tsel_wr_en = 0;
 667         tsel_idle_en = 0;
 668
 669         /* F0_0 */
 670         clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
 671                         (soc_odt | (CS0_MR22_VAL << 3)) << 16);
 672         /* F2_0, F1_0 */
 673         clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
 674                         ((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
 675                         (soc_odt | (CS0_MR22_VAL << 3)));
 676         /* F0_1 */
 677         clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
 678                         (soc_odt | (CS1_MR22_VAL << 3)) << 16);
 679         /* F2_1, F1_1 */
 680         clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
 681                         ((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
 682                         (soc_odt | (CS1_MR22_VAL << 3)));
 683
 684         /*
 685          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 686          * sets termination values for read/idle cycles and drive strength
 687          * for write cycles for DQ/DM
 688          */
 689         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 690                     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
 691                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 692         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 693         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 694         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 695         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 696
 697         /*
 698          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 699          * sets termination values for read/idle cycles and drive strength
 700          * for write cycles for DQS
 701          */
 702         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 703         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 704         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 705         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 706
 707         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 708         reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
 709         if (params->base.dramtype == LPDDR4) {
 710                 /* LPDDR4 these register read always return 0, so
 711                  * can not use clrsetbits_le32(), need to write32
 712                  */
 713                 writel((0x300 << 8) | reg_value, &denali_phy[544]);
 714                 writel((0x300 << 8) | reg_value, &denali_phy[672]);
 715                 writel((0x300 << 8) | reg_value, &denali_phy[800]);
 716         } else {
 717                 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 718                 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 719                 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 720         }
 721
 722         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 723         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 724
 725         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 726         if (!ctl_phy_reg)
 727                 clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 728
 729         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 730         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 731
 732         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 733         clrsetbits_le32(&denali_phy[939], 0xff,
 734                         tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 735
 736         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 737         clrsetbits_le32(&denali_phy[929], 0xff,
 738                         tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 739
 740         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 741         clrsetbits_le32(&denali_phy[924], 0xff,
 742                         tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
 743         clrsetbits_le32(&denali_phy[925], 0xff,
 744                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 745
 746         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 747         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 748                 << 16;
 749         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 750         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 751         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 752         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 753
 754         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 755         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 756                 << 24;
 757         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 758         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 759         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 760         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 761
 762         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 763         reg_value = tsel_wr_en << 8;
 764         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 765         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 766         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 767
 768         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 769         reg_value = tsel_wr_en << 17;
 770         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 771         /*
 772          * pad_rst/cke/cs/clk_term tsel 1bits
 773          * DENALI_PHY_938/936/940/934 offset_17
 774          */
 775         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 776         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 777         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 778         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 779
 780         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 781         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 782
 783         phy_io_config(chan, params, mr5);
 784 }
 785
 786 static void pctl_start(struct dram_info *dram,
 787                        struct rk3399_sdram_params *params,
 788                        u32 channel_mask)
 789 {
 790         const struct chan_info *chan_0 = &dram->chan[0];
 791         const struct chan_info *chan_1 = &dram->chan[1];
 792
 793         u32 *denali_ctl_0 = chan_0->pctl->denali_ctl;
 794         u32 *denali_phy_0 = chan_0->publ->denali_phy;
 795         u32 *ddrc0_con_0 = get_ddrc0_con(dram, 0);
 796         u32 *denali_ctl_1 = chan_1->pctl->denali_ctl;
 797         u32 *denali_phy_1 = chan_1->publ->denali_phy;
 798         u32 *ddrc1_con_0 = get_ddrc0_con(dram, 1);
 799         u32 count = 0;
 800         u32 byte, tmp;
 801
 802         /* PHY_DLL_RST_EN */
 803         if (channel_mask & 1) {
 804                 writel(0x01000000, &ddrc0_con_0);
 805                 clrsetbits_le32(&denali_phy_0[957], 0x3 << 24, 0x2 << 24);
 806         }
 807
 808         if (channel_mask & 1) {
 809                 count = 0;
 810                 while (!(readl(&denali_ctl_0[203]) & (1 << 3))) {
 811                         if (count > 1000) {
 812                                 printf("%s: Failed to init pctl channel 0\n",
 813                                        __func__);
 814                                 while (1)
 815                                         ;
 816                         }
 817                         udelay(1);
 818                         count++;
 819                 }
 820
 821                 writel(0x01000100, &ddrc0_con_0);
 822                 for (byte = 0; byte < 4; byte++)        {
 823                         tmp = 0x820;
 824                         writel((tmp << 16) | tmp,
 825                                &denali_phy_0[53 + (128 * byte)]);
 826                         writel((tmp << 16) | tmp,
 827                                &denali_phy_0[54 + (128 * byte)]);
 828                         writel((tmp << 16) | tmp,
 829                                &denali_phy_0[55 + (128 * byte)]);
 830                         writel((tmp << 16) | tmp,
 831                                &denali_phy_0[56 + (128 * byte)]);
 832                         writel((tmp << 16) | tmp,
 833                                &denali_phy_0[57 + (128 * byte)]);
 834                         clrsetbits_le32(&denali_phy_0[58 + (128 * byte)],
 835                                         0xffff, tmp);
 836                 }
 837                 clrsetbits_le32(&denali_ctl_0[68], PWRUP_SREFRESH_EXIT,
 838                                 dram->pwrup_srefresh_exit[0]);
 839         }
 840
 841         if (channel_mask & 2) {
 842                 writel(0x01000000, &ddrc1_con_0);
 843                 clrsetbits_le32(&denali_phy_1[957], 0x3 << 24, 0x2 << 24);
 844         }
 845         if (channel_mask & 2) {
 846                 count = 0;
 847                 while (!(readl(&denali_ctl_1[203]) & (1 << 3))) {
 848                         if (count > 1000) {
 849                                 printf("%s: Failed to init pctl channel 1\n",
 850                                        __func__);
 851                                 while (1)
 852                                         ;
 853                         }
 854                         udelay(1);
 855                         count++;
 856                 }
 857
 858                 writel(0x01000100, &ddrc1_con_0);
 859                 for (byte = 0; byte < 4; byte++)        {
 860                         tmp = 0x820;
 861                         writel((tmp << 16) | tmp,
 862                                &denali_phy_1[53 + (128 * byte)]);
 863                         writel((tmp << 16) | tmp,
 864                                &denali_phy_1[54 + (128 * byte)]);
 865                         writel((tmp << 16) | tmp,
 866                                &denali_phy_1[55 + (128 * byte)]);
 867                         writel((tmp << 16) | tmp,
 868                                &denali_phy_1[56 + (128 * byte)]);
 869                         writel((tmp << 16) | tmp,
 870                                &denali_phy_1[57 + (128 * byte)]);
 871                         clrsetbits_le32(&denali_phy_1[58 + (128 * byte)],
 872                                         0xffff, tmp);
 873                 }
 874
 875                 clrsetbits_le32(&denali_ctl_1[68], PWRUP_SREFRESH_EXIT,
 876                                 dram->pwrup_srefresh_exit[1]);
 877
 878                 /*
 879                  * restore channel 1 RESET original setting
 880                  * to avoid 240ohm too weak to prevent ESD test
 881                  */
 882                 if (params->base.dramtype == LPDDR4)
 883                         clrsetbits_le32(&denali_phy_1[937], 0xff,
 884                                         params->phy_regs.denali_phy[937] &
 885                                         0xFF);
 886         }
 887 }
 888
 889 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 890                     u32 channel, struct rk3399_sdram_params *params)
 891 {
 892         u32 *denali_ctl = chan->pctl->denali_ctl;
 893         u32 *denali_pi = chan->pi->denali_pi;
 894         u32 *denali_phy = chan->publ->denali_phy;
 895         const u32 *params_ctl = params->pctl_regs.denali_ctl;
 896         const u32 *params_phy = params->phy_regs.denali_phy;
 897         u32 tmp, tmp1, tmp2;
 898         struct rk3399_sdram_params *params_cfg;
 899         u32 byte;
 900
 901         dram->ops->modify_param(chan, params);
 902         /*
 903          * work around controller bug:
 904          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 905          */
 906         sdram_copy_to_reg(&denali_ctl[1], &params_ctl[1],
 907                           sizeof(struct rk3399_ddr_pctl_regs) - 4);
 908         writel(params_ctl[0], &denali_ctl[0]);
 909
 910         /*
 911          * two channel init at the same time, then ZQ Cal Start
 912          * at the same time, it will use the same RZQ, but cannot
 913          * start at the same time.
 914          *
 915          * So, increase tINIT3 for channel 1, will avoid two
 916          * channel ZQ Cal Start at the same time
 917          */
 918         if (params->base.dramtype == LPDDR4 && channel == 1) {
 919                 tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
 920                 tmp1 = readl(&denali_ctl[14]);
 921                 writel(tmp + tmp1, &denali_ctl[14]);
 922         }
 923
 924         sdram_copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 925                           sizeof(struct rk3399_ddr_pi_regs));
 926
 927         /* rank count need to set for init */
 928         set_memory_map(chan, channel, params);
 929
 930         writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
 931         writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 932         writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 933
 934         if (params->base.dramtype == LPDDR4) {
 935                 writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
 936                 writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
 937         }
 938
 939         dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
 940                                              PWRUP_SREFRESH_EXIT;
 941         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 942
 943         /* PHY_DLL_RST_EN */
 944         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 945
 946         setbits_le32(&denali_pi[0], START);
 947         setbits_le32(&denali_ctl[0], START);
 948
 949         /**
 950          * LPDDR4 use PLL bypass mode for init
 951          * not need to wait for the PLL to lock
 952          */
 953         if (params->base.dramtype != LPDDR4) {
 954                 /* Waiting for phy DLL lock */
 955                 while (1) {
 956                         tmp = readl(&denali_phy[920]);
 957                         tmp1 = readl(&denali_phy[921]);
 958                         tmp2 = readl(&denali_phy[922]);
 959                         if ((((tmp >> 16) & 0x1) == 0x1) &&
 960                             (((tmp1 >> 16) & 0x1) == 0x1) &&
 961                             (((tmp1 >> 0) & 0x1) == 0x1) &&
 962                             (((tmp2 >> 0) & 0x1) == 0x1))
 963                                 break;
 964                 }
 965         }
 966
 967         sdram_copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 968         sdram_copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 969         sdram_copy_to_reg(&denali_phy[128], &params_phy[128],
 970                           (218 - 128 + 1) * 4);
 971         sdram_copy_to_reg(&denali_phy[256], &params_phy[256],
 972                           (346 - 256 + 1) * 4);
 973         sdram_copy_to_reg(&denali_phy[384], &params_phy[384],
 974                           (474 - 384 + 1) * 4);
 975         sdram_copy_to_reg(&denali_phy[512], &params_phy[512],
 976                           (549 - 512 + 1) * 4);
 977         sdram_copy_to_reg(&denali_phy[640], &params_phy[640],
 978                           (677 - 640 + 1) * 4);
 979         sdram_copy_to_reg(&denali_phy[768], &params_phy[768],
 980                           (805 - 768 + 1) * 4);
 981
 982         if (params->base.dramtype == LPDDR4)
 983                 params_cfg = dram->ops->get_phy_index_params(1, params);
 984         else
 985                 params_cfg = dram->ops->get_phy_index_params(0, params);
 986
 987         clrsetbits_le32(&params_cfg->phy_regs.denali_phy[896], 0x3 << 8,
 988                         0 << 8);
 989         writel(params_cfg->phy_regs.denali_phy[896], &denali_phy[896]);
 990
 991         writel(params->phy_regs.denali_phy[83] + (0x10 << 16),
 992                &denali_phy[83]);
 993         writel(params->phy_regs.denali_phy[84] + (0x10 << 8),
 994                &denali_phy[84]);
 995         writel(params->phy_regs.denali_phy[211] + (0x10 << 16),
 996                &denali_phy[211]);
 997         writel(params->phy_regs.denali_phy[212] + (0x10 << 8),
 998                &denali_phy[212]);
 999         writel(params->phy_regs.denali_phy[339] + (0x10 << 16),
1000                &denali_phy[339]);
1001         writel(params->phy_regs.denali_phy[340] + (0x10 << 8),
1002                &denali_phy[340]);
1003         writel(params->phy_regs.denali_phy[467] + (0x10 << 16),
1004                &denali_phy[467]);
1005         writel(params->phy_regs.denali_phy[468] + (0x10 << 8),
1006                &denali_phy[468]);
1007
1008         if (params->base.dramtype == LPDDR4) {
1009                 /*
1010                  * to improve write dqs and dq phase from 1.5ns to 3.5ns
1011                  * at 50MHz. this's the measure result from oscilloscope
1012                  * of dqs and dq write signal.
1013                  */
1014                 for (byte = 0; byte < 4; byte++) {
1015                         tmp = 0x680;
1016                         clrsetbits_le32(&denali_phy[1 + (128 * byte)],
1017                                         0xfff << 8, tmp << 8);
1018                 }
1019                 /*
1020                  * to workaround 366ball two channel's RESET connect to
1021                  * one RESET signal of die
1022                  */
1023                 if (channel == 1)
1024                         clrsetbits_le32(&denali_phy[937], 0xff,
1025                                         PHY_DRV_ODT_240 |
1026                                         (PHY_DRV_ODT_240 << 0x4));
1027         }
1028
1029         return 0;
1030 }
1031
1032 static void select_per_cs_training_index(const struct chan_info *chan,
1033                                          u32 rank)
1034 {
1035         u32 *denali_phy = chan->publ->denali_phy;
1036
1037         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
1038         if ((readl(&denali_phy[84]) >> 16) & 1) {
1039                 /*
1040                  * PHY_8/136/264/392
1041                  * phy_per_cs_training_index_X 1bit offset_24
1042                  */
1043                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
1044                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
1045                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
1046                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
1047         }
1048 }
1049
1050 static void override_write_leveling_value(const struct chan_info *chan)
1051 {
1052         u32 *denali_ctl = chan->pctl->denali_ctl;
1053         u32 *denali_phy = chan->publ->denali_phy;
1054         u32 byte;
1055
1056         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
1057         setbits_le32(&denali_phy[896], 1);
1058
1059         /*
1060          * PHY_8/136/264/392
1061          * phy_per_cs_training_multicast_en_X 1bit offset_16
1062          */
1063         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
1064         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
1065         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
1066         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
1067
1068         for (byte = 0; byte < 4; byte++)
1069                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
1070                                 0x200 << 16);
1071
1072         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
1073         clrbits_le32(&denali_phy[896], 1);
1074
1075         /* CTL_200 ctrlupd_req 1bit offset_8 */
1076         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
1077 }
1078
1079 static int data_training_ca(const struct chan_info *chan, u32 channel,
1080                             const struct rk3399_sdram_params *params)
1081 {
1082         u32 *denali_pi = chan->pi->denali_pi;
1083         u32 *denali_phy = chan->publ->denali_phy;
1084         u32 i, tmp;
1085         u32 obs_0, obs_1, obs_2, obs_err = 0;
1086         u32 rank = params->ch[channel].cap_info.rank;
1087         u32 rank_mask;
1088
1089         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1090         writel(0x00003f7c, (&denali_pi[175]));
1091
1092         if (params->base.dramtype == LPDDR4)
1093                 rank_mask = (rank == 1) ? 0x5 : 0xf;
1094         else
1095                 rank_mask = (rank == 1) ? 0x1 : 0x3;
1096
1097         for (i = 0; i < 4; i++) {
1098                 if (!(rank_mask & (1 << i)))
1099                         continue;
1100
1101                 select_per_cs_training_index(chan, i);
1102
1103                 /* PI_100 PI_CALVL_EN:RW:8:2 */
1104                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
1105
1106                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
1107                 clrsetbits_le32(&denali_pi[92],
1108                                 (0x1 << 16) | (0x3 << 24),
1109                                 (0x1 << 16) | (i << 24));
1110
1111                 /* Waiting for training complete */
1112                 while (1) {
1113                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1114                         tmp = readl(&denali_pi[174]) >> 8;
1115                         /*
1116                          * check status obs
1117                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
1118                          */
1119                         obs_0 = readl(&denali_phy[532]);
1120                         obs_1 = readl(&denali_phy[660]);
1121                         obs_2 = readl(&denali_phy[788]);
1122                         if (((obs_0 >> 30) & 0x3) ||
1123                             ((obs_1 >> 30) & 0x3) ||
1124                             ((obs_2 >> 30) & 0x3))
1125                                 obs_err = 1;
1126                         if ((((tmp >> 11) & 0x1) == 0x1) &&
1127                             (((tmp >> 13) & 0x1) == 0x1) &&
1128                             (((tmp >> 5) & 0x1) == 0x0) &&
1129                             obs_err == 0)
1130                                 break;
1131                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
1132                                  (obs_err == 1))
1133                                 return -EIO;
1134                 }
1135
1136                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1137                 writel(0x00003f7c, (&denali_pi[175]));
1138         }
1139
1140         clrbits_le32(&denali_pi[100], 0x3 << 8);
1141
1142         return 0;
1143 }
1144
1145 static int data_training_wl(const struct chan_info *chan, u32 channel,
1146                             const struct rk3399_sdram_params *params)
1147 {
1148         u32 *denali_pi = chan->pi->denali_pi;
1149         u32 *denali_phy = chan->publ->denali_phy;
1150         u32 i, tmp;
1151         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1152         u32 rank = params->ch[channel].cap_info.rank;
1153
1154         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1155         writel(0x00003f7c, (&denali_pi[175]));
1156
1157         for (i = 0; i < rank; i++) {
1158                 select_per_cs_training_index(chan, i);
1159
1160                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
1161                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
1162
1163                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
1164                 clrsetbits_le32(&denali_pi[59],
1165                                 (0x1 << 8) | (0x3 << 16),
1166                                 (0x1 << 8) | (i << 16));
1167
1168                 /* Waiting for training complete */
1169                 while (1) {
1170                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1171                         tmp = readl(&denali_pi[174]) >> 8;
1172
1173                         /*
1174                          * check status obs, if error maybe can not
1175                          * get leveling done PHY_40/168/296/424
1176                          * phy_wrlvl_status_obs_X:0:13
1177                          */
1178                         obs_0 = readl(&denali_phy[40]);
1179                         obs_1 = readl(&denali_phy[168]);
1180                         obs_2 = readl(&denali_phy[296]);
1181                         obs_3 = readl(&denali_phy[424]);
1182                         if (((obs_0 >> 12) & 0x1) ||
1183                             ((obs_1 >> 12) & 0x1) ||
1184                             ((obs_2 >> 12) & 0x1) ||
1185                             ((obs_3 >> 12) & 0x1))
1186                                 obs_err = 1;
1187                         if ((((tmp >> 10) & 0x1) == 0x1) &&
1188                             (((tmp >> 13) & 0x1) == 0x1) &&
1189                             (((tmp >> 4) & 0x1) == 0x0) &&
1190                             obs_err == 0)
1191                                 break;
1192                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
1193                                  (obs_err == 1))
1194                                 return -EIO;
1195                 }
1196
1197                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1198                 writel(0x00003f7c, (&denali_pi[175]));
1199         }
1200
1201         override_write_leveling_value(chan);
1202         clrbits_le32(&denali_pi[60], 0x3 << 8);
1203
1204         return 0;
1205 }
1206
1207 static int data_training_rg(const struct chan_info *chan, u32 channel,
1208                             const struct rk3399_sdram_params *params)
1209 {
1210         u32 *denali_pi = chan->pi->denali_pi;
1211         u32 *denali_phy = chan->publ->denali_phy;
1212         u32 i, tmp;
1213         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1214         u32 rank = params->ch[channel].cap_info.rank;
1215
1216         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1217         writel(0x00003f7c, (&denali_pi[175]));
1218
1219         for (i = 0; i < rank; i++) {
1220                 select_per_cs_training_index(chan, i);
1221
1222                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
1223                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
1224
1225                 /*
1226                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
1227                  * PI_RDLVL_CS:RW:24:2
1228                  */
1229                 clrsetbits_le32(&denali_pi[74],
1230                                 (0x1 << 16) | (0x3 << 24),
1231                                 (0x1 << 16) | (i << 24));
1232
1233                 /* Waiting for training complete */
1234                 while (1) {
1235                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1236                         tmp = readl(&denali_pi[174]) >> 8;
1237
1238                         /*
1239                          * check status obs
1240                          * PHY_43/171/299/427
1241                          *     PHY_GTLVL_STATUS_OBS_x:16:8
1242                          */
1243                         obs_0 = readl(&denali_phy[43]);
1244                         obs_1 = readl(&denali_phy[171]);
1245                         obs_2 = readl(&denali_phy[299]);
1246                         obs_3 = readl(&denali_phy[427]);
1247                         if (((obs_0 >> (16 + 6)) & 0x3) ||
1248                             ((obs_1 >> (16 + 6)) & 0x3) ||
1249                             ((obs_2 >> (16 + 6)) & 0x3) ||
1250                             ((obs_3 >> (16 + 6)) & 0x3))
1251                                 obs_err = 1;
1252                         if ((((tmp >> 9) & 0x1) == 0x1) &&
1253                             (((tmp >> 13) & 0x1) == 0x1) &&
1254                             (((tmp >> 3) & 0x1) == 0x0) &&
1255                             obs_err == 0)
1256                                 break;
1257                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
1258                                  (obs_err == 1))
1259                                 return -EIO;
1260                 }
1261
1262                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1263                 writel(0x00003f7c, (&denali_pi[175]));
1264         }
1265
1266         clrbits_le32(&denali_pi[80], 0x3 << 24);
1267
1268         return 0;
1269 }
1270
1271 static int data_training_rl(const struct chan_info *chan, u32 channel,
1272                             const struct rk3399_sdram_params *params)
1273 {
1274         u32 *denali_pi = chan->pi->denali_pi;
1275         u32 i, tmp;
1276         u32 rank = params->ch[channel].cap_info.rank;
1277
1278         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1279         writel(0x00003f7c, (&denali_pi[175]));
1280
1281         for (i = 0; i < rank; i++) {
1282                 select_per_cs_training_index(chan, i);
1283
1284                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
1285                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
1286
1287                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
1288                 clrsetbits_le32(&denali_pi[74],
1289                                 (0x1 << 8) | (0x3 << 24),
1290                                 (0x1 << 8) | (i << 24));
1291
1292                 /* Waiting for training complete */
1293                 while (1) {
1294                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1295                         tmp = readl(&denali_pi[174]) >> 8;
1296
1297                         /*
1298                          * make sure status obs not report error bit
1299                          * PHY_46/174/302/430
1300                          *     phy_rdlvl_status_obs_X:16:8
1301                          */
1302                         if ((((tmp >> 8) & 0x1) == 0x1) &&
1303                             (((tmp >> 13) & 0x1) == 0x1) &&
1304                             (((tmp >> 2) & 0x1) == 0x0))
1305                                 break;
1306                         else if (((tmp >> 2) & 0x1) == 0x1)
1307                                 return -EIO;
1308                 }
1309
1310                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1311                 writel(0x00003f7c, (&denali_pi[175]));
1312         }
1313
1314         clrbits_le32(&denali_pi[80], 0x3 << 16);
1315
1316         return 0;
1317 }
1318
1319 static int data_training_wdql(const struct chan_info *chan, u32 channel,
1320                               const struct rk3399_sdram_params *params)
1321 {
1322         u32 *denali_pi = chan->pi->denali_pi;
1323         u32 i, tmp;
1324         u32 rank = params->ch[channel].cap_info.rank;
1325         u32 rank_mask;
1326
1327         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1328         writel(0x00003f7c, (&denali_pi[175]));
1329
1330         if (params->base.dramtype == LPDDR4)
1331                 rank_mask = (rank == 1) ? 0x5 : 0xf;
1332         else
1333                 rank_mask = (rank == 1) ? 0x1 : 0x3;
1334
1335         for (i = 0; i < 4; i++) {
1336                 if (!(rank_mask & (1 << i)))
1337                         continue;
1338
1339                 select_per_cs_training_index(chan, i);
1340
1341                 /*
1342                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
1343                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
1344                  */
1345                 clrbits_le32(&denali_pi[181], 0x1 << 8);
1346
1347                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
1348                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
1349
1350                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
1351                 clrsetbits_le32(&denali_pi[121],
1352                                 (0x1 << 8) | (0x3 << 16),
1353                                 (0x1 << 8) | (i << 16));
1354
1355                 /* Waiting for training complete */
1356                 while (1) {
1357                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1358                         tmp = readl(&denali_pi[174]) >> 8;
1359                         if ((((tmp >> 12) & 0x1) == 0x1) &&
1360                             (((tmp >> 13) & 0x1) == 0x1) &&
1361                             (((tmp >> 6) & 0x1) == 0x0))
1362                                 break;
1363                         else if (((tmp >> 6) & 0x1) == 0x1)
1364                                 return -EIO;
1365                 }
1366
1367                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1368                 writel(0x00003f7c, (&denali_pi[175]));
1369         }
1370
1371         clrbits_le32(&denali_pi[124], 0x3 << 16);
1372
1373         return 0;
1374 }
1375
1376 static int data_training(struct dram_info *dram, u32 channel,
1377                          const struct rk3399_sdram_params *params,
1378                          u32 training_flag)
1379 {
1380         struct chan_info *chan = &dram->chan[channel];
1381         u32 *denali_phy = chan->publ->denali_phy;
1382         int ret;
1383
1384         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1385         setbits_le32(&denali_phy[927], (1 << 22));
1386
1387         if (training_flag == PI_FULL_TRAINING) {
1388                 if (params->base.dramtype == LPDDR4) {
1389                         training_flag = PI_WRITE_LEVELING |
1390                                         PI_READ_GATE_TRAINING |
1391                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
1392                 } else if (params->base.dramtype == LPDDR3) {
1393                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1394                                         PI_READ_GATE_TRAINING;
1395                 } else if (params->base.dramtype == DDR3) {
1396                         training_flag = PI_WRITE_LEVELING |
1397                                         PI_READ_GATE_TRAINING |
1398                                         PI_READ_LEVELING;
1399                 }
1400         }
1401
1402         /* ca training(LPDDR4,LPDDR3 support) */
1403         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
1404                 ret = data_training_ca(chan, channel, params);
1405                 if (ret < 0) {
1406                         debug("%s: data training ca failed\n", __func__);
1407                         return ret;
1408                 }
1409         }
1410
1411         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1412         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
1413                 ret = data_training_wl(chan, channel, params);
1414                 if (ret < 0) {
1415                         debug("%s: data training wl failed\n", __func__);
1416                         return ret;
1417                 }
1418         }
1419
1420         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1421         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
1422                 ret = data_training_rg(chan, channel, params);
1423                 if (ret < 0) {
1424                         debug("%s: data training rg failed\n", __func__);
1425                         return ret;
1426                 }
1427         }
1428
1429         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1430         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
1431                 ret = data_training_rl(chan, channel, params);
1432                 if (ret < 0) {
1433                         debug("%s: data training rl failed\n", __func__);
1434                         return ret;
1435                 }
1436         }
1437
1438         /* wdq leveling(LPDDR4 support) */
1439         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1440                 ret = data_training_wdql(chan, channel, params);
1441                 if (ret < 0) {
1442                         debug("%s: data training wdql failed\n", __func__);
1443                         return ret;
1444                 }
1445         }
1446
1447         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1448         clrbits_le32(&denali_phy[927], (1 << 22));
1449
1450         return 0;
1451 }
1452
1453 static void set_ddrconfig(const struct chan_info *chan,
1454                           const struct rk3399_sdram_params *params,
1455                           unsigned char channel, u32 ddrconfig)
1456 {
1457         /* only need to set ddrconfig */
1458         struct msch_regs *ddr_msch_regs = chan->msch;
1459         unsigned int cs0_cap = 0;
1460         unsigned int cs1_cap = 0;
1461
1462         cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1463                         + params->ch[channel].cap_info.col
1464                         + params->ch[channel].cap_info.bk
1465                         + params->ch[channel].cap_info.bw - 20));
1466         if (params->ch[channel].cap_info.rank > 1)
1467                 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1468                                 - params->ch[channel].cap_info.cs1_row);
1469         if (params->ch[channel].cap_info.row_3_4) {
1470                 cs0_cap = cs0_cap * 3 / 4;
1471                 cs1_cap = cs1_cap * 3 / 4;
1472         }
1473
1474         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1475         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1476                &ddr_msch_regs->ddrsize);
1477 }
1478
1479 static void sdram_msch_config(struct msch_regs *msch,
1480                               struct sdram_msch_timings *noc_timings)
1481 {
1482         writel(noc_timings->ddrtiminga0.d32,
1483                &msch->ddrtiminga0.d32);
1484         writel(noc_timings->ddrtimingb0.d32,
1485                &msch->ddrtimingb0.d32);
1486         writel(noc_timings->ddrtimingc0.d32,
1487                &msch->ddrtimingc0.d32);
1488         writel(noc_timings->devtodev0.d32,
1489                &msch->devtodev0.d32);
1490         writel(noc_timings->ddrmode.d32,
1491                &msch->ddrmode.d32);
1492 }
1493
1494 static void dram_all_config(struct dram_info *dram,
1495                             struct rk3399_sdram_params *params)
1496 {
1497         u32 sys_reg2 = 0;
1498         u32 sys_reg3 = 0;
1499         unsigned int channel, idx;
1500
1501         for (channel = 0, idx = 0;
1502              (idx < params->base.num_channels) && (channel < 2);
1503              channel++) {
1504                 struct msch_regs *ddr_msch_regs;
1505                 struct sdram_msch_timings *noc_timing;
1506
1507                 if (params->ch[channel].cap_info.col == 0)
1508                         continue;
1509                 idx++;
1510                 sdram_org_config(&params->ch[channel].cap_info,
1511                                  &params->base, &sys_reg2,
1512                                  &sys_reg3, channel);
1513                 ddr_msch_regs = dram->chan[channel].msch;
1514                 noc_timing = &params->ch[channel].noc_timings;
1515                 sdram_msch_config(ddr_msch_regs, noc_timing);
1516
1517                 /**
1518                  * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
1519                  *
1520                  * The hardware for LPDDR4 with
1521                  * - CLK0P/N connect to lower 16-bits
1522                  * - CLK1P/N connect to higher 16-bits
1523                  *
1524                  * dfi dram clk is configured via CLK1P/N, so disabling
1525                  * dfi dram clk will disable the CLK1P/N as well for lpddr4.
1526                  */
1527                 if (params->ch[channel].cap_info.rank == 1 &&
1528                     params->base.dramtype != LPDDR4)
1529                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1530                                      1 << 17);
1531         }
1532
1533         writel(sys_reg2, &dram->pmugrf->os_reg2);
1534         writel(sys_reg3, &dram->pmugrf->os_reg3);
1535         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1536                      params->base.stride << 10);
1537
1538         /* reboot hold register set */
1539         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1540                 PRESET_GPIO1_HOLD(1),
1541                 &dram->pmucru->pmucru_rstnhold_con[1]);
1542         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1543 }
1544
1545 static void set_cap_relate_config(const struct chan_info *chan,
1546                                   struct rk3399_sdram_params *params,
1547                                   unsigned int channel)
1548 {
1549         u32 *denali_ctl = chan->pctl->denali_ctl;
1550         u32 tmp;
1551         struct sdram_msch_timings *noc_timing;
1552
1553         if (params->base.dramtype == LPDDR3) {
1554                 tmp = (8 << params->ch[channel].cap_info.bw) /
1555                         (8 << params->ch[channel].cap_info.dbw);
1556
1557                 /**
1558                  * memdata_ratio
1559                  * 1 -> 0, 2 -> 1, 4 -> 2
1560                  */
1561                 clrsetbits_le32(&denali_ctl[197], 0x7,
1562                                 (tmp >> 1));
1563                 clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
1564                                 (tmp >> 1) << 8);
1565         }
1566
1567         noc_timing = &params->ch[channel].noc_timings;
1568
1569         /*
1570          * noc timing bw relate timing is 32 bit, and real bw is 16bit
1571          * actually noc reg is setting at function dram_all_config
1572          */
1573         if (params->ch[channel].cap_info.bw == 16 &&
1574             noc_timing->ddrmode.b.mwrsize == 2) {
1575                 if (noc_timing->ddrmode.b.burstsize)
1576                         noc_timing->ddrmode.b.burstsize -= 1;
1577                 noc_timing->ddrmode.b.mwrsize -= 1;
1578                 noc_timing->ddrtimingc0.b.burstpenalty *= 2;
1579                 noc_timing->ddrtimingc0.b.wrtomwr *= 2;
1580         }
1581 }
1582
1583 static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
1584 {
1585         unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
1586         unsigned int col = params->ch[channel].cap_info.col;
1587         unsigned int bw = params->ch[channel].cap_info.bw;
1588         u16  ddr_cfg_2_rbc[] = {
1589                 /*
1590                  * [6]    highest bit col
1591                  * [5:3]  max row(14+n)
1592                  * [2]    insertion row
1593                  * [1:0]  col(9+n),col, data bus 32bit
1594                  *
1595                  * highbitcol, max_row, insertion_row,  col
1596                  */
1597                 ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
1598                 ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
1599                 ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
1600                 ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
1601                 ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
1602                 ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
1603                 ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
1604                 ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
1605         };
1606         u32 i;
1607
1608         col -= (bw == 2) ? 0 : 1;
1609         col -= 9;
1610
1611         for (i = 0; i < 4; i++) {
1612                 if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
1613                     (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
1614                         break;
1615         }
1616
1617         if (i >= 4)
1618                 i = -EINVAL;
1619
1620         return i;
1621 }
1622
1623 static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
1624 {
1625         rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
1626 }
1627
1628 #if !defined(CONFIG_RAM_RK3399_LPDDR4)
1629 static int data_training_first(struct dram_info *dram, u32 channel, u8 rank,
1630                                struct rk3399_sdram_params *params)
1631 {
1632         u8 training_flag = PI_READ_GATE_TRAINING;
1633
1634         /*
1635          * LPDDR3 CA training msut be trigger before
1636          * other training.
1637          * DDR3 is not have CA training.
1638          */
1639
1640         if (params->base.dramtype == LPDDR3)
1641                 training_flag |= PI_CA_TRAINING;
1642
1643         return data_training(dram, channel, params, training_flag);
1644 }
1645
1646 static int switch_to_phy_index1(struct dram_info *dram,
1647                                 struct rk3399_sdram_params *params)
1648 {
1649         u32 channel;
1650         u32 *denali_phy;
1651         u32 ch_count = params->base.num_channels;
1652         int ret;
1653         int i = 0;
1654
1655         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1656                              1 << 4 | 1 << 2 | 1),
1657                         &dram->cic->cic_ctrl0);
1658         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1659                 mdelay(10);
1660                 i++;
1661                 if (i > 10) {
1662                         debug("index1 frequency change overtime\n");
1663                         return -ETIME;
1664                 }
1665         }
1666
1667         i = 0;
1668         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1669         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1670                 mdelay(10);
1671                 i++;
1672                 if (i > 10) {
1673                         debug("index1 frequency done overtime\n");
1674                         return -ETIME;
1675                 }
1676         }
1677
1678         for (channel = 0; channel < ch_count; channel++) {
1679                 denali_phy = dram->chan[channel].publ->denali_phy;
1680                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1681                 ret = data_training(dram, channel, params, PI_FULL_TRAINING);
1682                 if (ret < 0) {
1683                         debug("index1 training failed\n");
1684                         return ret;
1685                 }
1686         }
1687
1688         return 0;
1689 }
1690
1691 struct rk3399_sdram_params
1692         *get_phy_index_params(u32 phy_fn,
1693                               struct rk3399_sdram_params *params)
1694 {
1695         if (phy_fn == 0)
1696                 return params;
1697         else
1698                 return NULL;
1699 }
1700
1701 void modify_param(const struct chan_info *chan,
1702                   struct rk3399_sdram_params *params)
1703 {
1704         struct rk3399_sdram_params *params_cfg;
1705         u32 *denali_pi_params;
1706
1707         denali_pi_params = params->pi_regs.denali_pi;
1708
1709         /* modify PHY F0/F1/F2 params */
1710         params_cfg = get_phy_index_params(0, params);
1711         set_ds_odt(chan, params_cfg, false, 0);
1712
1713         clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24);
1714         clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24);
1715         clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
1716         clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
1717 }
1718 #else
1719
1720 struct rk3399_sdram_params dfs_cfgs_lpddr4[] = {
1721 #include "sdram-rk3399-lpddr4-400.inc"
1722 #include "sdram-rk3399-lpddr4-800.inc"
1723 };
1724
1725 static struct rk3399_sdram_params
1726         *lpddr4_get_phy_index_params(u32 phy_fn,
1727                                      struct rk3399_sdram_params *params)
1728 {
1729         if (phy_fn == 0)
1730                 return params;
1731         else if (phy_fn == 1)
1732                 return &dfs_cfgs_lpddr4[1];
1733         else if (phy_fn == 2)
1734                 return &dfs_cfgs_lpddr4[0];
1735         else
1736                 return NULL;
1737 }
1738
1739 static void *get_denali_pi(const struct chan_info *chan,
1740                            struct rk3399_sdram_params *params, bool reg)
1741 {
1742         return reg ? &chan->pi->denali_pi : &params->pi_regs.denali_pi;
1743 }
1744
1745 static u32 lpddr4_get_phy_fn(struct rk3399_sdram_params *params, u32 ctl_fn)
1746 {
1747         u32 lpddr4_phy_fn[] = {1, 0, 0xb};
1748
1749         return lpddr4_phy_fn[ctl_fn];
1750 }
1751
1752 static u32 lpddr4_get_ctl_fn(struct rk3399_sdram_params *params, u32 phy_fn)
1753 {
1754         u32 lpddr4_ctl_fn[] = {1, 0, 2};
1755
1756         return lpddr4_ctl_fn[phy_fn];
1757 }
1758
1759 static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
1760 {
1761         return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
1762 }
1763
1764 /*
1765  * read mr_num mode register
1766  * rank = 1: cs0
1767  * rank = 2: cs1
1768  */
1769 static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
1770                    u32 mr_num, u32 *buf)
1771 {
1772         s32 timeout = 100;
1773
1774         writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,
1775                &ddr_pctl_regs->denali_ctl[118]);
1776
1777         while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &
1778                         ((1 << 21) | (1 << 12)))) {
1779                 udelay(1);
1780
1781                 if (timeout <= 0) {
1782                         printf("%s: pctl timeout!\n", __func__);
1783                         return -ETIMEDOUT;
1784                 }
1785
1786                 timeout--;
1787         }
1788
1789         if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {
1790                 *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;
1791         } else {
1792                 printf("%s: read mr failed with 0x%x status\n", __func__,
1793                        readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);
1794                 *buf = 0;
1795         }
1796
1797         setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));
1798
1799         return 0;
1800 }
1801
1802 static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank,
1803                             struct rk3399_sdram_params *params)
1804 {
1805         u64 cs0_cap;
1806         u32 stride;
1807         u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;
1808         u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;
1809         u32 mr5, mr12, mr14;
1810         struct chan_info *chan = &dram->chan[channel];
1811         struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;
1812         void __iomem *addr = NULL;
1813         int ret = 0;
1814         u32 val;
1815
1816         stride = get_ddr_stride(dram->pmusgrf);
1817
1818         if (params->ch[channel].cap_info.col == 0) {
1819                 ret = -EPERM;
1820                 goto end;
1821         }
1822
1823         cs = params->ch[channel].cap_info.rank;
1824         col = params->ch[channel].cap_info.col;
1825         bk = params->ch[channel].cap_info.bk;
1826         bw = params->ch[channel].cap_info.bw;
1827         row_3_4 = params->ch[channel].cap_info.row_3_4;
1828         cs0_row = params->ch[channel].cap_info.cs0_row;
1829         cs1_row = params->ch[channel].cap_info.cs1_row;
1830         ddrconfig = params->ch[channel].cap_info.ddrconfig;
1831
1832         /* 2GB */
1833         params->ch[channel].cap_info.rank = 2;
1834         params->ch[channel].cap_info.col = 10;
1835         params->ch[channel].cap_info.bk = 3;
1836         params->ch[channel].cap_info.bw = 2;
1837         params->ch[channel].cap_info.row_3_4 = 0;
1838         params->ch[channel].cap_info.cs0_row = 15;
1839         params->ch[channel].cap_info.cs1_row = 15;
1840         params->ch[channel].cap_info.ddrconfig = 1;
1841
1842         set_memory_map(chan, channel, params);
1843         params->ch[channel].cap_info.ddrconfig =
1844                         calculate_ddrconfig(params, channel);
1845         set_ddrconfig(chan, params, channel,
1846                       params->ch[channel].cap_info.ddrconfig);
1847         set_cap_relate_config(chan, params, channel);
1848
1849         cs0_cap = (1 << (params->ch[channel].cap_info.bw
1850                         + params->ch[channel].cap_info.col
1851                         + params->ch[channel].cap_info.bk
1852                         + params->ch[channel].cap_info.cs0_row));
1853
1854         if (params->ch[channel].cap_info.row_3_4)
1855                 cs0_cap = cs0_cap * 3 / 4;
1856
1857         if (channel == 0)
1858                 set_ddr_stride(dram->pmusgrf, 0x17);
1859         else
1860                 set_ddr_stride(dram->pmusgrf, 0x18);
1861
1862         /* read and write data to DRAM, avoid be optimized by compiler. */
1863         if (rank == 1)
1864                 addr = (void __iomem *)0x100;
1865         else if (rank == 2)
1866                 addr = (void __iomem *)(cs0_cap + 0x100);
1867
1868         val = readl(addr);
1869         writel(val + 1, addr);
1870
1871         read_mr(ddr_pctl_regs, rank, 5, &mr5);
1872         read_mr(ddr_pctl_regs, rank, 12, &mr12);
1873         read_mr(ddr_pctl_regs, rank, 14, &mr14);
1874
1875         if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {
1876                 ret = -EINVAL;
1877                 goto end;
1878         }
1879 end:
1880         params->ch[channel].cap_info.rank = cs;
1881         params->ch[channel].cap_info.col = col;
1882         params->ch[channel].cap_info.bk = bk;
1883         params->ch[channel].cap_info.bw = bw;
1884         params->ch[channel].cap_info.row_3_4 = row_3_4;
1885         params->ch[channel].cap_info.cs0_row = cs0_row;
1886         params->ch[channel].cap_info.cs1_row = cs1_row;
1887         params->ch[channel].cap_info.ddrconfig = ddrconfig;
1888
1889         set_ddr_stride(dram->pmusgrf, stride);
1890
1891         return ret;
1892 }
1893
1894 static void set_lpddr4_dq_odt(const struct chan_info *chan,
1895                               struct rk3399_sdram_params *params, u32 ctl_fn,
1896                               bool en, bool ctl_phy_reg, u32 mr5)
1897 {
1898         u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1899         u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1900         struct io_setting *io;
1901         u32 reg_value;
1902
1903         io = lpddr4_get_io_settings(params, mr5);
1904         if (en)
1905                 reg_value = io->dq_odt;
1906         else
1907                 reg_value = 0;
1908
1909         switch (ctl_fn) {
1910         case 0:
1911                 clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
1912                 clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
1913
1914                 clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
1915                 clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
1916                 clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
1917                 clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
1918                 break;
1919         case 1:
1920                 clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
1921                 clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
1922
1923                 clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
1924                 clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
1925                 clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
1926                 clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
1927                 break;
1928         case 2:
1929         default:
1930                 clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
1931                 clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
1932
1933                 clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
1934                 clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
1935                 clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
1936                 clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
1937                 break;
1938         }
1939 }
1940
1941 static void set_lpddr4_ca_odt(const struct chan_info *chan,
1942                               struct rk3399_sdram_params *params, u32 ctl_fn,
1943                               bool en, bool ctl_phy_reg, u32 mr5)
1944 {
1945         u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1946         u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1947         struct io_setting *io;
1948         u32 reg_value;
1949
1950         io = lpddr4_get_io_settings(params, mr5);
1951         if (en)
1952                 reg_value = io->ca_odt;
1953         else
1954                 reg_value = 0;
1955
1956         switch (ctl_fn) {
1957         case 0:
1958                 clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
1959                 clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
1960
1961                 clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
1962                 clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
1963                 clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
1964                 clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
1965                 break;
1966         case 1:
1967                 clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
1968                 clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
1969
1970                 clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
1971                 clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
1972                 clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
1973                 clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
1974                 break;
1975         case 2:
1976         default:
1977                 clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
1978                 clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
1979
1980                 clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
1981                 clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
1982                 clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
1983                 clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
1984                 break;
1985         }
1986 }
1987
1988 static void set_lpddr4_MR3(const struct chan_info *chan,
1989                            struct rk3399_sdram_params *params, u32 ctl_fn,
1990                            bool ctl_phy_reg, u32 mr5)
1991 {
1992         u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1993         u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1994         struct io_setting *io;
1995         u32 reg_value;
1996
1997         io = lpddr4_get_io_settings(params, mr5);
1998
1999         reg_value = ((io->pdds << 3) | 1);
2000
2001         switch (ctl_fn) {
2002         case 0:
2003                 clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
2004                 clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
2005
2006                 clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
2007                 clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
2008                 clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
2009                 clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
2010                 break;
2011         case 1:
2012                 clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
2013                                 reg_value << 16);
2014                 clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
2015                                 reg_value << 16);
2016
2017                 clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
2018                 clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
2019                 clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
2020                 clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
2021                 break;
2022         case 2:
2023         default:
2024                 clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
2025                 clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
2026
2027                 clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
2028                 clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
2029                 clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
2030                 clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
2031                 break;
2032         }
2033 }
2034
2035 static void set_lpddr4_MR12(const struct chan_info *chan,
2036                             struct rk3399_sdram_params *params, u32 ctl_fn,
2037                             bool ctl_phy_reg, u32 mr5)
2038 {
2039         u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
2040         u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
2041         struct io_setting *io;
2042         u32 reg_value;
2043
2044         io = lpddr4_get_io_settings(params, mr5);
2045
2046         reg_value = io->ca_vref;
2047
2048         switch (ctl_fn) {
2049         case 0:
2050                 clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
2051                                 reg_value << 16);
2052                 clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
2053                                 reg_value << 16);
2054
2055                 clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
2056                 clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
2057                 clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
2058                 clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
2059                 break;
2060         case 1:
2061                 clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
2062                 clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
2063
2064                 clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
2065                 clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
2066                 clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
2067                 clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
2068                 break;
2069         case 2:
2070         default:
2071                 clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
2072                                 reg_value << 16);
2073                 clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
2074                                 reg_value << 16);
2075
2076                 clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
2077                 clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
2078                 clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
2079                 clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
2080                 break;
2081         }
2082 }
2083
2084 static void set_lpddr4_MR14(const struct chan_info *chan,
2085                             struct rk3399_sdram_params *params, u32 ctl_fn,
2086                             bool ctl_phy_reg, u32 mr5)
2087 {
2088         u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
2089         u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
2090         struct io_setting *io;
2091         u32 reg_value;
2092
2093         io = lpddr4_get_io_settings(params, mr5);
2094
2095         reg_value = io->dq_vref;
2096
2097         switch (ctl_fn) {
2098         case 0:
2099                 clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
2100                                 reg_value << 16);
2101                 clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
2102                                 reg_value << 16);
2103
2104                 clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
2105                 clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
2106                 clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
2107                 clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
2108                 break;
2109         case 1:
2110                 clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
2111                 clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
2112
2113                 clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
2114                 clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
2115                 clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
2116                 clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
2117                 break;
2118         case 2:
2119         default:
2120                 clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
2121                                 reg_value << 16);
2122                 clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
2123                                 reg_value << 16);
2124
2125                 clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
2126                 clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
2127                 clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
2128                 clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
2129                 break;
2130         }
2131 }
2132
2133 void lpddr4_modify_param(const struct chan_info *chan,
2134                          struct rk3399_sdram_params *params)
2135 {
2136         struct rk3399_sdram_params *params_cfg;
2137         u32 *denali_ctl_params;
2138         u32 *denali_pi_params;
2139         u32 *denali_phy_params;
2140
2141         denali_ctl_params = params->pctl_regs.denali_ctl;
2142         denali_pi_params = params->pi_regs.denali_pi;
2143         denali_phy_params = params->phy_regs.denali_phy;
2144
2145         set_lpddr4_dq_odt(chan, params, 2, true, false, 0);
2146         set_lpddr4_ca_odt(chan, params, 2, true, false, 0);
2147         set_lpddr4_MR3(chan, params, 2, false, 0);
2148         set_lpddr4_MR12(chan, params, 2, false, 0);
2149         set_lpddr4_MR14(chan, params, 2, false, 0);
2150         params_cfg = lpddr4_get_phy_index_params(0, params);
2151         set_ds_odt(chan, params_cfg, false, 0);
2152         /* read two cycle preamble */
2153         clrsetbits_le32(&denali_ctl_params[200], 0x3 << 24, 0x3 << 24);
2154         clrsetbits_le32(&denali_phy_params[7], 0x3 << 24, 0x3 << 24);
2155         clrsetbits_le32(&denali_phy_params[135], 0x3 << 24, 0x3 << 24);
2156         clrsetbits_le32(&denali_phy_params[263], 0x3 << 24, 0x3 << 24);
2157         clrsetbits_le32(&denali_phy_params[391], 0x3 << 24, 0x3 << 24);
2158
2159         /* boot frequency two cycle preamble */
2160         clrsetbits_le32(&denali_phy_params[2], 0x3 << 16, 0x3 << 16);
2161         clrsetbits_le32(&denali_phy_params[130], 0x3 << 16, 0x3 << 16);
2162         clrsetbits_le32(&denali_phy_params[258], 0x3 << 16, 0x3 << 16);
2163         clrsetbits_le32(&denali_phy_params[386], 0x3 << 16, 0x3 << 16);
2164
2165         clrsetbits_le32(&denali_pi_params[45], 0x3 << 8, 0x3 << 8);
2166         clrsetbits_le32(&denali_pi_params[58], 0x1, 0x1);
2167
2168         /*
2169          * bypass mode need PHY_SLICE_PWR_RDC_DISABLE_x = 1,
2170          * boot frequency mode use bypass mode
2171          */
2172         setbits_le32(&denali_phy_params[10], 1 << 16);
2173         setbits_le32(&denali_phy_params[138], 1 << 16);
2174         setbits_le32(&denali_phy_params[266], 1 << 16);
2175         setbits_le32(&denali_phy_params[394], 1 << 16);
2176
2177         clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24);
2178         clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24);
2179         clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
2180         clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
2181 }
2182
2183 static void lpddr4_copy_phy(struct dram_info *dram,
2184                             struct rk3399_sdram_params *params, u32 phy_fn,
2185                             struct rk3399_sdram_params *params_cfg,
2186                             u32 channel)
2187 {
2188         u32 *denali_ctl, *denali_phy;
2189         u32 *denali_phy_params;
2190         u32 speed = 0;
2191         u32 ctl_fn, mr5;
2192
2193         denali_ctl = dram->chan[channel].pctl->denali_ctl;
2194         denali_phy = dram->chan[channel].publ->denali_phy;
2195         denali_phy_params = params_cfg->phy_regs.denali_phy;
2196
2197         /* switch index */
2198         clrsetbits_le32(&denali_phy_params[896], 0x3 << 8,
2199                         phy_fn << 8);
2200         writel(denali_phy_params[896], &denali_phy[896]);
2201
2202         /* phy_pll_ctrl_ca, phy_pll_ctrl */
2203         writel(denali_phy_params[911], &denali_phy[911]);
2204
2205         /* phy_low_freq_sel */
2206         clrsetbits_le32(&denali_phy[913], 0x1,
2207                         denali_phy_params[913] & 0x1);
2208
2209         /* phy_grp_slave_delay_x, phy_cslvl_dly_step */
2210         writel(denali_phy_params[916], &denali_phy[916]);
2211         writel(denali_phy_params[917], &denali_phy[917]);
2212         writel(denali_phy_params[918], &denali_phy[918]);
2213
2214         /* phy_adrz_sw_wraddr_shift_x  */
2215         writel(denali_phy_params[512], &denali_phy[512]);
2216         clrsetbits_le32(&denali_phy[513], 0xffff,
2217                         denali_phy_params[513] & 0xffff);
2218         writel(denali_phy_params[640], &denali_phy[640]);
2219         clrsetbits_le32(&denali_phy[641], 0xffff,
2220                         denali_phy_params[641] & 0xffff);
2221         writel(denali_phy_params[768], &denali_phy[768]);
2222         clrsetbits_le32(&denali_phy[769], 0xffff,
2223                         denali_phy_params[769] & 0xffff);
2224
2225         writel(denali_phy_params[544], &denali_phy[544]);
2226         writel(denali_phy_params[545], &denali_phy[545]);
2227         writel(denali_phy_params[546], &denali_phy[546]);
2228         writel(denali_phy_params[547], &denali_phy[547]);
2229
2230         writel(denali_phy_params[672], &denali_phy[672]);
2231         writel(denali_phy_params[673], &denali_phy[673]);
2232         writel(denali_phy_params[674], &denali_phy[674]);
2233         writel(denali_phy_params[675], &denali_phy[675]);
2234
2235         writel(denali_phy_params[800], &denali_phy[800]);
2236         writel(denali_phy_params[801], &denali_phy[801]);
2237         writel(denali_phy_params[802], &denali_phy[802]);
2238         writel(denali_phy_params[803], &denali_phy[803]);
2239
2240         /*
2241          * phy_adr_master_delay_start_x
2242          * phy_adr_master_delay_step_x
2243          * phy_adr_master_delay_wait_x
2244          */
2245         writel(denali_phy_params[548], &denali_phy[548]);
2246         writel(denali_phy_params[676], &denali_phy[676]);
2247         writel(denali_phy_params[804], &denali_phy[804]);
2248
2249         /* phy_adr_calvl_dly_step_x */
2250         writel(denali_phy_params[549], &denali_phy[549]);
2251         writel(denali_phy_params[677], &denali_phy[677]);
2252         writel(denali_phy_params[805], &denali_phy[805]);
2253
2254         /*
2255          * phy_clk_wrdm_slave_delay_x
2256          * phy_clk_wrdqz_slave_delay_x
2257          * phy_clk_wrdqs_slave_delay_x
2258          */
2259         sdram_copy_to_reg((u32 *)&denali_phy[59],
2260                           (u32 *)&denali_phy_params[59], (63 - 58) * 4);
2261         sdram_copy_to_reg((u32 *)&denali_phy[187],
2262                           (u32 *)&denali_phy_params[187], (191 - 186) * 4);
2263         sdram_copy_to_reg((u32 *)&denali_phy[315],
2264                           (u32 *)&denali_phy_params[315], (319 - 314) * 4);
2265         sdram_copy_to_reg((u32 *)&denali_phy[443],
2266                           (u32 *)&denali_phy_params[443], (447 - 442) * 4);
2267
2268         /*
2269          * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8
2270          * dqs_tsel_wr_end[7:4] add half cycle
2271          * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8
2272          * dq_tsel_wr_end[7:4] add half cycle
2273          */
2274         writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
2275         writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
2276         writel(denali_phy_params[85], &denali_phy[85]);
2277
2278         writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
2279         writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
2280         writel(denali_phy_params[213], &denali_phy[213]);
2281
2282         writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
2283         writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
2284         writel(denali_phy_params[341], &denali_phy[341]);
2285
2286         writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
2287         writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
2288         writel(denali_phy_params[469], &denali_phy[469]);
2289
2290         /*
2291          * phy_gtlvl_resp_wait_cnt_x
2292          * phy_gtlvl_dly_step_x
2293          * phy_wrlvl_resp_wait_cnt_x
2294          * phy_gtlvl_final_step_x
2295          * phy_gtlvl_back_step_x
2296          * phy_rdlvl_dly_step_x
2297          *
2298          * phy_master_delay_step_x
2299          * phy_master_delay_wait_x
2300          * phy_wrlvl_dly_step_x
2301          * phy_rptr_update_x
2302          * phy_wdqlvl_dly_step_x
2303          */
2304         writel(denali_phy_params[87], &denali_phy[87]);
2305         writel(denali_phy_params[88], &denali_phy[88]);
2306         writel(denali_phy_params[89], &denali_phy[89]);
2307         writel(denali_phy_params[90], &denali_phy[90]);
2308
2309         writel(denali_phy_params[215], &denali_phy[215]);
2310         writel(denali_phy_params[216], &denali_phy[216]);
2311         writel(denali_phy_params[217], &denali_phy[217]);
2312         writel(denali_phy_params[218], &denali_phy[218]);
2313
2314         writel(denali_phy_params[343], &denali_phy[343]);
2315         writel(denali_phy_params[344], &denali_phy[344]);
2316         writel(denali_phy_params[345], &denali_phy[345]);
2317         writel(denali_phy_params[346], &denali_phy[346]);
2318
2319         writel(denali_phy_params[471], &denali_phy[471]);
2320         writel(denali_phy_params[472], &denali_phy[472]);
2321         writel(denali_phy_params[473], &denali_phy[473]);
2322         writel(denali_phy_params[474], &denali_phy[474]);
2323
2324         /*
2325          * phy_gtlvl_lat_adj_start_x
2326          * phy_gtlvl_rddqs_slv_dly_start_x
2327          * phy_rdlvl_rddqs_dq_slv_dly_start_x
2328          * phy_wdqlvl_dqdm_slv_dly_start_x
2329          */
2330         writel(denali_phy_params[80], &denali_phy[80]);
2331         writel(denali_phy_params[81], &denali_phy[81]);
2332
2333         writel(denali_phy_params[208], &denali_phy[208]);
2334         writel(denali_phy_params[209], &denali_phy[209]);
2335
2336         writel(denali_phy_params[336], &denali_phy[336]);
2337         writel(denali_phy_params[337], &denali_phy[337]);
2338
2339         writel(denali_phy_params[464], &denali_phy[464]);
2340         writel(denali_phy_params[465], &denali_phy[465]);
2341
2342         /*
2343          * phy_master_delay_start_x
2344          * phy_sw_master_mode_x
2345          * phy_rddata_en_tsel_dly_x
2346          */
2347         writel(denali_phy_params[86], &denali_phy[86]);
2348         writel(denali_phy_params[214], &denali_phy[214]);
2349         writel(denali_phy_params[342], &denali_phy[342]);
2350         writel(denali_phy_params[470], &denali_phy[470]);
2351
2352         /*
2353          * phy_rddqz_slave_delay_x
2354          * phy_rddqs_dqz_fall_slave_delay_x
2355          * phy_rddqs_dqz_rise_slave_delay_x
2356          * phy_rddqs_dm_fall_slave_delay_x
2357          * phy_rddqs_dm_rise_slave_delay_x
2358          * phy_rddqs_gate_slave_delay_x
2359          * phy_wrlvl_delay_early_threshold_x
2360          * phy_write_path_lat_add_x
2361          * phy_rddqs_latency_adjust_x
2362          * phy_wrlvl_delay_period_threshold_x
2363          * phy_wrlvl_early_force_zero_x
2364          */
2365         sdram_copy_to_reg((u32 *)&denali_phy[64],
2366                           (u32 *)&denali_phy_params[64], (67 - 63) * 4);
2367         clrsetbits_le32(&denali_phy[68], 0xfffffc00,
2368                         denali_phy_params[68] & 0xfffffc00);
2369         sdram_copy_to_reg((u32 *)&denali_phy[69],
2370                           (u32 *)&denali_phy_params[69], (79 - 68) * 4);
2371         sdram_copy_to_reg((u32 *)&denali_phy[192],
2372                           (u32 *)&denali_phy_params[192], (195 - 191) * 4);
2373         clrsetbits_le32(&denali_phy[196], 0xfffffc00,
2374                         denali_phy_params[196] & 0xfffffc00);
2375         sdram_copy_to_reg((u32 *)&denali_phy[197],
2376                           (u32 *)&denali_phy_params[197], (207 - 196) * 4);
2377         sdram_copy_to_reg((u32 *)&denali_phy[320],
2378                           (u32 *)&denali_phy_params[320], (323 - 319) * 4);
2379         clrsetbits_le32(&denali_phy[324], 0xfffffc00,
2380                         denali_phy_params[324] & 0xfffffc00);
2381         sdram_copy_to_reg((u32 *)&denali_phy[325],
2382                           (u32 *)&denali_phy_params[325], (335 - 324) * 4);
2383         sdram_copy_to_reg((u32 *)&denali_phy[448],
2384                           (u32 *)&denali_phy_params[448], (451 - 447) * 4);
2385         clrsetbits_le32(&denali_phy[452], 0xfffffc00,
2386                         denali_phy_params[452] & 0xfffffc00);
2387         sdram_copy_to_reg((u32 *)&denali_phy[453],
2388                           (u32 *)&denali_phy_params[453], (463 - 452) * 4);
2389
2390         /* phy_two_cyc_preamble_x */
2391         clrsetbits_le32(&denali_phy[7], 0x3 << 24,
2392                         denali_phy_params[7] & (0x3 << 24));
2393         clrsetbits_le32(&denali_phy[135], 0x3 << 24,
2394                         denali_phy_params[135] & (0x3 << 24));
2395         clrsetbits_le32(&denali_phy[263], 0x3 << 24,
2396                         denali_phy_params[263] & (0x3 << 24));
2397         clrsetbits_le32(&denali_phy[391], 0x3 << 24,
2398                         denali_phy_params[391] & (0x3 << 24));
2399
2400         /* speed */
2401         if (params_cfg->base.ddr_freq < 400)
2402                 speed = 0x0;
2403         else if (params_cfg->base.ddr_freq < 800)
2404                 speed = 0x1;
2405         else if (params_cfg->base.ddr_freq < 1200)
2406                 speed = 0x2;
2407
2408         /* phy_924 phy_pad_fdbk_drive */
2409         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
2410         /* phy_926 phy_pad_data_drive */
2411         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
2412         /* phy_927 phy_pad_dqs_drive */
2413         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
2414         /* phy_928 phy_pad_addr_drive */
2415         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
2416         /* phy_929 phy_pad_clk_drive */
2417         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
2418         /* phy_935 phy_pad_cke_drive */
2419         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
2420         /* phy_937 phy_pad_rst_drive */
2421         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
2422         /* phy_939 phy_pad_cs_drive */
2423         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
2424
2425         if (params_cfg->base.dramtype == LPDDR4) {
2426                 read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
2427                 set_ds_odt(&dram->chan[channel], params_cfg, true, mr5);
2428
2429                 ctl_fn = lpddr4_get_ctl_fn(params_cfg, phy_fn);
2430                 set_lpddr4_dq_odt(&dram->chan[channel], params_cfg,
2431                                   ctl_fn, true, true, mr5);
2432                 set_lpddr4_ca_odt(&dram->chan[channel], params_cfg,
2433                                   ctl_fn, true, true, mr5);
2434                 set_lpddr4_MR3(&dram->chan[channel], params_cfg,
2435                                ctl_fn, true, mr5);
2436                 set_lpddr4_MR12(&dram->chan[channel], params_cfg,
2437                                 ctl_fn, true, mr5);
2438                 set_lpddr4_MR14(&dram->chan[channel], params_cfg,
2439                                 ctl_fn, true, mr5);
2440
2441                 /*
2442                  * if phy_sw_master_mode_x not bypass mode,
2443                  * clear phy_slice_pwr_rdc_disable.
2444                  * note: need use timings, not ddr_publ_regs
2445                  */
2446                 if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
2447                         clrbits_le32(&denali_phy[10], 1 << 16);
2448                         clrbits_le32(&denali_phy[138], 1 << 16);
2449                         clrbits_le32(&denali_phy[266], 1 << 16);
2450                         clrbits_le32(&denali_phy[394], 1 << 16);
2451                 }
2452
2453                 /*
2454                  * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
2455                  * smaller than 8
2456                  * NOTE: need use timings, not ddr_publ_regs
2457                  */
2458                 if ((denali_phy_params[84] >> 16) & 1) {
2459                         if (((readl(&denali_ctl[217 + ctl_fn]) >>
2460                                 16) & 0x1f) < 8)
2461                                 clrsetbits_le32(&denali_ctl[217 + ctl_fn],
2462                                                 0x1f << 16,
2463                                                 8 << 16);
2464                 }
2465         }
2466 }
2467
2468 static void lpddr4_set_phy(struct dram_info *dram,
2469                            struct rk3399_sdram_params *params, u32 phy_fn,
2470                            struct rk3399_sdram_params *params_cfg)
2471 {
2472         u32 channel;
2473
2474         for (channel = 0; channel < 2; channel++)
2475                 lpddr4_copy_phy(dram, params, phy_fn, params_cfg,
2476                                 channel);
2477 }
2478
2479 static int lpddr4_set_ctl(struct dram_info *dram,
2480                           struct rk3399_sdram_params *params,
2481                           u32 fn, u32 hz)
2482 {
2483         u32 channel;
2484         int ret_clk, ret;
2485
2486         /* cci idle req stall */
2487         writel(0x70007, &dram->grf->soc_con0);
2488
2489         /* enable all clk */
2490         setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
2491
2492         /* idle */
2493         setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
2494         while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
2495                != (0x3 << 18))
2496                 ;
2497
2498         /* change freq */
2499         writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
2500                 (fn << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
2501         while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
2502                 ;
2503
2504         ret_clk = clk_set_rate(&dram->ddr_clk, hz);
2505         if (ret_clk < 0) {
2506                 printf("%s clk set failed %d\n", __func__, ret_clk);
2507                 return ret_clk;
2508         }
2509
2510         writel(0x20002, &dram->cic->cic_ctrl0);
2511         while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
2512                 ;
2513
2514         /* deidle */
2515         clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
2516         while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
2517                 ;
2518
2519         /* clear enable all clk */
2520         clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
2521
2522         /* lpddr4 ctl2 can not do training, all training will fail */
2523         if (!(params->base.dramtype == LPDDR4 && fn == 2)) {
2524                 for (channel = 0; channel < 2; channel++) {
2525                         if (!(params->ch[channel].cap_info.col))
2526                                 continue;
2527                         ret = data_training(dram, channel, params,
2528                                             PI_FULL_TRAINING);
2529                         if (ret)
2530                                 printf("%s: channel %d training failed!\n",
2531                                        __func__, channel);
2532                         else
2533                                 debug("%s: channel %d training pass\n",
2534                                       __func__, channel);
2535                 }
2536         }
2537
2538         return 0;
2539 }
2540
2541 static int lpddr4_set_rate(struct dram_info *dram,
2542                            struct rk3399_sdram_params *params)
2543 {
2544         u32 ctl_fn;
2545         u32 phy_fn;
2546
2547         for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) {
2548                 phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
2549
2550                 lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]);
2551                 lpddr4_set_ctl(dram, params, ctl_fn,
2552                                dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
2553
2554                 printf("%s: change freq to %d mhz %d, %d\n", __func__,
2555                        dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, ctl_fn, phy_fn);
2556         }
2557
2558         return 0;
2559 }
2560 #endif /* CONFIG_RAM_RK3399_LPDDR4 */
2561
2562 /* CS0,n=1
2563  * CS1,n=2
2564  * CS0 & CS1, n=3
2565  * cs0_cap: MB unit
2566  */
2567 static void dram_set_cs(const struct chan_info *chan, u32 cs_map, u32 cs0_cap,
2568                         unsigned char dramtype)
2569 {
2570         u32 *denali_ctl = chan->pctl->denali_ctl;
2571         u32 *denali_pi = chan->pi->denali_pi;
2572         struct msch_regs *ddr_msch_regs = chan->msch;
2573
2574         clrsetbits_le32(&denali_ctl[196], 0x3, cs_map);
2575         writel((cs0_cap / 32) | (((4096 - cs0_cap) / 32) << 8),
2576                &ddr_msch_regs->ddrsize);
2577         if (dramtype == LPDDR4) {
2578                 if (cs_map == 1)
2579                         cs_map = 0x5;
2580                 else if (cs_map == 2)
2581                         cs_map = 0xa;
2582                 else
2583                         cs_map = 0xF;
2584         }
2585         /*PI_41 PI_CS_MAP:RW:24:4*/
2586         clrsetbits_le32(&denali_pi[41],
2587                         0xf << 24, cs_map << 24);
2588         if (cs_map == 1 && dramtype == DDR3)
2589                 writel(0x2EC7FFFF, &denali_pi[34]);
2590 }
2591
2592 static void dram_set_bw(const struct chan_info *chan, u32 bw)
2593 {
2594         u32 *denali_ctl = chan->pctl->denali_ctl;
2595
2596         if (bw == 2)
2597                 clrbits_le32(&denali_ctl[196], 1 << 16);
2598         else
2599                 setbits_le32(&denali_ctl[196], 1 << 16);
2600 }
2601
2602 static void dram_set_max_col(const struct chan_info *chan, u32 bw, u32 *pcol)
2603 {
2604         u32 *denali_ctl = chan->pctl->denali_ctl;
2605         struct msch_regs *ddr_msch_regs = chan->msch;
2606         u32 *denali_pi = chan->pi->denali_pi;
2607         u32 ddrconfig;
2608
2609         clrbits_le32(&denali_ctl[191], 0xf);
2610         clrsetbits_le32(&denali_ctl[190],
2611                         (7 << 24),
2612                         ((16 - ((bw == 2) ? 14 : 15)) << 24));
2613         /*PI_199 PI_COL_DIFF:RW:0:4*/
2614         clrbits_le32(&denali_pi[199], 0xf);
2615         /*PI_155 PI_ROW_DIFF:RW:24:3*/
2616         clrsetbits_le32(&denali_pi[155],
2617                         (7 << 24),
2618                         ((16 - 12) << 24));
2619         ddrconfig = (bw == 2) ? 3 : 2;
2620         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
2621         /* set max cs0 size */
2622         writel((4096 / 32) | ((0 / 32) << 8),
2623                &ddr_msch_regs->ddrsize);
2624
2625         *pcol = 12;
2626 }
2627
2628 static void dram_set_max_bank(const struct chan_info *chan, u32 bw, u32 *pbank,
2629                               u32 *pcol)
2630 {
2631         u32 *denali_ctl = chan->pctl->denali_ctl;
2632         u32 *denali_pi = chan->pi->denali_pi;
2633
2634         clrbits_le32(&denali_ctl[191], 0xf);
2635         clrbits_le32(&denali_ctl[190], (3 << 16));
2636         /*PI_199 PI_COL_DIFF:RW:0:4*/
2637         clrbits_le32(&denali_pi[199], 0xf);
2638         /*PI_155 PI_BANK_DIFF:RW:16:2*/
2639         clrbits_le32(&denali_pi[155], (3 << 16));
2640
2641         *pbank = 3;
2642         *pcol = 12;
2643 }
2644
2645 static void dram_set_max_row(const struct chan_info *chan, u32 bw, u32 *prow,
2646                              u32 *pbank, u32 *pcol)
2647 {
2648         u32 *denali_ctl = chan->pctl->denali_ctl;
2649         u32 *denali_pi = chan->pi->denali_pi;
2650         struct msch_regs *ddr_msch_regs = chan->msch;
2651
2652         clrsetbits_le32(&denali_ctl[191], 0xf, 12 - 10);
2653         clrbits_le32(&denali_ctl[190],
2654                      (0x3 << 16) | (0x7 << 24));
2655         /*PI_199 PI_COL_DIFF:RW:0:4*/
2656         clrsetbits_le32(&denali_pi[199], 0xf, 12 - 10);
2657         /*PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2*/
2658         clrbits_le32(&denali_pi[155],
2659                      (0x3 << 16) | (0x7 << 24));
2660         writel(1 | (1 << 8), &ddr_msch_regs->ddrconf);
2661         /* set max cs0 size */
2662         writel((4096 / 32) | ((0 / 32) << 8),
2663                &ddr_msch_regs->ddrsize);
2664
2665         *prow = 16;
2666         *pbank = 3;
2667         *pcol = (bw == 2) ? 10 : 11;
2668 }
2669
2670 static u64 dram_detect_cap(struct dram_info *dram,
2671                            struct rk3399_sdram_params *params,
2672                            unsigned char channel)
2673 {
2674         const struct chan_info *chan = &dram->chan[channel];
2675         struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
2676         u32 bw;
2677         u32 col_tmp;
2678         u32 bk_tmp;
2679         u32 row_tmp;
2680         u32 cs0_cap;
2681         u32 training_flag;
2682         u32 ddrconfig;
2683
2684         /* detect bw */
2685         bw = 2;
2686         if (params->base.dramtype != LPDDR4) {
2687                 dram_set_bw(chan, bw);
2688                 cap_info->bw = bw;
2689                 if (data_training(dram, channel, params,
2690                                   PI_READ_GATE_TRAINING)) {
2691                         bw = 1;
2692                         dram_set_bw(chan, 1);
2693                         cap_info->bw = bw;
2694                         if (data_training(dram, channel, params,
2695                                           PI_READ_GATE_TRAINING)) {
2696                                 printf("16bit error!!!\n");
2697                                 goto error;
2698                         }
2699                 }
2700         }
2701         /*
2702          * LPDDR3 CA training msut be trigger before other training.
2703          * DDR3 is not have CA training.
2704          */
2705         if (params->base.dramtype == LPDDR3)
2706                 training_flag = PI_WRITE_LEVELING;
2707         else
2708                 training_flag = PI_FULL_TRAINING;
2709
2710         if (params->base.dramtype != LPDDR4) {
2711                 if (data_training(dram, channel, params, training_flag)) {
2712                         printf("full training error!!!\n");
2713                         goto error;
2714                 }
2715         }
2716
2717         /* detect col */
2718         dram_set_max_col(chan, bw, &col_tmp);
2719         if (sdram_detect_col(cap_info, col_tmp) != 0)
2720                 goto error;
2721
2722         /* detect bank */
2723         dram_set_max_bank(chan, bw, &bk_tmp, &col_tmp);
2724         sdram_detect_bank(cap_info, col_tmp, bk_tmp);
2725
2726         /* detect row */
2727         dram_set_max_row(chan, bw, &row_tmp, &bk_tmp, &col_tmp);
2728         if (sdram_detect_row(cap_info, col_tmp, bk_tmp, row_tmp) != 0)
2729                 goto error;
2730
2731         /* detect row_3_4 */
2732         sdram_detect_row_3_4(cap_info, col_tmp, bk_tmp);
2733
2734         /* set ddrconfig */
2735         cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + cap_info->bk +
2736                          cap_info->bw - 20));
2737         if (cap_info->row_3_4)
2738                 cs0_cap = cs0_cap * 3 / 4;
2739
2740         cap_info->cs1_row = cap_info->cs0_row;
2741         set_memory_map(chan, channel, params);
2742         ddrconfig = calculate_ddrconfig(params, channel);
2743         if (-1 == ddrconfig)
2744                 goto error;
2745         set_ddrconfig(chan, params, channel,
2746                       cap_info->ddrconfig);
2747
2748         /* detect cs1 row */
2749         sdram_detect_cs1_row(cap_info, params->base.dramtype);
2750
2751         /* detect die bw */
2752         sdram_detect_dbw(cap_info, params->base.dramtype);
2753
2754         return 0;
2755 error:
2756         return (-1);
2757 }
2758
2759 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
2760 {
2761         unsigned int stride = params->base.stride;
2762         unsigned int channel, chinfo = 0;
2763         unsigned int ch_cap[2] = {0, 0};
2764         u64 cap;
2765
2766         for (channel = 0; channel < 2; channel++) {
2767                 unsigned int cs0_cap = 0;
2768                 unsigned int cs1_cap = 0;
2769                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
2770
2771                 if (cap_info->col == 0)
2772                         continue;
2773
2774                 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
2775                                  cap_info->bk + cap_info->bw - 20));
2776                 if (cap_info->rank > 1)
2777                         cs1_cap = cs0_cap >> (cap_info->cs0_row
2778                                               - cap_info->cs1_row);
2779                 if (cap_info->row_3_4) {
2780                         cs0_cap = cs0_cap * 3 / 4;
2781                         cs1_cap = cs1_cap * 3 / 4;
2782                 }
2783                 ch_cap[channel] = cs0_cap + cs1_cap;
2784                 chinfo |= 1 << channel;
2785         }
2786
2787         /* stride calculation for 1 channel */
2788         if (params->base.num_channels == 1 && chinfo & 1)
2789                 return 0x17;    /* channel a */
2790
2791         /* stride calculation for 2 channels, default gstride type is 256B */
2792         if (ch_cap[0] == ch_cap[1]) {
2793                 cap = ch_cap[0] + ch_cap[1];
2794                 switch (cap) {
2795                 /* 512MB */
2796                 case 512:
2797                         stride = 0;
2798                         break;
2799                 /* 1GB */
2800                 case 1024:
2801                         stride = 0x5;
2802                         break;
2803                 /*
2804                  * 768MB + 768MB same as total 2GB memory
2805                  * useful space: 0-768MB 1GB-1792MB
2806                  */
2807                 case 1536:
2808                 /* 2GB */
2809                 case 2048:
2810                         stride = 0x9;
2811                         break;
2812                 /* 1536MB + 1536MB */
2813                 case 3072:
2814                         stride = 0x11;
2815                         break;
2816                 /* 4GB */
2817                 case 4096:
2818                         stride = 0xD;
2819                         break;
2820                 default:
2821                         printf("%s: Unable to calculate stride for ", __func__);
2822                         print_size((cap * (1 << 20)), " capacity\n");
2823                         break;
2824                 }
2825         }
2826
2827         sdram_print_stride(stride);
2828
2829         return stride;
2830 }
2831
2832 static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
2833 {
2834         params->ch[channel].cap_info.rank = 0;
2835         params->ch[channel].cap_info.col = 0;
2836         params->ch[channel].cap_info.bk = 0;
2837         params->ch[channel].cap_info.bw = 32;
2838         params->ch[channel].cap_info.dbw = 32;
2839         params->ch[channel].cap_info.row_3_4 = 0;
2840         params->ch[channel].cap_info.cs0_row = 0;
2841         params->ch[channel].cap_info.cs1_row = 0;
2842         params->ch[channel].cap_info.ddrconfig = 0;
2843 }
2844
2845 static int sdram_init(struct dram_info *dram,
2846                       struct rk3399_sdram_params *params)
2847 {
2848         unsigned char dramtype = params->base.dramtype;
2849         unsigned int ddr_freq = params->base.ddr_freq;
2850         int channel, ch, rank;
2851         u32 tmp, ret;
2852
2853         debug("Starting SDRAM initialization...\n");
2854
2855         if ((dramtype == DDR3 && ddr_freq > 933) ||
2856             (dramtype == LPDDR3 && ddr_freq > 933) ||
2857             (dramtype == LPDDR4 && ddr_freq > 800)) {
2858                 debug("SDRAM frequency is to high!");
2859                 return -E2BIG;
2860         }
2861
2862         /* detect rank */
2863         for (ch = 0; ch < 2; ch++) {
2864                 params->ch[ch].cap_info.rank = 2;
2865                 for (rank = 2; rank != 0; rank--) {
2866                         for (channel = 0; channel < 2; channel++) {
2867                                 const struct chan_info *chan =
2868                                         &dram->chan[channel];
2869                                 struct rk3399_cru *cru = dram->cru;
2870                                 struct rk3399_ddr_publ_regs *publ = chan->publ;
2871
2872                                 phy_pctrl_reset(cru, channel);
2873                                 phy_dll_bypass_set(publ, ddr_freq);
2874                                 pctl_cfg(dram, chan, channel, params);
2875                         }
2876
2877                         /* start to trigger initialization */
2878                         pctl_start(dram, params, 3);
2879
2880                         /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
2881                         if (dramtype == LPDDR3)
2882                                 udelay(10);
2883
2884                         tmp = (rank == 2) ? 3 : 1;
2885                         dram_set_cs(&dram->chan[ch], tmp, 2048,
2886                                     params->base.dramtype);
2887                         params->ch[ch].cap_info.rank = rank;
2888
2889                         ret = dram->ops->data_training_first(dram, ch,
2890                                                              rank, params);
2891                         if (!ret) {
2892                                 debug("%s: data trained for rank %d, ch %d\n",
2893                                       __func__, rank, ch);
2894                                 break;
2895                         }
2896                 }
2897                 /* Computed rank with associated channel number */
2898                 params->ch[ch].cap_info.rank = rank;
2899         }
2900
2901         params->base.num_channels = 0;
2902         for (channel = 0; channel < 2; channel++) {
2903                 const struct chan_info *chan = &dram->chan[channel];
2904                 struct sdram_cap_info *cap_info =
2905                         &params->ch[channel].cap_info;
2906
2907                 if (cap_info->rank == 0) {
2908                         clear_channel_params(params, 1);
2909                         continue;
2910                 } else {
2911                         params->base.num_channels++;
2912                 }
2913
2914                 printf("Channel ");
2915                 printf(channel ? "1: " : "0: ");
2916
2917                 if (channel == 0)
2918                         set_ddr_stride(dram->pmusgrf, 0x17);
2919                 else
2920                         set_ddr_stride(dram->pmusgrf, 0x18);
2921
2922                 if (dram_detect_cap(dram, params, channel)) {
2923                         printf("Cap error!\n");
2924                         continue;
2925                 }
2926
2927                 sdram_print_ddr_info(cap_info, &params->base);
2928                 set_memory_map(chan, channel, params);
2929                 cap_info->ddrconfig =
2930                         calculate_ddrconfig(params, channel);
2931                 if (-1 == cap_info->ddrconfig) {
2932                         printf("no ddrconfig find, Cap not support!\n");
2933                         continue;
2934                 }
2935                 set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
2936                 set_cap_relate_config(chan, params, channel);
2937         }
2938
2939         if (params->base.num_channels == 0) {
2940                 printf("%s: ", __func__);
2941                 sdram_print_dram_type(params->base.dramtype);
2942                 printf(" - %dMHz failed!\n", params->base.ddr_freq);
2943                 return -EINVAL;
2944         }
2945
2946         params->base.stride = calculate_stride(params);
2947         dram_all_config(dram, params);
2948
2949         dram->ops->set_rate_index(dram, params);
2950
2951         debug("Finish SDRAM initialization...\n");
2952         return 0;
2953 }
2954
2955 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
2956 {
2957 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
2958         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
2959         int ret;
2960
2961         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
2962                                  (u32 *)&plat->sdram_params,
2963                                  sizeof(plat->sdram_params) / sizeof(u32));
2964         if (ret) {
2965                 printf("%s: Cannot read rockchip,sdram-params %d\n",
2966                        __func__, ret);
2967                 return ret;
2968         }
2969         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
2970         if (ret)
2971                 printf("%s: regmap failed %d\n", __func__, ret);
2972
2973 #endif
2974         return 0;
2975 }
2976
2977 #if CONFIG_IS_ENABLED(OF_PLATDATA)
2978 static int conv_of_platdata(struct udevice *dev)
2979 {
2980         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
2981         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
2982         int ret;
2983
2984         ret = regmap_init_mem_platdata(dev, dtplat->reg,
2985                                        ARRAY_SIZE(dtplat->reg) / 2,
2986                                        &plat->map);
2987         if (ret)
2988                 return ret;
2989
2990         return 0;
2991 }
2992 #endif
2993
2994 static const struct sdram_rk3399_ops rk3399_ops = {
2995 #if !defined(CONFIG_RAM_RK3399_LPDDR4)
2996         .data_training_first = data_training_first,
2997         .set_rate_index = switch_to_phy_index1,
2998         .modify_param = modify_param,
2999         .get_phy_index_params = get_phy_index_params,
3000 #else
3001         .data_training_first = lpddr4_mr_detect,
3002         .set_rate_index = lpddr4_set_rate,
3003         .modify_param = lpddr4_modify_param,
3004         .get_phy_index_params = lpddr4_get_phy_index_params,
3005 #endif
3006 };
3007
3008 static int rk3399_dmc_init(struct udevice *dev)
3009 {
3010         struct dram_info *priv = dev_get_priv(dev);
3011         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
3012         int ret;
3013 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
3014         struct rk3399_sdram_params *params = &plat->sdram_params;
3015 #else
3016         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
3017         struct rk3399_sdram_params *params =
3018                                         (void *)dtplat->rockchip_sdram_params;
3019
3020         ret = conv_of_platdata(dev);
3021         if (ret)
3022                 return ret;
3023 #endif
3024
3025         priv->ops = &rk3399_ops;
3026         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
3027         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
3028         priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
3029         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
3030         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
3031         priv->pmucru = rockchip_get_pmucru();
3032         priv->cru = rockchip_get_cru();
3033         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
3034         priv->chan[0].pi = regmap_get_range(plat->map, 1);
3035         priv->chan[0].publ = regmap_get_range(plat->map, 2);
3036         priv->chan[0].msch = regmap_get_range(plat->map, 3);
3037         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
3038         priv->chan[1].pi = regmap_get_range(plat->map, 5);
3039         priv->chan[1].publ = regmap_get_range(plat->map, 6);
3040         priv->chan[1].msch = regmap_get_range(plat->map, 7);
3041
3042         debug("con reg %p %p %p %p %p %p %p %p\n",
3043               priv->chan[0].pctl, priv->chan[0].pi,
3044               priv->chan[0].publ, priv->chan[0].msch,
3045               priv->chan[1].pctl, priv->chan[1].pi,
3046               priv->chan[1].publ, priv->chan[1].msch);
3047         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
3048               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
3049
3050 #if CONFIG_IS_ENABLED(OF_PLATDATA)
3051         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
3052 #else
3053         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
3054 #endif
3055         if (ret) {
3056                 printf("%s clk get failed %d\n", __func__, ret);
3057                 return ret;
3058         }
3059
3060         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
3061         if (ret < 0) {
3062                 printf("%s clk set failed %d\n", __func__, ret);
3063                 return ret;
3064         }
3065
3066         ret = sdram_init(priv, params);
3067         if (ret < 0) {
3068                 printf("%s DRAM init failed %d\n", __func__, ret);
3069                 return ret;
3070         }
3071
3072         return 0;
3073 }
3074 #endif
3075
3076 static int rk3399_dmc_probe(struct udevice *dev)
3077 {
3078 #if defined(CONFIG_TPL_BUILD) || \
3079         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
3080         if (rk3399_dmc_init(dev))
3081                 return 0;
3082 #else
3083         struct dram_info *priv = dev_get_priv(dev);
3084
3085         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
3086         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
3087         priv->info.base = CONFIG_SYS_SDRAM_BASE;
3088         priv->info.size =
3089                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
3090 #endif
3091         return 0;
3092 }
3093
3094 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
3095 {
3096         struct dram_info *priv = dev_get_priv(dev);
3097
3098         *info = priv->info;
3099
3100         return 0;
3101 }
3102
3103 static struct ram_ops rk3399_dmc_ops = {
3104         .get_info = rk3399_dmc_get_info,
3105 };
3106
3107 static const struct udevice_id rk3399_dmc_ids[] = {
3108         { .compatible = "rockchip,rk3399-dmc" },
3109         { }
3110 };
3111
3112 U_BOOT_DRIVER(dmc_rk3399) = {
3113         .name = "rockchip_rk3399_dmc",
3114         .id = UCLASS_RAM,
3115         .of_match = rk3399_dmc_ids,
3116         .ops = &rk3399_dmc_ops,
3117 #if defined(CONFIG_TPL_BUILD) || \
3118         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
3119         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
3120 #endif
3121         .probe = rk3399_dmc_probe,
3122         .priv_auto_alloc_size = sizeof(struct dram_info),
3123 #if defined(CONFIG_TPL_BUILD) || \
3124         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
3125         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
3126 #endif
3127 };