drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/sdram_common.h>
  21 #include <asm/arch-rockchip/sdram_rk3399.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  26 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  27 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  28
  29 #define PHY_DRV_ODT_HI_Z        0x0
  30 #define PHY_DRV_ODT_240         0x1
  31 #define PHY_DRV_ODT_120         0x8
  32 #define PHY_DRV_ODT_80          0x9
  33 #define PHY_DRV_ODT_60          0xc
  34 #define PHY_DRV_ODT_48          0xd
  35 #define PHY_DRV_ODT_40          0xe
  36 #define PHY_DRV_ODT_34_3        0xf
  37
  38 #define PHY_BOOSTP_EN           0x1
  39 #define PHY_BOOSTN_EN           0x1
  40 #define PHY_SLEWP_EN            0x1
  41 #define PHY_SLEWN_EN            0x1
  42 #define PHY_RX_CM_INPUT         0x1
  43
  44 #define CRU_SFTRST_DDR_CTRL(ch, n)      ((0x1 << (8 + 16 + (ch) * 4)) | \
  45                                         ((n) << (8 + (ch) * 4)))
  46 #define CRU_SFTRST_DDR_PHY(ch, n)       ((0x1 << (9 + 16 + (ch) * 4)) | \
  47                                         ((n) << (9 + (ch) * 4)))
  48 struct chan_info {
  49         struct rk3399_ddr_pctl_regs *pctl;
  50         struct rk3399_ddr_pi_regs *pi;
  51         struct rk3399_ddr_publ_regs *publ;
  52         struct rk3399_msch_regs *msch;
  53 };
  54
  55 struct dram_info {
  56 #if defined(CONFIG_TPL_BUILD) || \
  57         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  58         u32 pwrup_srefresh_exit[2];
  59         struct chan_info chan[2];
  60         struct clk ddr_clk;
  61         struct rk3399_cru *cru;
  62         struct rk3399_grf_regs *grf;
  63         struct rk3399_pmucru *pmucru;
  64         struct rk3399_pmusgrf_regs *pmusgrf;
  65         struct rk3399_ddr_cic_regs *cic;
  66 #endif
  67         struct ram_info info;
  68         struct rk3399_pmugrf_regs *pmugrf;
  69 };
  70
  71 #if defined(CONFIG_TPL_BUILD) || \
  72         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  73
  74 struct rockchip_dmc_plat {
  75 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  76         struct dtd_rockchip_rk3399_dmc dtplat;
  77 #else
  78         struct rk3399_sdram_params sdram_params;
  79 #endif
  80         struct regmap *map;
  81 };
  82
  83 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
  84 {
  85         return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
  86 }
  87
  88 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  89 {
  90         int i;
  91
  92         for (i = 0; i < n / sizeof(u32); i++) {
  93                 writel(*src, dest);
  94                 src++;
  95                 dest++;
  96         }
  97 }
  98
  99 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
 100                             u32 phy)
 101 {
 102         channel &= 0x1;
 103         ctl &= 0x1;
 104         phy &= 0x1;
 105         writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
 106                                    CRU_SFTRST_DDR_PHY(channel, phy),
 107                                    &cru->softrst_con[4]);
 108 }
 109
 110 static void phy_pctrl_reset(struct rk3399_cru *cru,  u32 channel)
 111 {
 112         rkclk_ddr_reset(cru, channel, 1, 1);
 113         udelay(10);
 114
 115         rkclk_ddr_reset(cru, channel, 1, 0);
 116         udelay(10);
 117
 118         rkclk_ddr_reset(cru, channel, 0, 0);
 119         udelay(10);
 120 }
 121
 122 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
 123                                u32 freq)
 124 {
 125         u32 *denali_phy = ddr_publ_regs->denali_phy;
 126
 127         /* From IP spec, only freq small than 125 can enter dll bypass mode */
 128         if (freq <= 125) {
 129                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 130                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 131                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 132                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 133                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 134
 135                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 136                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 137                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 138                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 139         } else {
 140                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 141                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 142                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 143                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 144                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 145
 146                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 147                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 148                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 149                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 150         }
 151 }
 152
 153 static void set_memory_map(const struct chan_info *chan, u32 channel,
 154                            const struct rk3399_sdram_params *params)
 155 {
 156         const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
 157         u32 *denali_ctl = chan->pctl->denali_ctl;
 158         u32 *denali_pi = chan->pi->denali_pi;
 159         u32 cs_map;
 160         u32 reduc;
 161         u32 row;
 162
 163         /* Get row number from ddrconfig setting */
 164         if (sdram_ch->cap_info.ddrconfig < 2 ||
 165             sdram_ch->cap_info.ddrconfig == 4)
 166                 row = 16;
 167         else if (sdram_ch->cap_info.ddrconfig == 3)
 168                 row = 14;
 169         else
 170                 row = 15;
 171
 172         cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
 173         reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
 174
 175         /* Set the dram configuration to ctrl */
 176         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
 177         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 178                         ((3 - sdram_ch->cap_info.bk) << 16) |
 179                         ((16 - row) << 24));
 180
 181         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 182                         cs_map | (reduc << 16));
 183
 184         /* PI_199 PI_COL_DIFF:RW:0:4 */
 185         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
 186
 187         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 188         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 189                         ((3 - sdram_ch->cap_info.bk) << 16) |
 190                         ((16 - row) << 24));
 191         /* PI_41 PI_CS_MAP:RW:24:4 */
 192         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 193         if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
 194                 writel(0x2EC7FFFF, &denali_pi[34]);
 195 }
 196
 197 static int phy_io_config(const struct chan_info *chan,
 198                          const struct rk3399_sdram_params *params)
 199 {
 200         u32 *denali_phy = chan->publ->denali_phy;
 201         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 202         u32 mode_sel;
 203         u32 reg_value;
 204         u32 drv_value, odt_value;
 205         u32 speed;
 206
 207         /* vref setting */
 208         if (params->base.dramtype == LPDDR4) {
 209                 /* LPDDR4 */
 210                 vref_mode_dq = 0x6;
 211                 vref_value_dq = 0x1f;
 212                 vref_mode_ac = 0x6;
 213                 vref_value_ac = 0x1f;
 214                 mode_sel = 0x6;
 215         } else if (params->base.dramtype == LPDDR3) {
 216                 if (params->base.odt == 1) {
 217                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 218                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 219                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 220                         if (drv_value == PHY_DRV_ODT_48) {
 221                                 switch (odt_value) {
 222                                 case PHY_DRV_ODT_240:
 223                                         vref_value_dq = 0x16;
 224                                         break;
 225                                 case PHY_DRV_ODT_120:
 226                                         vref_value_dq = 0x26;
 227                                         break;
 228                                 case PHY_DRV_ODT_60:
 229                                         vref_value_dq = 0x36;
 230                                         break;
 231                                 default:
 232                                         debug("Invalid ODT value.\n");
 233                                         return -EINVAL;
 234                                 }
 235                         } else if (drv_value == PHY_DRV_ODT_40) {
 236                                 switch (odt_value) {
 237                                 case PHY_DRV_ODT_240:
 238                                         vref_value_dq = 0x19;
 239                                         break;
 240                                 case PHY_DRV_ODT_120:
 241                                         vref_value_dq = 0x23;
 242                                         break;
 243                                 case PHY_DRV_ODT_60:
 244                                         vref_value_dq = 0x31;
 245                                         break;
 246                                 default:
 247                                         debug("Invalid ODT value.\n");
 248                                         return -EINVAL;
 249                                 }
 250                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 251                                 switch (odt_value) {
 252                                 case PHY_DRV_ODT_240:
 253                                         vref_value_dq = 0x17;
 254                                         break;
 255                                 case PHY_DRV_ODT_120:
 256                                         vref_value_dq = 0x20;
 257                                         break;
 258                                 case PHY_DRV_ODT_60:
 259                                         vref_value_dq = 0x2e;
 260                                         break;
 261                                 default:
 262                                         debug("Invalid ODT value.\n");
 263                                         return -EINVAL;
 264                                 }
 265                         } else {
 266                                 debug("Invalid DRV value.\n");
 267                                 return -EINVAL;
 268                         }
 269                 } else {
 270                         vref_mode_dq = 0x2;  /* LPDDR3 */
 271                         vref_value_dq = 0x1f;
 272                 }
 273                 vref_mode_ac = 0x2;
 274                 vref_value_ac = 0x1f;
 275                 mode_sel = 0x0;
 276         } else if (params->base.dramtype == DDR3) {
 277                 /* DDR3L */
 278                 vref_mode_dq = 0x1;
 279                 vref_value_dq = 0x1f;
 280                 vref_mode_ac = 0x1;
 281                 vref_value_ac = 0x1f;
 282                 mode_sel = 0x1;
 283         } else {
 284                 debug("Unknown DRAM type.\n");
 285                 return -EINVAL;
 286         }
 287
 288         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 289
 290         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 291         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 292         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 293         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 294         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 295         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 296         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 297         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 298
 299         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 300
 301         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 302         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 303
 304         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 305         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 306         /* PHY_926 PHY_PAD_DATA_DRIVE */
 307         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 308         /* PHY_927 PHY_PAD_DQS_DRIVE */
 309         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 310         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 311         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 312         /* PHY_929 PHY_PAD_CLK_DRIVE */
 313         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 314         /* PHY_935 PHY_PAD_CKE_DRIVE */
 315         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 316         /* PHY_937 PHY_PAD_RST_DRIVE */
 317         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 318         /* PHY_939 PHY_PAD_CS_DRIVE */
 319         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 320
 321         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 322                 /* BOOSTP_EN & BOOSTN_EN */
 323                 reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
 324                 /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
 325                 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
 326                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 327                 clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
 328                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 329                 clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
 330                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 331                 clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
 332                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 333                 clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
 334                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 335                 clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
 336                 /* PHY_937 PHY_PAD_RST_DRIVE */
 337                 clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
 338                 /* PHY_939 PHY_PAD_CS_DRIVE */
 339                 clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
 340
 341                 /* SLEWP_EN & SLEWN_EN */
 342                 reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
 343                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 344                 clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
 345                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 346                 clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
 347                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 348                 clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
 349                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 350                 clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
 351                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 352                 clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
 353                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 354                 clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
 355                 /* PHY_937 PHY_PAD_RST_DRIVE */
 356                 clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
 357                 /* PHY_939 PHY_PAD_CS_DRIVE */
 358                 clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
 359         }
 360
 361         /* speed setting */
 362         if (params->base.ddr_freq < 400)
 363                 speed = 0x0;
 364         else if (params->base.ddr_freq < 800)
 365                 speed = 0x1;
 366         else if (params->base.ddr_freq < 1200)
 367                 speed = 0x2;
 368         else
 369                 speed = 0x3;
 370
 371         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 372         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 373         /* PHY_926 PHY_PAD_DATA_DRIVE */
 374         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 375         /* PHY_927 PHY_PAD_DQS_DRIVE */
 376         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 377         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 378         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 379         /* PHY_929 PHY_PAD_CLK_DRIVE */
 380         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 381         /* PHY_935 PHY_PAD_CKE_DRIVE */
 382         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 383         /* PHY_937 PHY_PAD_RST_DRIVE */
 384         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 385         /* PHY_939 PHY_PAD_CS_DRIVE */
 386         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 387
 388         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 389                 /* RX_CM_INPUT */
 390                 reg_value = PHY_RX_CM_INPUT;
 391                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 392                 clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
 393                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 394                 clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
 395                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 396                 clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
 397                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 398                 clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
 399                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 400                 clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
 401                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 402                 clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
 403                 /* PHY_937 PHY_PAD_RST_DRIVE */
 404                 clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
 405                 /* PHY_939 PHY_PAD_CS_DRIVE */
 406                 clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
 407         }
 408
 409         return 0;
 410 }
 411
 412 static void set_ds_odt(const struct chan_info *chan,
 413                        const struct rk3399_sdram_params *params)
 414 {
 415         u32 *denali_phy = chan->publ->denali_phy;
 416
 417         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 418         u32 tsel_idle_select_p, tsel_rd_select_p;
 419         u32 tsel_idle_select_n, tsel_rd_select_n;
 420         u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 421         u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 422         u32 reg_value;
 423
 424         if (params->base.dramtype == LPDDR4) {
 425                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 426                 tsel_rd_select_n = PHY_DRV_ODT_240;
 427
 428                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 429                 tsel_idle_select_n = PHY_DRV_ODT_240;
 430
 431                 tsel_wr_select_dq_p = PHY_DRV_ODT_40;
 432                 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 433
 434                 tsel_wr_select_ca_p = PHY_DRV_ODT_40;
 435                 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
 436         } else if (params->base.dramtype == LPDDR3) {
 437                 tsel_rd_select_p = PHY_DRV_ODT_240;
 438                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 439
 440                 tsel_idle_select_p = PHY_DRV_ODT_240;
 441                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 442
 443                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 444                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 445
 446                 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 447                 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
 448         } else {
 449                 tsel_rd_select_p = PHY_DRV_ODT_240;
 450                 tsel_rd_select_n = PHY_DRV_ODT_240;
 451
 452                 tsel_idle_select_p = PHY_DRV_ODT_240;
 453                 tsel_idle_select_n = PHY_DRV_ODT_240;
 454
 455                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 456                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 457
 458                 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 459                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 460         }
 461
 462         if (params->base.odt == 1)
 463                 tsel_rd_en = 1;
 464         else
 465                 tsel_rd_en = 0;
 466
 467         tsel_wr_en = 0;
 468         tsel_idle_en = 0;
 469
 470         /*
 471          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 472          * sets termination values for read/idle cycles and drive strength
 473          * for write cycles for DQ/DM
 474          */
 475         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 476                     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
 477                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 478         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 479         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 480         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 481         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 482
 483         /*
 484          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 485          * sets termination values for read/idle cycles and drive strength
 486          * for write cycles for DQS
 487          */
 488         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 489         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 490         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 491         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 492
 493         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 494         reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
 495         clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 496         clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 497         clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 498
 499         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 500         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 501
 502         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 503         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 504
 505         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 506         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 507
 508         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 509         clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
 510
 511         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 512         clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
 513
 514         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 515         clrsetbits_le32(&denali_phy[924], 0xff,
 516                         tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
 517         clrsetbits_le32(&denali_phy[925], 0xff,
 518                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 519
 520         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 521         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 522                 << 16;
 523         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 524         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 525         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 526         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 527
 528         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 529         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 530                 << 24;
 531         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 532         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 533         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 534         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 535
 536         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 537         reg_value = tsel_wr_en << 8;
 538         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 539         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 540         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 541
 542         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 543         reg_value = tsel_wr_en << 17;
 544         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 545         /*
 546          * pad_rst/cke/cs/clk_term tsel 1bits
 547          * DENALI_PHY_938/936/940/934 offset_17
 548          */
 549         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 550         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 551         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 552         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 553
 554         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 555         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 556
 557         phy_io_config(chan, params);
 558 }
 559
 560 static void pctl_start(struct dram_info *dram, u8 channel)
 561 {
 562         const struct chan_info *chan = &dram->chan[channel];
 563         u32 *denali_ctl = chan->pctl->denali_ctl;
 564         u32 *denali_phy = chan->publ->denali_phy;
 565         u32 *ddrc0_con = get_ddrc0_con(dram, channel);
 566         u32 count = 0;
 567         u32 byte, tmp;
 568
 569         writel(0x01000000, &ddrc0_con);
 570
 571         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 572
 573         while (!(readl(&denali_ctl[203]) & (1 << 3))) {
 574                 if (count > 1000) {
 575                         printf("%s: Failed to init pctl for channel %d\n",
 576                                __func__, channel);
 577                         while (1)
 578                                 ;
 579                 }
 580
 581                 udelay(1);
 582                 count++;
 583         }
 584
 585         writel(0x01000100, &ddrc0_con);
 586
 587         for (byte = 0; byte < 4; byte++) {
 588                 tmp = 0x820;
 589                 writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
 590                 writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
 591                 writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
 592                 writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
 593                 writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
 594
 595                 clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
 596         }
 597
 598         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 599                         dram->pwrup_srefresh_exit[channel]);
 600 }
 601
 602 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 603                     u32 channel, const struct rk3399_sdram_params *params)
 604 {
 605         u32 *denali_ctl = chan->pctl->denali_ctl;
 606         u32 *denali_pi = chan->pi->denali_pi;
 607         u32 *denali_phy = chan->publ->denali_phy;
 608         const u32 *params_ctl = params->pctl_regs.denali_ctl;
 609         const u32 *params_phy = params->phy_regs.denali_phy;
 610         u32 tmp, tmp1, tmp2;
 611
 612         /*
 613          * work around controller bug:
 614          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 615          */
 616         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 617                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 618         writel(params_ctl[0], &denali_ctl[0]);
 619
 620         /*
 621          * two channel init at the same time, then ZQ Cal Start
 622          * at the same time, it will use the same RZQ, but cannot
 623          * start at the same time.
 624          *
 625          * So, increase tINIT3 for channel 1, will avoid two
 626          * channel ZQ Cal Start at the same time
 627          */
 628         if (params->base.dramtype == LPDDR4 && channel == 1) {
 629                 tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
 630                 tmp1 = readl(&denali_ctl[14]);
 631                 writel(tmp + tmp1, &denali_ctl[14]);
 632         }
 633
 634         copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 635                     sizeof(struct rk3399_ddr_pi_regs));
 636
 637         /* rank count need to set for init */
 638         set_memory_map(chan, channel, params);
 639
 640         writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
 641         writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 642         writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 643
 644         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 645                 writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
 646                 writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
 647         }
 648
 649         dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
 650                                              PWRUP_SREFRESH_EXIT;
 651         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 652
 653         /* PHY_DLL_RST_EN */
 654         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 655
 656         setbits_le32(&denali_pi[0], START);
 657         setbits_le32(&denali_ctl[0], START);
 658
 659         /**
 660          * LPDDR4 use PLL bypass mode for init
 661          * not need to wait for the PLL to lock
 662          */
 663         if (params->base.dramtype != LPDDR4) {
 664                 /* Waiting for phy DLL lock */
 665                 while (1) {
 666                         tmp = readl(&denali_phy[920]);
 667                         tmp1 = readl(&denali_phy[921]);
 668                         tmp2 = readl(&denali_phy[922]);
 669                         if ((((tmp >> 16) & 0x1) == 0x1) &&
 670                             (((tmp1 >> 16) & 0x1) == 0x1) &&
 671                             (((tmp1 >> 0) & 0x1) == 0x1) &&
 672                             (((tmp2 >> 0) & 0x1) == 0x1))
 673                                 break;
 674                 }
 675         }
 676
 677         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 678         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 679         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 680         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 681         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 682         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 683         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 684         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 685         set_ds_odt(chan, params);
 686
 687         /*
 688          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 689          * dqs_tsel_wr_end[7:4] add Half cycle
 690          */
 691         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 692         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 693         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 694         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 695         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 696         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 697         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 698         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 699
 700         /*
 701          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 702          * dq_tsel_wr_end[7:4] add Half cycle
 703          */
 704         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 705         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 706         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 707         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 708         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 709         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 710         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 711         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 712
 713         return 0;
 714 }
 715
 716 static void select_per_cs_training_index(const struct chan_info *chan,
 717                                          u32 rank)
 718 {
 719         u32 *denali_phy = chan->publ->denali_phy;
 720
 721         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 722         if ((readl(&denali_phy[84]) >> 16) & 1) {
 723                 /*
 724                  * PHY_8/136/264/392
 725                  * phy_per_cs_training_index_X 1bit offset_24
 726                  */
 727                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 728                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 729                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 730                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 731         }
 732 }
 733
 734 static void override_write_leveling_value(const struct chan_info *chan)
 735 {
 736         u32 *denali_ctl = chan->pctl->denali_ctl;
 737         u32 *denali_phy = chan->publ->denali_phy;
 738         u32 byte;
 739
 740         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 741         setbits_le32(&denali_phy[896], 1);
 742
 743         /*
 744          * PHY_8/136/264/392
 745          * phy_per_cs_training_multicast_en_X 1bit offset_16
 746          */
 747         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 748         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 749         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 750         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 751
 752         for (byte = 0; byte < 4; byte++)
 753                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 754                                 0x200 << 16);
 755
 756         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 757         clrbits_le32(&denali_phy[896], 1);
 758
 759         /* CTL_200 ctrlupd_req 1bit offset_8 */
 760         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 761 }
 762
 763 static int data_training_ca(const struct chan_info *chan, u32 channel,
 764                             const struct rk3399_sdram_params *params)
 765 {
 766         u32 *denali_pi = chan->pi->denali_pi;
 767         u32 *denali_phy = chan->publ->denali_phy;
 768         u32 i, tmp;
 769         u32 obs_0, obs_1, obs_2, obs_err = 0;
 770         u32 rank = params->ch[channel].cap_info.rank;
 771         u32 rank_mask;
 772
 773         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 774         writel(0x00003f7c, (&denali_pi[175]));
 775
 776         if (params->base.dramtype == LPDDR4)
 777                 rank_mask = (rank == 1) ? 0x5 : 0xf;
 778         else
 779                 rank_mask = (rank == 1) ? 0x1 : 0x3;
 780
 781         for (i = 0; i < 4; i++) {
 782                 if (!(rank_mask & (1 << i)))
 783                         continue;
 784
 785                 select_per_cs_training_index(chan, i);
 786
 787                 /* PI_100 PI_CALVL_EN:RW:8:2 */
 788                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
 789
 790                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 791                 clrsetbits_le32(&denali_pi[92],
 792                                 (0x1 << 16) | (0x3 << 24),
 793                                 (0x1 << 16) | (i << 24));
 794
 795                 /* Waiting for training complete */
 796                 while (1) {
 797                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 798                         tmp = readl(&denali_pi[174]) >> 8;
 799                         /*
 800                          * check status obs
 801                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
 802                          */
 803                         obs_0 = readl(&denali_phy[532]);
 804                         obs_1 = readl(&denali_phy[660]);
 805                         obs_2 = readl(&denali_phy[788]);
 806                         if (((obs_0 >> 30) & 0x3) ||
 807                             ((obs_1 >> 30) & 0x3) ||
 808                             ((obs_2 >> 30) & 0x3))
 809                                 obs_err = 1;
 810                         if ((((tmp >> 11) & 0x1) == 0x1) &&
 811                             (((tmp >> 13) & 0x1) == 0x1) &&
 812                             (((tmp >> 5) & 0x1) == 0x0) &&
 813                             obs_err == 0)
 814                                 break;
 815                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
 816                                  (obs_err == 1))
 817                                 return -EIO;
 818                 }
 819
 820                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 821                 writel(0x00003f7c, (&denali_pi[175]));
 822         }
 823
 824         clrbits_le32(&denali_pi[100], 0x3 << 8);
 825
 826         return 0;
 827 }
 828
 829 static int data_training_wl(const struct chan_info *chan, u32 channel,
 830                             const struct rk3399_sdram_params *params)
 831 {
 832         u32 *denali_pi = chan->pi->denali_pi;
 833         u32 *denali_phy = chan->publ->denali_phy;
 834         u32 i, tmp;
 835         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 836         u32 rank = params->ch[channel].cap_info.rank;
 837
 838         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 839         writel(0x00003f7c, (&denali_pi[175]));
 840
 841         for (i = 0; i < rank; i++) {
 842                 select_per_cs_training_index(chan, i);
 843
 844                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
 845                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
 846
 847                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
 848                 clrsetbits_le32(&denali_pi[59],
 849                                 (0x1 << 8) | (0x3 << 16),
 850                                 (0x1 << 8) | (i << 16));
 851
 852                 /* Waiting for training complete */
 853                 while (1) {
 854                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 855                         tmp = readl(&denali_pi[174]) >> 8;
 856
 857                         /*
 858                          * check status obs, if error maybe can not
 859                          * get leveling done PHY_40/168/296/424
 860                          * phy_wrlvl_status_obs_X:0:13
 861                          */
 862                         obs_0 = readl(&denali_phy[40]);
 863                         obs_1 = readl(&denali_phy[168]);
 864                         obs_2 = readl(&denali_phy[296]);
 865                         obs_3 = readl(&denali_phy[424]);
 866                         if (((obs_0 >> 12) & 0x1) ||
 867                             ((obs_1 >> 12) & 0x1) ||
 868                             ((obs_2 >> 12) & 0x1) ||
 869                             ((obs_3 >> 12) & 0x1))
 870                                 obs_err = 1;
 871                         if ((((tmp >> 10) & 0x1) == 0x1) &&
 872                             (((tmp >> 13) & 0x1) == 0x1) &&
 873                             (((tmp >> 4) & 0x1) == 0x0) &&
 874                             obs_err == 0)
 875                                 break;
 876                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
 877                                  (obs_err == 1))
 878                                 return -EIO;
 879                 }
 880
 881                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 882                 writel(0x00003f7c, (&denali_pi[175]));
 883         }
 884
 885         override_write_leveling_value(chan);
 886         clrbits_le32(&denali_pi[60], 0x3 << 8);
 887
 888         return 0;
 889 }
 890
 891 static int data_training_rg(const struct chan_info *chan, u32 channel,
 892                             const struct rk3399_sdram_params *params)
 893 {
 894         u32 *denali_pi = chan->pi->denali_pi;
 895         u32 *denali_phy = chan->publ->denali_phy;
 896         u32 i, tmp;
 897         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 898         u32 rank = params->ch[channel].cap_info.rank;
 899
 900         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 901         writel(0x00003f7c, (&denali_pi[175]));
 902
 903         for (i = 0; i < rank; i++) {
 904                 select_per_cs_training_index(chan, i);
 905
 906                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
 907                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
 908
 909                 /*
 910                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
 911                  * PI_RDLVL_CS:RW:24:2
 912                  */
 913                 clrsetbits_le32(&denali_pi[74],
 914                                 (0x1 << 16) | (0x3 << 24),
 915                                 (0x1 << 16) | (i << 24));
 916
 917                 /* Waiting for training complete */
 918                 while (1) {
 919                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 920                         tmp = readl(&denali_pi[174]) >> 8;
 921
 922                         /*
 923                          * check status obs
 924                          * PHY_43/171/299/427
 925                          *     PHY_GTLVL_STATUS_OBS_x:16:8
 926                          */
 927                         obs_0 = readl(&denali_phy[43]);
 928                         obs_1 = readl(&denali_phy[171]);
 929                         obs_2 = readl(&denali_phy[299]);
 930                         obs_3 = readl(&denali_phy[427]);
 931                         if (((obs_0 >> (16 + 6)) & 0x3) ||
 932                             ((obs_1 >> (16 + 6)) & 0x3) ||
 933                             ((obs_2 >> (16 + 6)) & 0x3) ||
 934                             ((obs_3 >> (16 + 6)) & 0x3))
 935                                 obs_err = 1;
 936                         if ((((tmp >> 9) & 0x1) == 0x1) &&
 937                             (((tmp >> 13) & 0x1) == 0x1) &&
 938                             (((tmp >> 3) & 0x1) == 0x0) &&
 939                             obs_err == 0)
 940                                 break;
 941                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
 942                                  (obs_err == 1))
 943                                 return -EIO;
 944                 }
 945
 946                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 947                 writel(0x00003f7c, (&denali_pi[175]));
 948         }
 949
 950         clrbits_le32(&denali_pi[80], 0x3 << 24);
 951
 952         return 0;
 953 }
 954
 955 static int data_training_rl(const struct chan_info *chan, u32 channel,
 956                             const struct rk3399_sdram_params *params)
 957 {
 958         u32 *denali_pi = chan->pi->denali_pi;
 959         u32 i, tmp;
 960         u32 rank = params->ch[channel].cap_info.rank;
 961
 962         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 963         writel(0x00003f7c, (&denali_pi[175]));
 964
 965         for (i = 0; i < rank; i++) {
 966                 select_per_cs_training_index(chan, i);
 967
 968                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
 969                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
 970
 971                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
 972                 clrsetbits_le32(&denali_pi[74],
 973                                 (0x1 << 8) | (0x3 << 24),
 974                                 (0x1 << 8) | (i << 24));
 975
 976                 /* Waiting for training complete */
 977                 while (1) {
 978                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 979                         tmp = readl(&denali_pi[174]) >> 8;
 980
 981                         /*
 982                          * make sure status obs not report error bit
 983                          * PHY_46/174/302/430
 984                          *     phy_rdlvl_status_obs_X:16:8
 985                          */
 986                         if ((((tmp >> 8) & 0x1) == 0x1) &&
 987                             (((tmp >> 13) & 0x1) == 0x1) &&
 988                             (((tmp >> 2) & 0x1) == 0x0))
 989                                 break;
 990                         else if (((tmp >> 2) & 0x1) == 0x1)
 991                                 return -EIO;
 992                 }
 993
 994                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 995                 writel(0x00003f7c, (&denali_pi[175]));
 996         }
 997
 998         clrbits_le32(&denali_pi[80], 0x3 << 16);
 999
1000         return 0;
1001 }
1002
1003 static int data_training_wdql(const struct chan_info *chan, u32 channel,
1004                               const struct rk3399_sdram_params *params)
1005 {
1006         u32 *denali_pi = chan->pi->denali_pi;
1007         u32 i, tmp;
1008         u32 rank = params->ch[channel].cap_info.rank;
1009         u32 rank_mask;
1010
1011         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1012         writel(0x00003f7c, (&denali_pi[175]));
1013
1014         if (params->base.dramtype == LPDDR4)
1015                 rank_mask = (rank == 1) ? 0x5 : 0xf;
1016         else
1017                 rank_mask = (rank == 1) ? 0x1 : 0x3;
1018
1019         for (i = 0; i < 4; i++) {
1020                 if (!(rank_mask & (1 << i)))
1021                         continue;
1022
1023                 select_per_cs_training_index(chan, i);
1024
1025                 /*
1026                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
1027                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
1028                  */
1029                 clrbits_le32(&denali_pi[181], 0x1 << 8);
1030
1031                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
1032                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
1033
1034                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
1035                 clrsetbits_le32(&denali_pi[121],
1036                                 (0x1 << 8) | (0x3 << 16),
1037                                 (0x1 << 8) | (i << 16));
1038
1039                 /* Waiting for training complete */
1040                 while (1) {
1041                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1042                         tmp = readl(&denali_pi[174]) >> 8;
1043                         if ((((tmp >> 12) & 0x1) == 0x1) &&
1044                             (((tmp >> 13) & 0x1) == 0x1) &&
1045                             (((tmp >> 6) & 0x1) == 0x0))
1046                                 break;
1047                         else if (((tmp >> 6) & 0x1) == 0x1)
1048                                 return -EIO;
1049                 }
1050
1051                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1052                 writel(0x00003f7c, (&denali_pi[175]));
1053         }
1054
1055         clrbits_le32(&denali_pi[124], 0x3 << 16);
1056
1057         return 0;
1058 }
1059
1060 static int data_training(const struct chan_info *chan, u32 channel,
1061                          const struct rk3399_sdram_params *params,
1062                          u32 training_flag)
1063 {
1064         u32 *denali_phy = chan->publ->denali_phy;
1065         int ret;
1066
1067         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1068         setbits_le32(&denali_phy[927], (1 << 22));
1069
1070         if (training_flag == PI_FULL_TRAINING) {
1071                 if (params->base.dramtype == LPDDR4) {
1072                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1073                                         PI_READ_GATE_TRAINING |
1074                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
1075                 } else if (params->base.dramtype == LPDDR3) {
1076                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1077                                         PI_READ_GATE_TRAINING;
1078                 } else if (params->base.dramtype == DDR3) {
1079                         training_flag = PI_WRITE_LEVELING |
1080                                         PI_READ_GATE_TRAINING |
1081                                         PI_READ_LEVELING;
1082                 }
1083         }
1084
1085         /* ca training(LPDDR4,LPDDR3 support) */
1086         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
1087                 ret = data_training_ca(chan, channel, params);
1088                 if (ret < 0) {
1089                         debug("%s: data training ca failed\n", __func__);
1090                         return ret;
1091                 }
1092         }
1093
1094         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1095         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
1096                 ret = data_training_wl(chan, channel, params);
1097                 if (ret < 0) {
1098                         debug("%s: data training wl failed\n", __func__);
1099                         return ret;
1100                 }
1101         }
1102
1103         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1104         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
1105                 ret = data_training_rg(chan, channel, params);
1106                 if (ret < 0) {
1107                         debug("%s: data training rg failed\n", __func__);
1108                         return ret;
1109                 }
1110         }
1111
1112         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1113         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
1114                 ret = data_training_rl(chan, channel, params);
1115                 if (ret < 0) {
1116                         debug("%s: data training rl failed\n", __func__);
1117                         return ret;
1118                 }
1119         }
1120
1121         /* wdq leveling(LPDDR4 support) */
1122         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1123                 ret = data_training_wdql(chan, channel, params);
1124                 if (ret < 0) {
1125                         debug("%s: data training wdql failed\n", __func__);
1126                         return ret;
1127                 }
1128         }
1129
1130         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1131         clrbits_le32(&denali_phy[927], (1 << 22));
1132
1133         return 0;
1134 }
1135
1136 static void set_ddrconfig(const struct chan_info *chan,
1137                           const struct rk3399_sdram_params *params,
1138                           unsigned char channel, u32 ddrconfig)
1139 {
1140         /* only need to set ddrconfig */
1141         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
1142         unsigned int cs0_cap = 0;
1143         unsigned int cs1_cap = 0;
1144
1145         cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1146                         + params->ch[channel].cap_info.col
1147                         + params->ch[channel].cap_info.bk
1148                         + params->ch[channel].cap_info.bw - 20));
1149         if (params->ch[channel].cap_info.rank > 1)
1150                 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1151                                 - params->ch[channel].cap_info.cs1_row);
1152         if (params->ch[channel].cap_info.row_3_4) {
1153                 cs0_cap = cs0_cap * 3 / 4;
1154                 cs1_cap = cs1_cap * 3 / 4;
1155         }
1156
1157         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1158         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1159                &ddr_msch_regs->ddrsize);
1160 }
1161
1162 static void dram_all_config(struct dram_info *dram,
1163                             const struct rk3399_sdram_params *params)
1164 {
1165         u32 sys_reg2 = 0;
1166         u32 sys_reg3 = 0;
1167         unsigned int channel, idx;
1168
1169         sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
1170         sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
1171
1172         for (channel = 0, idx = 0;
1173              (idx < params->base.num_channels) && (channel < 2);
1174              channel++) {
1175                 const struct rk3399_sdram_channel *info = &params->ch[channel];
1176                 struct rk3399_msch_regs *ddr_msch_regs;
1177                 const struct rk3399_msch_timings *noc_timing;
1178
1179                 if (params->ch[channel].cap_info.col == 0)
1180                         continue;
1181                 idx++;
1182                 sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
1183                 sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
1184                 sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
1185                 sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
1186                 sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
1187                 sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
1188                 sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
1189                 SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
1190                 if (info->cap_info.cs1_row)
1191                         SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
1192                                             sys_reg3, channel);
1193                 sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
1194                 sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
1195
1196                 ddr_msch_regs = dram->chan[channel].msch;
1197                 noc_timing = &params->ch[channel].noc_timings;
1198                 writel(noc_timing->ddrtiminga0,
1199                        &ddr_msch_regs->ddrtiminga0);
1200                 writel(noc_timing->ddrtimingb0,
1201                        &ddr_msch_regs->ddrtimingb0);
1202                 writel(noc_timing->ddrtimingc0.d32,
1203                        &ddr_msch_regs->ddrtimingc0);
1204                 writel(noc_timing->devtodev0,
1205                        &ddr_msch_regs->devtodev0);
1206                 writel(noc_timing->ddrmode.d32,
1207                        &ddr_msch_regs->ddrmode);
1208
1209                 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1210                 if (params->ch[channel].cap_info.rank == 1)
1211                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1212                                      1 << 17);
1213         }
1214
1215         writel(sys_reg2, &dram->pmugrf->os_reg2);
1216         writel(sys_reg3, &dram->pmugrf->os_reg3);
1217         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1218                      params->base.stride << 10);
1219
1220         /* reboot hold register set */
1221         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1222                 PRESET_GPIO1_HOLD(1),
1223                 &dram->pmucru->pmucru_rstnhold_con[1]);
1224         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1225 }
1226
1227 static int switch_to_phy_index1(struct dram_info *dram,
1228                                 const struct rk3399_sdram_params *params)
1229 {
1230         u32 channel;
1231         u32 *denali_phy;
1232         u32 ch_count = params->base.num_channels;
1233         int ret;
1234         int i = 0;
1235
1236         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1237                              1 << 4 | 1 << 2 | 1),
1238                         &dram->cic->cic_ctrl0);
1239         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1240                 mdelay(10);
1241                 i++;
1242                 if (i > 10) {
1243                         debug("index1 frequency change overtime\n");
1244                         return -ETIME;
1245                 }
1246         }
1247
1248         i = 0;
1249         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1250         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1251                 mdelay(10);
1252                 i++;
1253                 if (i > 10) {
1254                         debug("index1 frequency done overtime\n");
1255                         return -ETIME;
1256                 }
1257         }
1258
1259         for (channel = 0; channel < ch_count; channel++) {
1260                 denali_phy = dram->chan[channel].publ->denali_phy;
1261                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1262                 ret = data_training(&dram->chan[channel], channel,
1263                                     params, PI_FULL_TRAINING);
1264                 if (ret < 0) {
1265                         debug("index1 training failed\n");
1266                         return ret;
1267                 }
1268         }
1269
1270         return 0;
1271 }
1272
1273 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
1274 {
1275         unsigned int stride = params->base.stride;
1276         unsigned int channel, chinfo = 0;
1277         unsigned int ch_cap[2] = {0, 0};
1278         u64 cap;
1279
1280         for (channel = 0; channel < 2; channel++) {
1281                 unsigned int cs0_cap = 0;
1282                 unsigned int cs1_cap = 0;
1283                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
1284
1285                 if (cap_info->col == 0)
1286                         continue;
1287
1288                 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
1289                                  cap_info->bk + cap_info->bw - 20));
1290                 if (cap_info->rank > 1)
1291                         cs1_cap = cs0_cap >> (cap_info->cs0_row
1292                                               - cap_info->cs1_row);
1293                 if (cap_info->row_3_4) {
1294                         cs0_cap = cs0_cap * 3 / 4;
1295                         cs1_cap = cs1_cap * 3 / 4;
1296                 }
1297                 ch_cap[channel] = cs0_cap + cs1_cap;
1298                 chinfo |= 1 << channel;
1299         }
1300
1301         /* stride calculation for 1 channel */
1302         if (params->base.num_channels == 1 && chinfo & 1)
1303                 return 0x17;    /* channel a */
1304
1305         /* stride calculation for 2 channels, default gstride type is 256B */
1306         if (ch_cap[0] == ch_cap[1]) {
1307                 cap = ch_cap[0] + ch_cap[1];
1308                 switch (cap) {
1309                 /* 512MB */
1310                 case 512:
1311                         stride = 0;
1312                         break;
1313                 /* 1GB */
1314                 case 1024:
1315                         stride = 0x5;
1316                         break;
1317                 /*
1318                  * 768MB + 768MB same as total 2GB memory
1319                  * useful space: 0-768MB 1GB-1792MB
1320                  */
1321                 case 1536:
1322                 /* 2GB */
1323                 case 2048:
1324                         stride = 0x9;
1325                         break;
1326                 /* 1536MB + 1536MB */
1327                 case 3072:
1328                         stride = 0x11;
1329                         break;
1330                 /* 4GB */
1331                 case 4096:
1332                         stride = 0xD;
1333                         break;
1334                 default:
1335                         printf("%s: Unable to calculate stride for ", __func__);
1336                         print_size((cap * (1 << 20)), " capacity\n");
1337                         break;
1338                 }
1339         }
1340
1341         sdram_print_stride(stride);
1342
1343         return stride;
1344 }
1345
1346 static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
1347 {
1348         params->ch[channel].cap_info.rank = 0;
1349         params->ch[channel].cap_info.col = 0;
1350         params->ch[channel].cap_info.bk = 0;
1351         params->ch[channel].cap_info.bw = 32;
1352         params->ch[channel].cap_info.dbw = 32;
1353         params->ch[channel].cap_info.row_3_4 = 0;
1354         params->ch[channel].cap_info.cs0_row = 0;
1355         params->ch[channel].cap_info.cs1_row = 0;
1356         params->ch[channel].cap_info.ddrconfig = 0;
1357 }
1358
1359 static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
1360 {
1361         int channel;
1362         int ret;
1363
1364         for (channel = 0; channel < 2; channel++) {
1365                 const struct chan_info *chan = &dram->chan[channel];
1366                 struct rk3399_cru *cru = dram->cru;
1367                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1368
1369                 phy_pctrl_reset(cru, channel);
1370                 phy_dll_bypass_set(publ, params->base.ddr_freq);
1371
1372                 ret = pctl_cfg(dram, chan, channel, params);
1373                 if (ret < 0) {
1374                         printf("%s: pctl config failed\n", __func__);
1375                         return ret;
1376                 }
1377
1378                 /* start to trigger initialization */
1379                 pctl_start(dram, channel);
1380         }
1381
1382         return 0;
1383 }
1384
1385 static int sdram_init(struct dram_info *dram,
1386                       struct rk3399_sdram_params *params)
1387 {
1388         unsigned char dramtype = params->base.dramtype;
1389         unsigned int ddr_freq = params->base.ddr_freq;
1390         u32 training_flag = PI_READ_GATE_TRAINING;
1391         int channel, ch, rank;
1392         int ret;
1393
1394         debug("Starting SDRAM initialization...\n");
1395
1396         if ((dramtype == DDR3 && ddr_freq > 933) ||
1397             (dramtype == LPDDR3 && ddr_freq > 933) ||
1398             (dramtype == LPDDR4 && ddr_freq > 800)) {
1399                 debug("SDRAM frequency is to high!");
1400                 return -E2BIG;
1401         }
1402
1403         for (ch = 0; ch < 2; ch++) {
1404                 params->ch[ch].cap_info.rank = 2;
1405                 for (rank = 2; rank != 0; rank--) {
1406                         ret = pctl_init(dram, params);
1407                         if (ret < 0) {
1408                                 printf("%s: pctl init failed\n", __func__);
1409                                 return ret;
1410                         }
1411
1412                         /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1413                         if (dramtype == LPDDR3)
1414                                 udelay(10);
1415
1416                         params->ch[ch].cap_info.rank = rank;
1417
1418                         /*
1419                          * LPDDR3 CA training msut be trigger before
1420                          * other training.
1421                          * DDR3 is not have CA training.
1422                          */
1423                         if (params->base.dramtype == LPDDR3)
1424                                 training_flag |= PI_CA_TRAINING;
1425
1426                         if (!(data_training(&dram->chan[ch], ch,
1427                                             params, training_flag)))
1428                                 break;
1429                 }
1430                 /* Computed rank with associated channel number */
1431                 params->ch[ch].cap_info.rank = rank;
1432         }
1433
1434         params->base.num_channels = 0;
1435         for (channel = 0; channel < 2; channel++) {
1436                 const struct chan_info *chan = &dram->chan[channel];
1437                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
1438                 u8 training_flag = PI_FULL_TRAINING;
1439
1440                 if (cap_info->rank == 0) {
1441                         clear_channel_params(params, channel);
1442                         continue;
1443                 } else {
1444                         params->base.num_channels++;
1445                 }
1446
1447                 debug("Channel ");
1448                 debug(channel ? "1: " : "0: ");
1449
1450                 /* LPDDR3 should have write and read gate training */
1451                 if (params->base.dramtype == LPDDR3)
1452                         training_flag = PI_WRITE_LEVELING |
1453                                         PI_READ_GATE_TRAINING;
1454
1455                 if (params->base.dramtype != LPDDR4) {
1456                         ret = data_training(dram, channel, params,
1457                                             training_flag);
1458                         if (!ret) {
1459                                 debug("%s: data train failed for channel %d\n",
1460                                       __func__, ret);
1461                                 continue;
1462                         }
1463                 }
1464
1465                 sdram_print_ddr_info(cap_info, &params->base);
1466
1467                 set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
1468         }
1469
1470         if (params->base.num_channels == 0) {
1471                 printf("%s: ", __func__);
1472                 sdram_print_dram_type(params->base.dramtype);
1473                 printf(" - %dMHz failed!\n", params->base.ddr_freq);
1474                 return -EINVAL;
1475         }
1476
1477         params->base.stride = calculate_stride(params);
1478         dram_all_config(dram, params);
1479         switch_to_phy_index1(dram, params);
1480
1481         debug("Finish SDRAM initialization...\n");
1482         return 0;
1483 }
1484
1485 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1486 {
1487 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1488         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1489         int ret;
1490
1491         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1492                                  (u32 *)&plat->sdram_params,
1493                                  sizeof(plat->sdram_params) / sizeof(u32));
1494         if (ret) {
1495                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1496                        __func__, ret);
1497                 return ret;
1498         }
1499         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1500         if (ret)
1501                 printf("%s: regmap failed %d\n", __func__, ret);
1502
1503 #endif
1504         return 0;
1505 }
1506
1507 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1508 static int conv_of_platdata(struct udevice *dev)
1509 {
1510         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1511         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1512         int ret;
1513
1514         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1515                                        ARRAY_SIZE(dtplat->reg) / 2,
1516                                        &plat->map);
1517         if (ret)
1518                 return ret;
1519
1520         return 0;
1521 }
1522 #endif
1523
1524 static int rk3399_dmc_init(struct udevice *dev)
1525 {
1526         struct dram_info *priv = dev_get_priv(dev);
1527         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1528         int ret;
1529 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1530         struct rk3399_sdram_params *params = &plat->sdram_params;
1531 #else
1532         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1533         struct rk3399_sdram_params *params =
1534                                         (void *)dtplat->rockchip_sdram_params;
1535
1536         ret = conv_of_platdata(dev);
1537         if (ret)
1538                 return ret;
1539 #endif
1540
1541         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1542         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1543         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1544         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1545         priv->pmucru = rockchip_get_pmucru();
1546         priv->cru = rockchip_get_cru();
1547         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1548         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1549         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1550         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1551         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1552         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1553         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1554         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1555
1556         debug("con reg %p %p %p %p %p %p %p %p\n",
1557               priv->chan[0].pctl, priv->chan[0].pi,
1558               priv->chan[0].publ, priv->chan[0].msch,
1559               priv->chan[1].pctl, priv->chan[1].pi,
1560               priv->chan[1].publ, priv->chan[1].msch);
1561         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1562               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1563
1564 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1565         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1566 #else
1567         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1568 #endif
1569         if (ret) {
1570                 printf("%s clk get failed %d\n", __func__, ret);
1571                 return ret;
1572         }
1573
1574         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1575         if (ret < 0) {
1576                 printf("%s clk set failed %d\n", __func__, ret);
1577                 return ret;
1578         }
1579
1580         ret = sdram_init(priv, params);
1581         if (ret < 0) {
1582                 printf("%s DRAM init failed %d\n", __func__, ret);
1583                 return ret;
1584         }
1585
1586         return 0;
1587 }
1588 #endif
1589
1590 static int rk3399_dmc_probe(struct udevice *dev)
1591 {
1592 #if defined(CONFIG_TPL_BUILD) || \
1593         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1594         if (rk3399_dmc_init(dev))
1595                 return 0;
1596 #else
1597         struct dram_info *priv = dev_get_priv(dev);
1598
1599         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1600         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1601         priv->info.base = CONFIG_SYS_SDRAM_BASE;
1602         priv->info.size =
1603                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1604 #endif
1605         return 0;
1606 }
1607
1608 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1609 {
1610         struct dram_info *priv = dev_get_priv(dev);
1611
1612         *info = priv->info;
1613
1614         return 0;
1615 }
1616
1617 static struct ram_ops rk3399_dmc_ops = {
1618         .get_info = rk3399_dmc_get_info,
1619 };
1620
1621 static const struct udevice_id rk3399_dmc_ids[] = {
1622         { .compatible = "rockchip,rk3399-dmc" },
1623         { }
1624 };
1625
1626 U_BOOT_DRIVER(dmc_rk3399) = {
1627         .name = "rockchip_rk3399_dmc",
1628         .id = UCLASS_RAM,
1629         .of_match = rk3399_dmc_ids,
1630         .ops = &rk3399_dmc_ops,
1631 #if defined(CONFIG_TPL_BUILD) || \
1632         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1633         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1634 #endif
1635         .probe = rk3399_dmc_probe,
1636         .priv_auto_alloc_size = sizeof(struct dram_info),
1637 #if defined(CONFIG_TPL_BUILD) || \
1638         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1639         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1640 #endif
1641 };