1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * (C) Copyright 2016-2017 Rockchip Inc.
5 * Adapted from coreboot.
11 #include <dt-structs.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/cru_rk3399.h>
18 #include <asm/arch-rockchip/grf_rk3399.h>
19 #include <asm/arch-rockchip/pmu_rk3399.h>
20 #include <asm/arch-rockchip/hardware.h>
21 #include <asm/arch-rockchip/sdram.h>
22 #include <asm/arch-rockchip/sdram_rk3399.h>
23 #include <linux/err.h>
26 #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
27 #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
28 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
30 #define PHY_DRV_ODT_HI_Z 0x0
31 #define PHY_DRV_ODT_240 0x1
32 #define PHY_DRV_ODT_120 0x8
33 #define PHY_DRV_ODT_80 0x9
34 #define PHY_DRV_ODT_60 0xc
35 #define PHY_DRV_ODT_48 0xd
36 #define PHY_DRV_ODT_40 0xe
37 #define PHY_DRV_ODT_34_3 0xf
39 #define PHY_BOOSTP_EN 0x1
40 #define PHY_BOOSTN_EN 0x1
41 #define PHY_SLEWP_EN 0x1
42 #define PHY_SLEWN_EN 0x1
43 #define PHY_RX_CM_INPUT 0x1
44 #define CS0_MR22_VAL 0
45 #define CS1_MR22_VAL 3
47 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
48 ((n) << (8 + (ch) * 4)))
49 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
50 ((n) << (9 + (ch) * 4)))
52 struct rk3399_ddr_pctl_regs *pctl;
53 struct rk3399_ddr_pi_regs *pi;
54 struct rk3399_ddr_publ_regs *publ;
55 struct msch_regs *msch;
59 #if defined(CONFIG_TPL_BUILD) || \
60 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
61 u32 pwrup_srefresh_exit[2];
62 struct chan_info chan[2];
64 struct rk3399_cru *cru;
65 struct rk3399_grf_regs *grf;
66 struct rk3399_pmu_regs *pmu;
67 struct rk3399_pmucru *pmucru;
68 struct rk3399_pmusgrf_regs *pmusgrf;
69 struct rk3399_ddr_cic_regs *cic;
70 const struct sdram_rk3399_ops *ops;
73 struct rk3399_pmugrf_regs *pmugrf;
76 struct sdram_rk3399_ops {
77 int (*data_training)(struct dram_info *dram, u32 channel, u8 rank,
78 struct rk3399_sdram_params *sdram);
79 int (*set_rate)(struct dram_info *dram,
80 struct rk3399_sdram_params *params);
83 #if defined(CONFIG_TPL_BUILD) || \
84 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
86 struct rockchip_dmc_plat {
87 #if CONFIG_IS_ENABLED(OF_PLATDATA)
88 struct dtd_rockchip_rk3399_dmc dtplat;
90 struct rk3399_sdram_params sdram_params;
111 } lpddr4_io_setting[] = {
122 PHY_DRV_ODT_HI_Z, /* rd_odt; */
123 PHY_DRV_ODT_40, /* wr_dq_drv; */
124 PHY_DRV_ODT_40, /* wr_ca_drv; */
125 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
127 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */
139 PHY_DRV_ODT_HI_Z, /* rd_odt; */
140 PHY_DRV_ODT_48, /* wr_dq_drv; */
141 PHY_DRV_ODT_40, /* wr_ca_drv; */
142 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
144 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */
156 PHY_DRV_ODT_40, /* rd_odt; */
157 PHY_DRV_ODT_48, /* wr_dq_drv; */
158 PHY_DRV_ODT_40, /* wr_ca_drv; */
159 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
161 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */
170 0x59, /* dq_vref; 32% */
173 PHY_DRV_ODT_HI_Z, /* rd_odt; */
174 PHY_DRV_ODT_48, /* wr_dq_drv; */
175 PHY_DRV_ODT_40, /* wr_ca_drv; */
176 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
178 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */
190 PHY_DRV_ODT_40, /* rd_odt; */
191 PHY_DRV_ODT_60, /* wr_dq_drv; */
192 PHY_DRV_ODT_40, /* wr_ca_drv; */
193 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
195 17, /* rd_vref; (unit %, range 3.3% - 48.7%) */
199 static struct io_setting *
200 lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
202 struct io_setting *io = NULL;
205 for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
206 io = &lpddr4_io_setting[n];
209 if (io->mhz >= params->base.ddr_freq &&
213 if (io->mhz >= params->base.ddr_freq)
221 static void *get_denali_ctl(const struct chan_info *chan,
222 struct rk3399_sdram_params *params, bool reg)
224 return reg ? &chan->pctl->denali_ctl : ¶ms->pctl_regs.denali_ctl;
227 static void *get_denali_phy(const struct chan_info *chan,
228 struct rk3399_sdram_params *params, bool reg)
230 return reg ? &chan->publ->denali_phy : ¶ms->phy_regs.denali_phy;
233 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
235 return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
238 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
244 writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
245 CRU_SFTRST_DDR_PHY(channel, phy),
246 &cru->softrst_con[4]);
249 static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
251 rkclk_ddr_reset(cru, channel, 1, 1);
254 rkclk_ddr_reset(cru, channel, 1, 0);
257 rkclk_ddr_reset(cru, channel, 0, 0);
261 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
264 u32 *denali_phy = ddr_publ_regs->denali_phy;
266 /* From IP spec, only freq small than 125 can enter dll bypass mode */
268 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
269 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
270 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
271 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
272 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
274 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
275 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
276 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
277 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
279 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
280 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
281 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
282 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
283 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
285 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
286 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
287 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
288 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
292 static void set_memory_map(const struct chan_info *chan, u32 channel,
293 const struct rk3399_sdram_params *params)
295 const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel];
296 u32 *denali_ctl = chan->pctl->denali_ctl;
297 u32 *denali_pi = chan->pi->denali_pi;
302 /* Get row number from ddrconfig setting */
303 if (sdram_ch->cap_info.ddrconfig < 2 ||
304 sdram_ch->cap_info.ddrconfig == 4)
306 else if (sdram_ch->cap_info.ddrconfig == 3)
311 cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
312 reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
314 /* Set the dram configuration to ctrl */
315 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
316 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
317 ((3 - sdram_ch->cap_info.bk) << 16) |
320 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
321 cs_map | (reduc << 16));
323 /* PI_199 PI_COL_DIFF:RW:0:4 */
324 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
326 /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
327 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
328 ((3 - sdram_ch->cap_info.bk) << 16) |
331 if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
334 else if (cs_map == 2)
340 /* PI_41 PI_CS_MAP:RW:24:4 */
341 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
342 if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
343 writel(0x2EC7FFFF, &denali_pi[34]);
346 static int phy_io_config(const struct chan_info *chan,
347 const struct rk3399_sdram_params *params, u32 mr5)
349 u32 *denali_phy = chan->publ->denali_phy;
350 u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
353 u32 drv_value, odt_value;
356 /* vref setting & mode setting */
357 if (params->base.dramtype == LPDDR4) {
358 struct io_setting *io = lpddr4_get_io_settings(params, mr5);
359 u32 rd_vref = io->rd_vref * 1000;
361 if (rd_vref < 36700) {
362 /* MODE_LV[2:0] = LPDDR4 (Range 2)*/
364 /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
366 vref_value_dq = (rd_vref - 3300) / 521;
368 /* MODE_LV[2:0] = LPDDR4 (Range 1)*/
370 /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
372 vref_value_dq = (rd_vref - 15300) / 521;
377 } else if (params->base.dramtype == LPDDR3) {
378 if (params->base.odt == 1) {
379 vref_mode_dq = 0x5; /* LPDDR3 ODT */
380 drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
381 odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
382 if (drv_value == PHY_DRV_ODT_48) {
384 case PHY_DRV_ODT_240:
385 vref_value_dq = 0x16;
387 case PHY_DRV_ODT_120:
388 vref_value_dq = 0x26;
391 vref_value_dq = 0x36;
394 debug("Invalid ODT value.\n");
397 } else if (drv_value == PHY_DRV_ODT_40) {
399 case PHY_DRV_ODT_240:
400 vref_value_dq = 0x19;
402 case PHY_DRV_ODT_120:
403 vref_value_dq = 0x23;
406 vref_value_dq = 0x31;
409 debug("Invalid ODT value.\n");
412 } else if (drv_value == PHY_DRV_ODT_34_3) {
414 case PHY_DRV_ODT_240:
415 vref_value_dq = 0x17;
417 case PHY_DRV_ODT_120:
418 vref_value_dq = 0x20;
421 vref_value_dq = 0x2e;
424 debug("Invalid ODT value.\n");
428 debug("Invalid DRV value.\n");
432 vref_mode_dq = 0x2; /* LPDDR3 */
433 vref_value_dq = 0x1f;
436 vref_value_ac = 0x1f;
438 } else if (params->base.dramtype == DDR3) {
441 vref_value_dq = 0x1f;
443 vref_value_ac = 0x1f;
446 debug("Unknown DRAM type.\n");
450 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
452 /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
453 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
454 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
455 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
456 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
457 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
458 /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
459 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
461 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
463 /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
464 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
466 /* PHY_924 PHY_PAD_FDBK_DRIVE */
467 clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
468 /* PHY_926 PHY_PAD_DATA_DRIVE */
469 clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
470 /* PHY_927 PHY_PAD_DQS_DRIVE */
471 clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
472 /* PHY_928 PHY_PAD_ADDR_DRIVE */
473 clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
474 /* PHY_929 PHY_PAD_CLK_DRIVE */
475 clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
476 /* PHY_935 PHY_PAD_CKE_DRIVE */
477 clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
478 /* PHY_937 PHY_PAD_RST_DRIVE */
479 clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
480 /* PHY_939 PHY_PAD_CS_DRIVE */
481 clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
483 if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
484 /* BOOSTP_EN & BOOSTN_EN */
485 reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
486 /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
487 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
488 /* PHY_926 PHY_PAD_DATA_DRIVE */
489 clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
490 /* PHY_927 PHY_PAD_DQS_DRIVE */
491 clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
492 /* PHY_928 PHY_PAD_ADDR_DRIVE */
493 clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
494 /* PHY_929 PHY_PAD_CLK_DRIVE */
495 clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
496 /* PHY_935 PHY_PAD_CKE_DRIVE */
497 clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
498 /* PHY_937 PHY_PAD_RST_DRIVE */
499 clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
500 /* PHY_939 PHY_PAD_CS_DRIVE */
501 clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
503 /* SLEWP_EN & SLEWN_EN */
504 reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
505 /* PHY_924 PHY_PAD_FDBK_DRIVE */
506 clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
507 /* PHY_926 PHY_PAD_DATA_DRIVE */
508 clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
509 /* PHY_927 PHY_PAD_DQS_DRIVE */
510 clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
511 /* PHY_928 PHY_PAD_ADDR_DRIVE */
512 clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
513 /* PHY_929 PHY_PAD_CLK_DRIVE */
514 clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
515 /* PHY_935 PHY_PAD_CKE_DRIVE */
516 clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
517 /* PHY_937 PHY_PAD_RST_DRIVE */
518 clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
519 /* PHY_939 PHY_PAD_CS_DRIVE */
520 clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
524 if (params->base.ddr_freq < 400)
526 else if (params->base.ddr_freq < 800)
528 else if (params->base.ddr_freq < 1200)
533 /* PHY_924 PHY_PAD_FDBK_DRIVE */
534 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
535 /* PHY_926 PHY_PAD_DATA_DRIVE */
536 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
537 /* PHY_927 PHY_PAD_DQS_DRIVE */
538 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
539 /* PHY_928 PHY_PAD_ADDR_DRIVE */
540 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
541 /* PHY_929 PHY_PAD_CLK_DRIVE */
542 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
543 /* PHY_935 PHY_PAD_CKE_DRIVE */
544 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
545 /* PHY_937 PHY_PAD_RST_DRIVE */
546 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
547 /* PHY_939 PHY_PAD_CS_DRIVE */
548 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
550 if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
552 reg_value = PHY_RX_CM_INPUT;
553 /* PHY_924 PHY_PAD_FDBK_DRIVE */
554 clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
555 /* PHY_926 PHY_PAD_DATA_DRIVE */
556 clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
557 /* PHY_927 PHY_PAD_DQS_DRIVE */
558 clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
559 /* PHY_928 PHY_PAD_ADDR_DRIVE */
560 clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
561 /* PHY_929 PHY_PAD_CLK_DRIVE */
562 clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
563 /* PHY_935 PHY_PAD_CKE_DRIVE */
564 clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
565 /* PHY_937 PHY_PAD_RST_DRIVE */
566 clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
567 /* PHY_939 PHY_PAD_CS_DRIVE */
568 clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
574 static void set_ds_odt(const struct chan_info *chan,
575 struct rk3399_sdram_params *params,
576 bool ctl_phy_reg, u32 mr5)
578 u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg);
579 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
580 u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
581 u32 tsel_idle_select_p, tsel_rd_select_p;
582 u32 tsel_idle_select_n, tsel_rd_select_n;
583 u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
584 u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
585 u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
586 struct io_setting *io = NULL;
590 if (params->base.dramtype == LPDDR4) {
591 io = lpddr4_get_io_settings(params, mr5);
593 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
594 tsel_rd_select_n = io->rd_odt;
596 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
597 tsel_idle_select_n = PHY_DRV_ODT_240;
599 tsel_wr_select_dq_p = io->wr_dq_drv;
600 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
602 tsel_wr_select_ca_p = io->wr_ca_drv;
603 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
605 tsel_ckcs_select_p = io->wr_ckcs_drv;
606 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
607 switch (tsel_rd_select_n) {
608 case PHY_DRV_ODT_240:
611 case PHY_DRV_ODT_120:
626 case PHY_DRV_ODT_34_3:
628 printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
631 case PHY_DRV_ODT_HI_Z:
636 } else if (params->base.dramtype == LPDDR3) {
637 tsel_rd_select_p = PHY_DRV_ODT_240;
638 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
640 tsel_idle_select_p = PHY_DRV_ODT_240;
641 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
643 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
644 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
646 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
647 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
649 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
650 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
652 tsel_rd_select_p = PHY_DRV_ODT_240;
653 tsel_rd_select_n = PHY_DRV_ODT_240;
655 tsel_idle_select_p = PHY_DRV_ODT_240;
656 tsel_idle_select_n = PHY_DRV_ODT_240;
658 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
659 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
661 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
662 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
664 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
665 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
668 if (params->base.odt == 1) {
671 if (params->base.dramtype == LPDDR4)
672 tsel_rd_en = io->rd_odt_en;
681 clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
682 (soc_odt | (CS0_MR22_VAL << 3)) << 16);
684 clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
685 ((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
686 (soc_odt | (CS0_MR22_VAL << 3)));
688 clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
689 (soc_odt | (CS1_MR22_VAL << 3)) << 16);
691 clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
692 ((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
693 (soc_odt | (CS1_MR22_VAL << 3)));
696 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
697 * sets termination values for read/idle cycles and drive strength
698 * for write cycles for DQ/DM
700 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
701 (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
702 (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
703 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
704 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
705 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
706 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
709 * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
710 * sets termination values for read/idle cycles and drive strength
711 * for write cycles for DQS
713 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
714 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
715 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
716 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
718 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
719 reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
720 if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
721 /* LPDDR4 these register read always return 0, so
722 * can not use clrsetbits_le32(), need to write32
724 writel((0x300 << 8) | reg_value, &denali_phy[544]);
725 writel((0x300 << 8) | reg_value, &denali_phy[672]);
726 writel((0x300 << 8) | reg_value, &denali_phy[800]);
728 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
729 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
730 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
733 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
734 clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
736 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
738 clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
740 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
741 clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
743 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
744 clrsetbits_le32(&denali_phy[939], 0xff,
745 tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
747 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
748 clrsetbits_le32(&denali_phy[929], 0xff,
749 tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
751 /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
752 clrsetbits_le32(&denali_phy[924], 0xff,
753 tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
754 clrsetbits_le32(&denali_phy[925], 0xff,
755 tsel_rd_select_n | (tsel_rd_select_p << 4));
757 /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
758 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
760 clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
761 clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
762 clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
763 clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
765 /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
766 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
768 clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
769 clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
770 clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
771 clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
773 /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
774 reg_value = tsel_wr_en << 8;
775 clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
776 clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
777 clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
779 /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
780 reg_value = tsel_wr_en << 17;
781 clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
783 * pad_rst/cke/cs/clk_term tsel 1bits
784 * DENALI_PHY_938/936/940/934 offset_17
786 clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
787 clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
788 clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
789 clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
791 /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
792 clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
794 phy_io_config(chan, params, mr5);
797 static void pctl_start(struct dram_info *dram, u8 channel)
799 const struct chan_info *chan = &dram->chan[channel];
800 u32 *denali_ctl = chan->pctl->denali_ctl;
801 u32 *denali_phy = chan->publ->denali_phy;
802 u32 *ddrc0_con = get_ddrc0_con(dram, channel);
806 writel(0x01000000, &ddrc0_con);
808 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
810 while (!(readl(&denali_ctl[203]) & (1 << 3))) {
812 printf("%s: Failed to init pctl for channel %d\n",
822 writel(0x01000100, &ddrc0_con);
824 for (byte = 0; byte < 4; byte++) {
826 writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
827 writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
828 writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
829 writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
830 writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
832 clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
835 clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
836 dram->pwrup_srefresh_exit[channel]);
839 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
840 u32 channel, struct rk3399_sdram_params *params)
842 u32 *denali_ctl = chan->pctl->denali_ctl;
843 u32 *denali_pi = chan->pi->denali_pi;
844 u32 *denali_phy = chan->publ->denali_phy;
845 const u32 *params_ctl = params->pctl_regs.denali_ctl;
846 const u32 *params_phy = params->phy_regs.denali_phy;
850 * work around controller bug:
851 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
853 sdram_copy_to_reg(&denali_ctl[1], ¶ms_ctl[1],
854 sizeof(struct rk3399_ddr_pctl_regs) - 4);
855 writel(params_ctl[0], &denali_ctl[0]);
858 * two channel init at the same time, then ZQ Cal Start
859 * at the same time, it will use the same RZQ, but cannot
860 * start at the same time.
862 * So, increase tINIT3 for channel 1, will avoid two
863 * channel ZQ Cal Start at the same time
865 if (params->base.dramtype == LPDDR4 && channel == 1) {
866 tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
867 tmp1 = readl(&denali_ctl[14]);
868 writel(tmp + tmp1, &denali_ctl[14]);
871 sdram_copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0],
872 sizeof(struct rk3399_ddr_pi_regs));
874 /* rank count need to set for init */
875 set_memory_map(chan, channel, params);
877 writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
878 writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
879 writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
881 if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
882 writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
883 writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
886 dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
888 clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
891 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
893 setbits_le32(&denali_pi[0], START);
894 setbits_le32(&denali_ctl[0], START);
897 * LPDDR4 use PLL bypass mode for init
898 * not need to wait for the PLL to lock
900 if (params->base.dramtype != LPDDR4) {
901 /* Waiting for phy DLL lock */
903 tmp = readl(&denali_phy[920]);
904 tmp1 = readl(&denali_phy[921]);
905 tmp2 = readl(&denali_phy[922]);
906 if ((((tmp >> 16) & 0x1) == 0x1) &&
907 (((tmp1 >> 16) & 0x1) == 0x1) &&
908 (((tmp1 >> 0) & 0x1) == 0x1) &&
909 (((tmp2 >> 0) & 0x1) == 0x1))
914 sdram_copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4);
915 sdram_copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4);
916 sdram_copy_to_reg(&denali_phy[128], ¶ms_phy[128],
917 (218 - 128 + 1) * 4);
918 sdram_copy_to_reg(&denali_phy[256], ¶ms_phy[256],
919 (346 - 256 + 1) * 4);
920 sdram_copy_to_reg(&denali_phy[384], ¶ms_phy[384],
921 (474 - 384 + 1) * 4);
922 sdram_copy_to_reg(&denali_phy[512], ¶ms_phy[512],
923 (549 - 512 + 1) * 4);
924 sdram_copy_to_reg(&denali_phy[640], ¶ms_phy[640],
925 (677 - 640 + 1) * 4);
926 sdram_copy_to_reg(&denali_phy[768], ¶ms_phy[768],
927 (805 - 768 + 1) * 4);
929 set_ds_odt(chan, params, true, 0);
932 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
933 * dqs_tsel_wr_end[7:4] add Half cycle
935 tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
936 clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
937 tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
938 clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
939 tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
940 clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
941 tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
942 clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
945 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
946 * dq_tsel_wr_end[7:4] add Half cycle
948 tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
949 clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
950 tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
951 clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
952 tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
953 clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
954 tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
955 clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
960 static void select_per_cs_training_index(const struct chan_info *chan,
963 u32 *denali_phy = chan->publ->denali_phy;
965 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
966 if ((readl(&denali_phy[84]) >> 16) & 1) {
969 * phy_per_cs_training_index_X 1bit offset_24
971 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
972 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
973 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
974 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
978 static void override_write_leveling_value(const struct chan_info *chan)
980 u32 *denali_ctl = chan->pctl->denali_ctl;
981 u32 *denali_phy = chan->publ->denali_phy;
984 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
985 setbits_le32(&denali_phy[896], 1);
989 * phy_per_cs_training_multicast_en_X 1bit offset_16
991 clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
992 clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
993 clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
994 clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
996 for (byte = 0; byte < 4; byte++)
997 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
1000 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
1001 clrbits_le32(&denali_phy[896], 1);
1003 /* CTL_200 ctrlupd_req 1bit offset_8 */
1004 clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
1007 static int data_training_ca(const struct chan_info *chan, u32 channel,
1008 const struct rk3399_sdram_params *params)
1010 u32 *denali_pi = chan->pi->denali_pi;
1011 u32 *denali_phy = chan->publ->denali_phy;
1013 u32 obs_0, obs_1, obs_2, obs_err = 0;
1014 u32 rank = params->ch[channel].cap_info.rank;
1017 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1018 writel(0x00003f7c, (&denali_pi[175]));
1020 if (params->base.dramtype == LPDDR4)
1021 rank_mask = (rank == 1) ? 0x5 : 0xf;
1023 rank_mask = (rank == 1) ? 0x1 : 0x3;
1025 for (i = 0; i < 4; i++) {
1026 if (!(rank_mask & (1 << i)))
1029 select_per_cs_training_index(chan, i);
1031 /* PI_100 PI_CALVL_EN:RW:8:2 */
1032 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
1034 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
1035 clrsetbits_le32(&denali_pi[92],
1036 (0x1 << 16) | (0x3 << 24),
1037 (0x1 << 16) | (i << 24));
1039 /* Waiting for training complete */
1041 /* PI_174 PI_INT_STATUS:RD:8:18 */
1042 tmp = readl(&denali_pi[174]) >> 8;
1045 * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
1047 obs_0 = readl(&denali_phy[532]);
1048 obs_1 = readl(&denali_phy[660]);
1049 obs_2 = readl(&denali_phy[788]);
1050 if (((obs_0 >> 30) & 0x3) ||
1051 ((obs_1 >> 30) & 0x3) ||
1052 ((obs_2 >> 30) & 0x3))
1054 if ((((tmp >> 11) & 0x1) == 0x1) &&
1055 (((tmp >> 13) & 0x1) == 0x1) &&
1056 (((tmp >> 5) & 0x1) == 0x0) &&
1059 else if ((((tmp >> 5) & 0x1) == 0x1) ||
1064 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1065 writel(0x00003f7c, (&denali_pi[175]));
1068 clrbits_le32(&denali_pi[100], 0x3 << 8);
1073 static int data_training_wl(const struct chan_info *chan, u32 channel,
1074 const struct rk3399_sdram_params *params)
1076 u32 *denali_pi = chan->pi->denali_pi;
1077 u32 *denali_phy = chan->publ->denali_phy;
1079 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1080 u32 rank = params->ch[channel].cap_info.rank;
1082 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1083 writel(0x00003f7c, (&denali_pi[175]));
1085 for (i = 0; i < rank; i++) {
1086 select_per_cs_training_index(chan, i);
1088 /* PI_60 PI_WRLVL_EN:RW:8:2 */
1089 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
1091 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
1092 clrsetbits_le32(&denali_pi[59],
1093 (0x1 << 8) | (0x3 << 16),
1094 (0x1 << 8) | (i << 16));
1096 /* Waiting for training complete */
1098 /* PI_174 PI_INT_STATUS:RD:8:18 */
1099 tmp = readl(&denali_pi[174]) >> 8;
1102 * check status obs, if error maybe can not
1103 * get leveling done PHY_40/168/296/424
1104 * phy_wrlvl_status_obs_X:0:13
1106 obs_0 = readl(&denali_phy[40]);
1107 obs_1 = readl(&denali_phy[168]);
1108 obs_2 = readl(&denali_phy[296]);
1109 obs_3 = readl(&denali_phy[424]);
1110 if (((obs_0 >> 12) & 0x1) ||
1111 ((obs_1 >> 12) & 0x1) ||
1112 ((obs_2 >> 12) & 0x1) ||
1113 ((obs_3 >> 12) & 0x1))
1115 if ((((tmp >> 10) & 0x1) == 0x1) &&
1116 (((tmp >> 13) & 0x1) == 0x1) &&
1117 (((tmp >> 4) & 0x1) == 0x0) &&
1120 else if ((((tmp >> 4) & 0x1) == 0x1) ||
1125 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1126 writel(0x00003f7c, (&denali_pi[175]));
1129 override_write_leveling_value(chan);
1130 clrbits_le32(&denali_pi[60], 0x3 << 8);
1135 static int data_training_rg(const struct chan_info *chan, u32 channel,
1136 const struct rk3399_sdram_params *params)
1138 u32 *denali_pi = chan->pi->denali_pi;
1139 u32 *denali_phy = chan->publ->denali_phy;
1141 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1142 u32 rank = params->ch[channel].cap_info.rank;
1144 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1145 writel(0x00003f7c, (&denali_pi[175]));
1147 for (i = 0; i < rank; i++) {
1148 select_per_cs_training_index(chan, i);
1150 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
1151 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
1154 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
1155 * PI_RDLVL_CS:RW:24:2
1157 clrsetbits_le32(&denali_pi[74],
1158 (0x1 << 16) | (0x3 << 24),
1159 (0x1 << 16) | (i << 24));
1161 /* Waiting for training complete */
1163 /* PI_174 PI_INT_STATUS:RD:8:18 */
1164 tmp = readl(&denali_pi[174]) >> 8;
1168 * PHY_43/171/299/427
1169 * PHY_GTLVL_STATUS_OBS_x:16:8
1171 obs_0 = readl(&denali_phy[43]);
1172 obs_1 = readl(&denali_phy[171]);
1173 obs_2 = readl(&denali_phy[299]);
1174 obs_3 = readl(&denali_phy[427]);
1175 if (((obs_0 >> (16 + 6)) & 0x3) ||
1176 ((obs_1 >> (16 + 6)) & 0x3) ||
1177 ((obs_2 >> (16 + 6)) & 0x3) ||
1178 ((obs_3 >> (16 + 6)) & 0x3))
1180 if ((((tmp >> 9) & 0x1) == 0x1) &&
1181 (((tmp >> 13) & 0x1) == 0x1) &&
1182 (((tmp >> 3) & 0x1) == 0x0) &&
1185 else if ((((tmp >> 3) & 0x1) == 0x1) ||
1190 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1191 writel(0x00003f7c, (&denali_pi[175]));
1194 clrbits_le32(&denali_pi[80], 0x3 << 24);
1199 static int data_training_rl(const struct chan_info *chan, u32 channel,
1200 const struct rk3399_sdram_params *params)
1202 u32 *denali_pi = chan->pi->denali_pi;
1204 u32 rank = params->ch[channel].cap_info.rank;
1206 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1207 writel(0x00003f7c, (&denali_pi[175]));
1209 for (i = 0; i < rank; i++) {
1210 select_per_cs_training_index(chan, i);
1212 /* PI_80 PI_RDLVL_EN:RW:16:2 */
1213 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
1215 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
1216 clrsetbits_le32(&denali_pi[74],
1217 (0x1 << 8) | (0x3 << 24),
1218 (0x1 << 8) | (i << 24));
1220 /* Waiting for training complete */
1222 /* PI_174 PI_INT_STATUS:RD:8:18 */
1223 tmp = readl(&denali_pi[174]) >> 8;
1226 * make sure status obs not report error bit
1227 * PHY_46/174/302/430
1228 * phy_rdlvl_status_obs_X:16:8
1230 if ((((tmp >> 8) & 0x1) == 0x1) &&
1231 (((tmp >> 13) & 0x1) == 0x1) &&
1232 (((tmp >> 2) & 0x1) == 0x0))
1234 else if (((tmp >> 2) & 0x1) == 0x1)
1238 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1239 writel(0x00003f7c, (&denali_pi[175]));
1242 clrbits_le32(&denali_pi[80], 0x3 << 16);
1247 static int data_training_wdql(const struct chan_info *chan, u32 channel,
1248 const struct rk3399_sdram_params *params)
1250 u32 *denali_pi = chan->pi->denali_pi;
1252 u32 rank = params->ch[channel].cap_info.rank;
1255 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1256 writel(0x00003f7c, (&denali_pi[175]));
1258 if (params->base.dramtype == LPDDR4)
1259 rank_mask = (rank == 1) ? 0x5 : 0xf;
1261 rank_mask = (rank == 1) ? 0x1 : 0x3;
1263 for (i = 0; i < 4; i++) {
1264 if (!(rank_mask & (1 << i)))
1267 select_per_cs_training_index(chan, i);
1270 * disable PI_WDQLVL_VREF_EN before wdq leveling?
1271 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
1273 clrbits_le32(&denali_pi[181], 0x1 << 8);
1275 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
1276 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
1278 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
1279 clrsetbits_le32(&denali_pi[121],
1280 (0x1 << 8) | (0x3 << 16),
1281 (0x1 << 8) | (i << 16));
1283 /* Waiting for training complete */
1285 /* PI_174 PI_INT_STATUS:RD:8:18 */
1286 tmp = readl(&denali_pi[174]) >> 8;
1287 if ((((tmp >> 12) & 0x1) == 0x1) &&
1288 (((tmp >> 13) & 0x1) == 0x1) &&
1289 (((tmp >> 6) & 0x1) == 0x0))
1291 else if (((tmp >> 6) & 0x1) == 0x1)
1295 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1296 writel(0x00003f7c, (&denali_pi[175]));
1299 clrbits_le32(&denali_pi[124], 0x3 << 16);
1304 static int data_training(struct dram_info *dram, u32 channel,
1305 const struct rk3399_sdram_params *params,
1308 struct chan_info *chan = &dram->chan[channel];
1309 u32 *denali_phy = chan->publ->denali_phy;
1312 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
1313 setbits_le32(&denali_phy[927], (1 << 22));
1315 if (training_flag == PI_FULL_TRAINING) {
1316 if (params->base.dramtype == LPDDR4) {
1317 training_flag = PI_WRITE_LEVELING |
1318 PI_READ_GATE_TRAINING |
1319 PI_READ_LEVELING | PI_WDQ_LEVELING;
1320 } else if (params->base.dramtype == LPDDR3) {
1321 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1322 PI_READ_GATE_TRAINING;
1323 } else if (params->base.dramtype == DDR3) {
1324 training_flag = PI_WRITE_LEVELING |
1325 PI_READ_GATE_TRAINING |
1330 /* ca training(LPDDR4,LPDDR3 support) */
1331 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
1332 ret = data_training_ca(chan, channel, params);
1334 debug("%s: data training ca failed\n", __func__);
1339 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1340 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
1341 ret = data_training_wl(chan, channel, params);
1343 debug("%s: data training wl failed\n", __func__);
1348 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1349 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
1350 ret = data_training_rg(chan, channel, params);
1352 debug("%s: data training rg failed\n", __func__);
1357 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1358 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
1359 ret = data_training_rl(chan, channel, params);
1361 debug("%s: data training rl failed\n", __func__);
1366 /* wdq leveling(LPDDR4 support) */
1367 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1368 ret = data_training_wdql(chan, channel, params);
1370 debug("%s: data training wdql failed\n", __func__);
1375 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
1376 clrbits_le32(&denali_phy[927], (1 << 22));
1381 static void set_ddrconfig(const struct chan_info *chan,
1382 const struct rk3399_sdram_params *params,
1383 unsigned char channel, u32 ddrconfig)
1385 /* only need to set ddrconfig */
1386 struct msch_regs *ddr_msch_regs = chan->msch;
1387 unsigned int cs0_cap = 0;
1388 unsigned int cs1_cap = 0;
1390 cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1391 + params->ch[channel].cap_info.col
1392 + params->ch[channel].cap_info.bk
1393 + params->ch[channel].cap_info.bw - 20));
1394 if (params->ch[channel].cap_info.rank > 1)
1395 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1396 - params->ch[channel].cap_info.cs1_row);
1397 if (params->ch[channel].cap_info.row_3_4) {
1398 cs0_cap = cs0_cap * 3 / 4;
1399 cs1_cap = cs1_cap * 3 / 4;
1402 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1403 writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1404 &ddr_msch_regs->ddrsize);
1407 static void sdram_msch_config(struct msch_regs *msch,
1408 struct sdram_msch_timings *noc_timings)
1410 writel(noc_timings->ddrtiminga0.d32,
1411 &msch->ddrtiminga0.d32);
1412 writel(noc_timings->ddrtimingb0.d32,
1413 &msch->ddrtimingb0.d32);
1414 writel(noc_timings->ddrtimingc0.d32,
1415 &msch->ddrtimingc0.d32);
1416 writel(noc_timings->devtodev0.d32,
1417 &msch->devtodev0.d32);
1418 writel(noc_timings->ddrmode.d32,
1419 &msch->ddrmode.d32);
1422 static void dram_all_config(struct dram_info *dram,
1423 struct rk3399_sdram_params *params)
1427 unsigned int channel, idx;
1429 for (channel = 0, idx = 0;
1430 (idx < params->base.num_channels) && (channel < 2);
1432 struct msch_regs *ddr_msch_regs;
1433 struct sdram_msch_timings *noc_timing;
1435 if (params->ch[channel].cap_info.col == 0)
1438 sdram_org_config(¶ms->ch[channel].cap_info,
1439 ¶ms->base, &sys_reg2,
1440 &sys_reg3, channel);
1441 ddr_msch_regs = dram->chan[channel].msch;
1442 noc_timing = ¶ms->ch[channel].noc_timings;
1443 sdram_msch_config(ddr_msch_regs, noc_timing);
1446 * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
1448 * The hardware for LPDDR4 with
1449 * - CLK0P/N connect to lower 16-bits
1450 * - CLK1P/N connect to higher 16-bits
1452 * dfi dram clk is configured via CLK1P/N, so disabling
1453 * dfi dram clk will disable the CLK1P/N as well for lpddr4.
1455 if (params->ch[channel].cap_info.rank == 1 &&
1456 params->base.dramtype != LPDDR4)
1457 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1461 writel(sys_reg2, &dram->pmugrf->os_reg2);
1462 writel(sys_reg3, &dram->pmugrf->os_reg3);
1463 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1464 params->base.stride << 10);
1466 /* reboot hold register set */
1467 writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1468 PRESET_GPIO1_HOLD(1),
1469 &dram->pmucru->pmucru_rstnhold_con[1]);
1470 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1473 static void set_cap_relate_config(const struct chan_info *chan,
1474 struct rk3399_sdram_params *params,
1475 unsigned int channel)
1477 u32 *denali_ctl = chan->pctl->denali_ctl;
1479 struct sdram_msch_timings *noc_timing;
1481 if (params->base.dramtype == LPDDR3) {
1482 tmp = (8 << params->ch[channel].cap_info.bw) /
1483 (8 << params->ch[channel].cap_info.dbw);
1487 * 1 -> 0, 2 -> 1, 4 -> 2
1489 clrsetbits_le32(&denali_ctl[197], 0x7,
1491 clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
1495 noc_timing = ¶ms->ch[channel].noc_timings;
1498 * noc timing bw relate timing is 32 bit, and real bw is 16bit
1499 * actually noc reg is setting at function dram_all_config
1501 if (params->ch[channel].cap_info.bw == 16 &&
1502 noc_timing->ddrmode.b.mwrsize == 2) {
1503 if (noc_timing->ddrmode.b.burstsize)
1504 noc_timing->ddrmode.b.burstsize -= 1;
1505 noc_timing->ddrmode.b.mwrsize -= 1;
1506 noc_timing->ddrtimingc0.b.burstpenalty *= 2;
1507 noc_timing->ddrtimingc0.b.wrtomwr *= 2;
1511 static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
1513 unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
1514 unsigned int col = params->ch[channel].cap_info.col;
1515 unsigned int bw = params->ch[channel].cap_info.bw;
1516 u16 ddr_cfg_2_rbc[] = {
1518 * [6] highest bit col
1519 * [5:3] max row(14+n)
1521 * [1:0] col(9+n),col, data bus 32bit
1523 * highbitcol, max_row, insertion_row, col
1525 ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
1526 ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
1527 ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
1528 ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
1529 ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
1530 ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
1531 ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
1532 ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
1536 col -= (bw == 2) ? 0 : 1;
1539 for (i = 0; i < 4; i++) {
1540 if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
1541 (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
1551 #if !defined(CONFIG_RAM_RK3399_LPDDR4)
1552 static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
1553 struct rk3399_sdram_params *params)
1555 u8 training_flag = PI_READ_GATE_TRAINING;
1558 * LPDDR3 CA training msut be trigger before
1560 * DDR3 is not have CA training.
1563 if (params->base.dramtype == LPDDR3)
1564 training_flag |= PI_CA_TRAINING;
1566 return data_training(dram, channel, params, training_flag);
1569 static int switch_to_phy_index1(struct dram_info *dram,
1570 struct rk3399_sdram_params *params)
1574 u32 ch_count = params->base.num_channels;
1578 writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1579 1 << 4 | 1 << 2 | 1),
1580 &dram->cic->cic_ctrl0);
1581 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1585 debug("index1 frequency change overtime\n");
1591 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1592 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1596 debug("index1 frequency done overtime\n");
1601 for (channel = 0; channel < ch_count; channel++) {
1602 denali_phy = dram->chan[channel].publ->denali_phy;
1603 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1604 ret = data_training(dram, channel, params, PI_FULL_TRAINING);
1606 debug("index1 training failed\n");
1616 struct rk3399_sdram_params lpddr4_timings[] = {
1617 #include "sdram-rk3399-lpddr4-400.inc"
1618 #include "sdram-rk3399-lpddr4-800.inc"
1621 static void *get_denali_pi(const struct chan_info *chan,
1622 struct rk3399_sdram_params *params, bool reg)
1624 return reg ? &chan->pi->denali_pi : ¶ms->pi_regs.denali_pi;
1627 static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl)
1629 u32 lpddr4_phy[] = {1, 0, 0xb};
1631 return lpddr4_phy[ctl];
1634 static u32 lpddr4_get_ctl(struct rk3399_sdram_params *params, u32 phy)
1636 u32 lpddr4_ctl[] = {1, 0, 2};
1638 return lpddr4_ctl[phy];
1641 static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
1643 return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
1646 static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
1648 rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
1652 * read mr_num mode register
1656 static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
1657 u32 mr_num, u32 *buf)
1661 writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,
1662 &ddr_pctl_regs->denali_ctl[118]);
1664 while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &
1665 ((1 << 21) | (1 << 12)))) {
1669 printf("%s: pctl timeout!\n", __func__);
1676 if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {
1677 *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;
1679 printf("%s: read mr failed with 0x%x status\n", __func__,
1680 readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);
1684 setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));
1689 static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank,
1690 struct rk3399_sdram_params *params)
1694 u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;
1695 u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;
1696 u32 mr5, mr12, mr14;
1697 struct chan_info *chan = &dram->chan[channel];
1698 struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;
1699 void __iomem *addr = NULL;
1703 stride = get_ddr_stride(dram->pmusgrf);
1705 if (params->ch[channel].cap_info.col == 0) {
1710 cs = params->ch[channel].cap_info.rank;
1711 col = params->ch[channel].cap_info.col;
1712 bk = params->ch[channel].cap_info.bk;
1713 bw = params->ch[channel].cap_info.bw;
1714 row_3_4 = params->ch[channel].cap_info.row_3_4;
1715 cs0_row = params->ch[channel].cap_info.cs0_row;
1716 cs1_row = params->ch[channel].cap_info.cs1_row;
1717 ddrconfig = params->ch[channel].cap_info.ddrconfig;
1720 params->ch[channel].cap_info.rank = 2;
1721 params->ch[channel].cap_info.col = 10;
1722 params->ch[channel].cap_info.bk = 3;
1723 params->ch[channel].cap_info.bw = 2;
1724 params->ch[channel].cap_info.row_3_4 = 0;
1725 params->ch[channel].cap_info.cs0_row = 15;
1726 params->ch[channel].cap_info.cs1_row = 15;
1727 params->ch[channel].cap_info.ddrconfig = 1;
1729 set_memory_map(chan, channel, params);
1730 params->ch[channel].cap_info.ddrconfig =
1731 calculate_ddrconfig(params, channel);
1732 set_ddrconfig(chan, params, channel,
1733 params->ch[channel].cap_info.ddrconfig);
1734 set_cap_relate_config(chan, params, channel);
1736 cs0_cap = (1 << (params->ch[channel].cap_info.bw
1737 + params->ch[channel].cap_info.col
1738 + params->ch[channel].cap_info.bk
1739 + params->ch[channel].cap_info.cs0_row));
1741 if (params->ch[channel].cap_info.row_3_4)
1742 cs0_cap = cs0_cap * 3 / 4;
1745 set_ddr_stride(dram->pmusgrf, 0x17);
1747 set_ddr_stride(dram->pmusgrf, 0x18);
1749 /* read and write data to DRAM, avoid be optimized by compiler. */
1751 addr = (void __iomem *)0x100;
1753 addr = (void __iomem *)(cs0_cap + 0x100);
1756 writel(val + 1, addr);
1758 read_mr(ddr_pctl_regs, rank, 5, &mr5);
1759 read_mr(ddr_pctl_regs, rank, 12, &mr12);
1760 read_mr(ddr_pctl_regs, rank, 14, &mr14);
1762 if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {
1767 params->ch[channel].cap_info.rank = cs;
1768 params->ch[channel].cap_info.col = col;
1769 params->ch[channel].cap_info.bk = bk;
1770 params->ch[channel].cap_info.bw = bw;
1771 params->ch[channel].cap_info.row_3_4 = row_3_4;
1772 params->ch[channel].cap_info.cs0_row = cs0_row;
1773 params->ch[channel].cap_info.cs1_row = cs1_row;
1774 params->ch[channel].cap_info.ddrconfig = ddrconfig;
1776 set_ddr_stride(dram->pmusgrf, stride);
1781 static void set_lpddr4_dq_odt(const struct chan_info *chan,
1782 struct rk3399_sdram_params *params, u32 ctl,
1783 bool en, bool ctl_phy_reg, u32 mr5)
1785 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1786 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1787 struct io_setting *io;
1793 io = lpddr4_get_io_settings(params, mr5);
1795 reg_value = io->dq_odt;
1799 clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
1800 clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
1802 clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
1803 clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
1804 clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
1805 clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
1808 clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
1809 clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
1811 clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
1812 clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
1813 clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
1814 clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
1818 clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
1819 clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
1821 clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
1822 clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
1823 clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
1824 clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
1829 static void set_lpddr4_ca_odt(const struct chan_info *chan,
1830 struct rk3399_sdram_params *params, u32 ctl,
1831 bool en, bool ctl_phy_reg, u32 mr5)
1833 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1834 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1835 struct io_setting *io;
1841 io = lpddr4_get_io_settings(params, mr5);
1843 reg_value = io->ca_odt;
1847 clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
1848 clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
1850 clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
1851 clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
1852 clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
1853 clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
1856 clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
1857 clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
1859 clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
1860 clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
1861 clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
1862 clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
1866 clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
1867 clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
1869 clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
1870 clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
1871 clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
1872 clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
1877 static void set_lpddr4_MR3(const struct chan_info *chan,
1878 struct rk3399_sdram_params *params, u32 ctl,
1879 bool ctl_phy_reg, u32 mr5)
1881 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1882 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1883 struct io_setting *io;
1886 io = lpddr4_get_io_settings(params, mr5);
1888 reg_value = ((io->pdds << 3) | 1);
1892 clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
1893 clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
1895 clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
1896 clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
1897 clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
1898 clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
1901 clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
1903 clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
1906 clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
1907 clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
1908 clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
1909 clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
1913 clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
1914 clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
1916 clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
1917 clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
1918 clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
1919 clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
1924 static void set_lpddr4_MR12(const struct chan_info *chan,
1925 struct rk3399_sdram_params *params, u32 ctl,
1926 bool ctl_phy_reg, u32 mr5)
1928 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1929 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1930 struct io_setting *io;
1933 io = lpddr4_get_io_settings(params, mr5);
1935 reg_value = io->ca_vref;
1939 clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
1941 clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
1944 clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
1945 clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
1946 clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
1947 clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
1950 clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
1951 clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
1953 clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
1954 clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
1955 clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
1956 clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
1960 clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
1962 clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
1965 clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
1966 clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
1967 clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
1968 clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
1973 static void set_lpddr4_MR14(const struct chan_info *chan,
1974 struct rk3399_sdram_params *params, u32 ctl,
1975 bool ctl_phy_reg, u32 mr5)
1977 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1978 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1979 struct io_setting *io;
1982 io = lpddr4_get_io_settings(params, mr5);
1984 reg_value = io->dq_vref;
1988 clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
1990 clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
1993 clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
1994 clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
1995 clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
1996 clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
1999 clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
2000 clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
2002 clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
2003 clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
2004 clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
2005 clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
2009 clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
2011 clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
2014 clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
2015 clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
2016 clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
2017 clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
2022 static void lpddr4_copy_phy(struct dram_info *dram,
2023 struct rk3399_sdram_params *params, u32 phy,
2024 struct rk3399_sdram_params *timings,
2027 u32 *denali_ctl, *denali_phy;
2028 u32 *denali_phy_params;
2032 denali_ctl = dram->chan[channel].pctl->denali_ctl;
2033 denali_phy = dram->chan[channel].publ->denali_phy;
2034 denali_phy_params = timings->phy_regs.denali_phy;
2037 clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, phy << 8);
2038 writel(denali_phy_params[896], &denali_phy[896]);
2040 /* phy_pll_ctrl_ca, phy_pll_ctrl */
2041 writel(denali_phy_params[911], &denali_phy[911]);
2043 /* phy_low_freq_sel */
2044 clrsetbits_le32(&denali_phy[913], 0x1,
2045 denali_phy_params[913] & 0x1);
2047 /* phy_grp_slave_delay_x, phy_cslvl_dly_step */
2048 writel(denali_phy_params[916], &denali_phy[916]);
2049 writel(denali_phy_params[917], &denali_phy[917]);
2050 writel(denali_phy_params[918], &denali_phy[918]);
2052 /* phy_adrz_sw_wraddr_shift_x */
2053 writel(denali_phy_params[512], &denali_phy[512]);
2054 clrsetbits_le32(&denali_phy[513], 0xffff,
2055 denali_phy_params[513] & 0xffff);
2056 writel(denali_phy_params[640], &denali_phy[640]);
2057 clrsetbits_le32(&denali_phy[641], 0xffff,
2058 denali_phy_params[641] & 0xffff);
2059 writel(denali_phy_params[768], &denali_phy[768]);
2060 clrsetbits_le32(&denali_phy[769], 0xffff,
2061 denali_phy_params[769] & 0xffff);
2063 writel(denali_phy_params[544], &denali_phy[544]);
2064 writel(denali_phy_params[545], &denali_phy[545]);
2065 writel(denali_phy_params[546], &denali_phy[546]);
2066 writel(denali_phy_params[547], &denali_phy[547]);
2068 writel(denali_phy_params[672], &denali_phy[672]);
2069 writel(denali_phy_params[673], &denali_phy[673]);
2070 writel(denali_phy_params[674], &denali_phy[674]);
2071 writel(denali_phy_params[675], &denali_phy[675]);
2073 writel(denali_phy_params[800], &denali_phy[800]);
2074 writel(denali_phy_params[801], &denali_phy[801]);
2075 writel(denali_phy_params[802], &denali_phy[802]);
2076 writel(denali_phy_params[803], &denali_phy[803]);
2079 * phy_adr_master_delay_start_x
2080 * phy_adr_master_delay_step_x
2081 * phy_adr_master_delay_wait_x
2083 writel(denali_phy_params[548], &denali_phy[548]);
2084 writel(denali_phy_params[676], &denali_phy[676]);
2085 writel(denali_phy_params[804], &denali_phy[804]);
2087 /* phy_adr_calvl_dly_step_x */
2088 writel(denali_phy_params[549], &denali_phy[549]);
2089 writel(denali_phy_params[677], &denali_phy[677]);
2090 writel(denali_phy_params[805], &denali_phy[805]);
2093 * phy_clk_wrdm_slave_delay_x
2094 * phy_clk_wrdqz_slave_delay_x
2095 * phy_clk_wrdqs_slave_delay_x
2097 sdram_copy_to_reg((u32 *)&denali_phy[59],
2098 (u32 *)&denali_phy_params[59], (63 - 58) * 4);
2099 sdram_copy_to_reg((u32 *)&denali_phy[187],
2100 (u32 *)&denali_phy_params[187], (191 - 186) * 4);
2101 sdram_copy_to_reg((u32 *)&denali_phy[315],
2102 (u32 *)&denali_phy_params[315], (319 - 314) * 4);
2103 sdram_copy_to_reg((u32 *)&denali_phy[443],
2104 (u32 *)&denali_phy_params[443], (447 - 442) * 4);
2107 * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8
2108 * dqs_tsel_wr_end[7:4] add half cycle
2109 * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8
2110 * dq_tsel_wr_end[7:4] add half cycle
2112 writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
2113 writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
2114 writel(denali_phy_params[85], &denali_phy[85]);
2116 writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
2117 writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
2118 writel(denali_phy_params[213], &denali_phy[213]);
2120 writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
2121 writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
2122 writel(denali_phy_params[341], &denali_phy[341]);
2124 writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
2125 writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
2126 writel(denali_phy_params[469], &denali_phy[469]);
2129 * phy_gtlvl_resp_wait_cnt_x
2130 * phy_gtlvl_dly_step_x
2131 * phy_wrlvl_resp_wait_cnt_x
2132 * phy_gtlvl_final_step_x
2133 * phy_gtlvl_back_step_x
2134 * phy_rdlvl_dly_step_x
2136 * phy_master_delay_step_x
2137 * phy_master_delay_wait_x
2138 * phy_wrlvl_dly_step_x
2140 * phy_wdqlvl_dly_step_x
2142 writel(denali_phy_params[87], &denali_phy[87]);
2143 writel(denali_phy_params[88], &denali_phy[88]);
2144 writel(denali_phy_params[89], &denali_phy[89]);
2145 writel(denali_phy_params[90], &denali_phy[90]);
2147 writel(denali_phy_params[215], &denali_phy[215]);
2148 writel(denali_phy_params[216], &denali_phy[216]);
2149 writel(denali_phy_params[217], &denali_phy[217]);
2150 writel(denali_phy_params[218], &denali_phy[218]);
2152 writel(denali_phy_params[343], &denali_phy[343]);
2153 writel(denali_phy_params[344], &denali_phy[344]);
2154 writel(denali_phy_params[345], &denali_phy[345]);
2155 writel(denali_phy_params[346], &denali_phy[346]);
2157 writel(denali_phy_params[471], &denali_phy[471]);
2158 writel(denali_phy_params[472], &denali_phy[472]);
2159 writel(denali_phy_params[473], &denali_phy[473]);
2160 writel(denali_phy_params[474], &denali_phy[474]);
2163 * phy_gtlvl_lat_adj_start_x
2164 * phy_gtlvl_rddqs_slv_dly_start_x
2165 * phy_rdlvl_rddqs_dq_slv_dly_start_x
2166 * phy_wdqlvl_dqdm_slv_dly_start_x
2168 writel(denali_phy_params[80], &denali_phy[80]);
2169 writel(denali_phy_params[81], &denali_phy[81]);
2171 writel(denali_phy_params[208], &denali_phy[208]);
2172 writel(denali_phy_params[209], &denali_phy[209]);
2174 writel(denali_phy_params[336], &denali_phy[336]);
2175 writel(denali_phy_params[337], &denali_phy[337]);
2177 writel(denali_phy_params[464], &denali_phy[464]);
2178 writel(denali_phy_params[465], &denali_phy[465]);
2181 * phy_master_delay_start_x
2182 * phy_sw_master_mode_x
2183 * phy_rddata_en_tsel_dly_x
2185 writel(denali_phy_params[86], &denali_phy[86]);
2186 writel(denali_phy_params[214], &denali_phy[214]);
2187 writel(denali_phy_params[342], &denali_phy[342]);
2188 writel(denali_phy_params[470], &denali_phy[470]);
2191 * phy_rddqz_slave_delay_x
2192 * phy_rddqs_dqz_fall_slave_delay_x
2193 * phy_rddqs_dqz_rise_slave_delay_x
2194 * phy_rddqs_dm_fall_slave_delay_x
2195 * phy_rddqs_dm_rise_slave_delay_x
2196 * phy_rddqs_gate_slave_delay_x
2197 * phy_wrlvl_delay_early_threshold_x
2198 * phy_write_path_lat_add_x
2199 * phy_rddqs_latency_adjust_x
2200 * phy_wrlvl_delay_period_threshold_x
2201 * phy_wrlvl_early_force_zero_x
2203 sdram_copy_to_reg((u32 *)&denali_phy[64],
2204 (u32 *)&denali_phy_params[64], (67 - 63) * 4);
2205 clrsetbits_le32(&denali_phy[68], 0xfffffc00,
2206 denali_phy_params[68] & 0xfffffc00);
2207 sdram_copy_to_reg((u32 *)&denali_phy[69],
2208 (u32 *)&denali_phy_params[69], (79 - 68) * 4);
2209 sdram_copy_to_reg((u32 *)&denali_phy[192],
2210 (u32 *)&denali_phy_params[192], (195 - 191) * 4);
2211 clrsetbits_le32(&denali_phy[196], 0xfffffc00,
2212 denali_phy_params[196] & 0xfffffc00);
2213 sdram_copy_to_reg((u32 *)&denali_phy[197],
2214 (u32 *)&denali_phy_params[197], (207 - 196) * 4);
2215 sdram_copy_to_reg((u32 *)&denali_phy[320],
2216 (u32 *)&denali_phy_params[320], (323 - 319) * 4);
2217 clrsetbits_le32(&denali_phy[324], 0xfffffc00,
2218 denali_phy_params[324] & 0xfffffc00);
2219 sdram_copy_to_reg((u32 *)&denali_phy[325],
2220 (u32 *)&denali_phy_params[325], (335 - 324) * 4);
2221 sdram_copy_to_reg((u32 *)&denali_phy[448],
2222 (u32 *)&denali_phy_params[448], (451 - 447) * 4);
2223 clrsetbits_le32(&denali_phy[452], 0xfffffc00,
2224 denali_phy_params[452] & 0xfffffc00);
2225 sdram_copy_to_reg((u32 *)&denali_phy[453],
2226 (u32 *)&denali_phy_params[453], (463 - 452) * 4);
2228 /* phy_two_cyc_preamble_x */
2229 clrsetbits_le32(&denali_phy[7], 0x3 << 24,
2230 denali_phy_params[7] & (0x3 << 24));
2231 clrsetbits_le32(&denali_phy[135], 0x3 << 24,
2232 denali_phy_params[135] & (0x3 << 24));
2233 clrsetbits_le32(&denali_phy[263], 0x3 << 24,
2234 denali_phy_params[263] & (0x3 << 24));
2235 clrsetbits_le32(&denali_phy[391], 0x3 << 24,
2236 denali_phy_params[391] & (0x3 << 24));
2239 if (timings->base.ddr_freq < 400 * MHz)
2241 else if (timings->base.ddr_freq < 800 * MHz)
2243 else if (timings->base.ddr_freq < 1200 * MHz)
2246 /* phy_924 phy_pad_fdbk_drive */
2247 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
2248 /* phy_926 phy_pad_data_drive */
2249 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
2250 /* phy_927 phy_pad_dqs_drive */
2251 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
2252 /* phy_928 phy_pad_addr_drive */
2253 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
2254 /* phy_929 phy_pad_clk_drive */
2255 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
2256 /* phy_935 phy_pad_cke_drive */
2257 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
2258 /* phy_937 phy_pad_rst_drive */
2259 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
2260 /* phy_939 phy_pad_cs_drive */
2261 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
2263 read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
2264 set_ds_odt(&dram->chan[channel], timings, true, mr5);
2266 ctl = lpddr4_get_ctl(timings, phy);
2267 set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
2268 set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
2269 set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
2270 set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5);
2271 set_lpddr4_MR14(&dram->chan[channel], timings, ctl, true, mr5);
2274 * if phy_sw_master_mode_x not bypass mode,
2275 * clear phy_slice_pwr_rdc_disable.
2276 * note: need use timings, not ddr_publ_regs
2278 if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
2279 clrbits_le32(&denali_phy[10], 1 << 16);
2280 clrbits_le32(&denali_phy[138], 1 << 16);
2281 clrbits_le32(&denali_phy[266], 1 << 16);
2282 clrbits_le32(&denali_phy[394], 1 << 16);
2286 * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
2288 * NOTE: need use timings, not ddr_publ_regs
2290 if ((denali_phy_params[84] >> 16) & 1) {
2291 if (((readl(&denali_ctl[217 + ctl]) >> 16) & 0x1f) < 8)
2292 clrsetbits_le32(&denali_ctl[217 + ctl],
2293 0x1f << 16, 8 << 16);
2297 static void lpddr4_set_phy(struct dram_info *dram,
2298 struct rk3399_sdram_params *params, u32 phy,
2299 struct rk3399_sdram_params *timings)
2303 for (channel = 0; channel < 2; channel++)
2304 lpddr4_copy_phy(dram, params, phy, timings, channel);
2307 static int lpddr4_set_ctl(struct dram_info *dram,
2308 struct rk3399_sdram_params *params, u32 ctl, u32 hz)
2313 /* cci idle req stall */
2314 writel(0x70007, &dram->grf->soc_con0);
2316 /* enable all clk */
2317 setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
2320 setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
2321 while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
2326 writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
2327 (ctl << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
2328 while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
2331 ret_clk = clk_set_rate(&dram->ddr_clk, hz);
2333 printf("%s clk set failed %d\n", __func__, ret_clk);
2337 writel(0x20002, &dram->cic->cic_ctrl0);
2338 while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
2342 clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
2343 while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
2346 /* clear enable all clk */
2347 clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
2349 /* lpddr4 ctl2 can not do training, all training will fail */
2350 if (!(params->base.dramtype == LPDDR4 && ctl == 2)) {
2351 for (channel = 0; channel < 2; channel++) {
2352 if (!(params->ch[channel].cap_info.col))
2354 ret = data_training(dram, channel, params,
2357 printf("%s: channel %d training failed!\n",
2360 debug("%s: channel %d training pass\n",
2368 static int lpddr4_set_rate(struct dram_info *dram,
2369 struct rk3399_sdram_params *params)
2374 for (ctl = 0; ctl < 2; ctl++) {
2375 phy = lpddr4_get_phy(params, ctl);
2377 lpddr4_set_phy(dram, params, phy, &lpddr4_timings[ctl]);
2378 lpddr4_set_ctl(dram, params, ctl,
2379 lpddr4_timings[ctl].base.ddr_freq);
2381 debug("%s: change freq to %d mhz %d, %d\n", __func__,
2382 lpddr4_timings[ctl].base.ddr_freq / MHz, ctl, phy);
2387 #endif /* CONFIG_RAM_RK3399_LPDDR4 */
2389 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
2391 unsigned int stride = params->base.stride;
2392 unsigned int channel, chinfo = 0;
2393 unsigned int ch_cap[2] = {0, 0};
2396 for (channel = 0; channel < 2; channel++) {
2397 unsigned int cs0_cap = 0;
2398 unsigned int cs1_cap = 0;
2399 struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;
2401 if (cap_info->col == 0)
2404 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
2405 cap_info->bk + cap_info->bw - 20));
2406 if (cap_info->rank > 1)
2407 cs1_cap = cs0_cap >> (cap_info->cs0_row
2408 - cap_info->cs1_row);
2409 if (cap_info->row_3_4) {
2410 cs0_cap = cs0_cap * 3 / 4;
2411 cs1_cap = cs1_cap * 3 / 4;
2413 ch_cap[channel] = cs0_cap + cs1_cap;
2414 chinfo |= 1 << channel;
2417 /* stride calculation for 1 channel */
2418 if (params->base.num_channels == 1 && chinfo & 1)
2419 return 0x17; /* channel a */
2421 /* stride calculation for 2 channels, default gstride type is 256B */
2422 if (ch_cap[0] == ch_cap[1]) {
2423 cap = ch_cap[0] + ch_cap[1];
2434 * 768MB + 768MB same as total 2GB memory
2435 * useful space: 0-768MB 1GB-1792MB
2442 /* 1536MB + 1536MB */
2451 printf("%s: Unable to calculate stride for ", __func__);
2452 print_size((cap * (1 << 20)), " capacity\n");
2457 sdram_print_stride(stride);
2462 static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
2464 params->ch[channel].cap_info.rank = 0;
2465 params->ch[channel].cap_info.col = 0;
2466 params->ch[channel].cap_info.bk = 0;
2467 params->ch[channel].cap_info.bw = 32;
2468 params->ch[channel].cap_info.dbw = 32;
2469 params->ch[channel].cap_info.row_3_4 = 0;
2470 params->ch[channel].cap_info.cs0_row = 0;
2471 params->ch[channel].cap_info.cs1_row = 0;
2472 params->ch[channel].cap_info.ddrconfig = 0;
2475 static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
2480 for (channel = 0; channel < 2; channel++) {
2481 const struct chan_info *chan = &dram->chan[channel];
2482 struct rk3399_cru *cru = dram->cru;
2483 struct rk3399_ddr_publ_regs *publ = chan->publ;
2485 phy_pctrl_reset(cru, channel);
2486 phy_dll_bypass_set(publ, params->base.ddr_freq);
2488 ret = pctl_cfg(dram, chan, channel, params);
2490 printf("%s: pctl config failed\n", __func__);
2494 /* start to trigger initialization */
2495 pctl_start(dram, channel);
2501 static int sdram_init(struct dram_info *dram,
2502 struct rk3399_sdram_params *params)
2504 unsigned char dramtype = params->base.dramtype;
2505 unsigned int ddr_freq = params->base.ddr_freq;
2506 int channel, ch, rank;
2509 debug("Starting SDRAM initialization...\n");
2511 if ((dramtype == DDR3 && ddr_freq > 933) ||
2512 (dramtype == LPDDR3 && ddr_freq > 933) ||
2513 (dramtype == LPDDR4 && ddr_freq > 800)) {
2514 debug("SDRAM frequency is to high!");
2518 for (ch = 0; ch < 2; ch++) {
2519 params->ch[ch].cap_info.rank = 2;
2520 for (rank = 2; rank != 0; rank--) {
2521 ret = pctl_init(dram, params);
2523 printf("%s: pctl init failed\n", __func__);
2527 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
2528 if (dramtype == LPDDR3)
2531 params->ch[ch].cap_info.rank = rank;
2533 ret = dram->ops->data_training(dram, ch, rank, params);
2535 debug("%s: data trained for rank %d, ch %d\n",
2536 __func__, rank, ch);
2540 /* Computed rank with associated channel number */
2541 params->ch[ch].cap_info.rank = rank;
2544 params->base.num_channels = 0;
2545 for (channel = 0; channel < 2; channel++) {
2546 const struct chan_info *chan = &dram->chan[channel];
2547 struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;
2548 u8 training_flag = PI_FULL_TRAINING;
2550 if (cap_info->rank == 0) {
2551 clear_channel_params(params, channel);
2554 params->base.num_channels++;
2558 debug(channel ? "1: " : "0: ");
2560 /* LPDDR3 should have write and read gate training */
2561 if (params->base.dramtype == LPDDR3)
2562 training_flag = PI_WRITE_LEVELING |
2563 PI_READ_GATE_TRAINING;
2565 if (params->base.dramtype != LPDDR4) {
2566 ret = data_training(dram, channel, params,
2569 debug("%s: data train failed for channel %d\n",
2575 sdram_print_ddr_info(cap_info, ¶ms->base);
2576 set_memory_map(chan, channel, params);
2577 cap_info->ddrconfig = calculate_ddrconfig(params, channel);
2579 set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
2580 set_cap_relate_config(chan, params, channel);
2583 if (params->base.num_channels == 0) {
2584 printf("%s: ", __func__);
2585 sdram_print_dram_type(params->base.dramtype);
2586 printf(" - %dMHz failed!\n", params->base.ddr_freq);
2590 params->base.stride = calculate_stride(params);
2591 dram_all_config(dram, params);
2592 dram->ops->set_rate(dram, params);
2594 debug("Finish SDRAM initialization...\n");
2598 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
2600 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
2601 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
2604 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
2605 (u32 *)&plat->sdram_params,
2606 sizeof(plat->sdram_params) / sizeof(u32));
2608 printf("%s: Cannot read rockchip,sdram-params %d\n",
2612 ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
2614 printf("%s: regmap failed %d\n", __func__, ret);
2620 #if CONFIG_IS_ENABLED(OF_PLATDATA)
2621 static int conv_of_platdata(struct udevice *dev)
2623 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
2624 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
2627 ret = regmap_init_mem_platdata(dev, dtplat->reg,
2628 ARRAY_SIZE(dtplat->reg) / 2,
2637 static const struct sdram_rk3399_ops rk3399_ops = {
2638 #if !defined(CONFIG_RAM_RK3399_LPDDR4)
2639 .data_training = default_data_training,
2640 .set_rate = switch_to_phy_index1,
2642 .data_training = lpddr4_mr_detect,
2643 .set_rate = lpddr4_set_rate,
2647 static int rk3399_dmc_init(struct udevice *dev)
2649 struct dram_info *priv = dev_get_priv(dev);
2650 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
2652 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
2653 struct rk3399_sdram_params *params = &plat->sdram_params;
2655 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
2656 struct rk3399_sdram_params *params =
2657 (void *)dtplat->rockchip_sdram_params;
2659 ret = conv_of_platdata(dev);
2664 priv->ops = &rk3399_ops;
2665 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
2666 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
2667 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
2668 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
2669 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
2670 priv->pmucru = rockchip_get_pmucru();
2671 priv->cru = rockchip_get_cru();
2672 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
2673 priv->chan[0].pi = regmap_get_range(plat->map, 1);
2674 priv->chan[0].publ = regmap_get_range(plat->map, 2);
2675 priv->chan[0].msch = regmap_get_range(plat->map, 3);
2676 priv->chan[1].pctl = regmap_get_range(plat->map, 4);
2677 priv->chan[1].pi = regmap_get_range(plat->map, 5);
2678 priv->chan[1].publ = regmap_get_range(plat->map, 6);
2679 priv->chan[1].msch = regmap_get_range(plat->map, 7);
2681 debug("con reg %p %p %p %p %p %p %p %p\n",
2682 priv->chan[0].pctl, priv->chan[0].pi,
2683 priv->chan[0].publ, priv->chan[0].msch,
2684 priv->chan[1].pctl, priv->chan[1].pi,
2685 priv->chan[1].publ, priv->chan[1].msch);
2686 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
2687 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
2689 #if CONFIG_IS_ENABLED(OF_PLATDATA)
2690 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
2692 ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
2695 printf("%s clk get failed %d\n", __func__, ret);
2699 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
2701 printf("%s clk set failed %d\n", __func__, ret);
2705 ret = sdram_init(priv, params);
2707 printf("%s DRAM init failed %d\n", __func__, ret);
2715 static int rk3399_dmc_probe(struct udevice *dev)
2717 #if defined(CONFIG_TPL_BUILD) || \
2718 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
2719 if (rk3399_dmc_init(dev))
2722 struct dram_info *priv = dev_get_priv(dev);
2724 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
2725 debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
2726 priv->info.base = CONFIG_SYS_SDRAM_BASE;
2728 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
2733 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
2735 struct dram_info *priv = dev_get_priv(dev);
2742 static struct ram_ops rk3399_dmc_ops = {
2743 .get_info = rk3399_dmc_get_info,
2746 static const struct udevice_id rk3399_dmc_ids[] = {
2747 { .compatible = "rockchip,rk3399-dmc" },
2751 U_BOOT_DRIVER(dmc_rk3399) = {
2752 .name = "rockchip_rk3399_dmc",
2754 .of_match = rk3399_dmc_ids,
2755 .ops = &rk3399_dmc_ops,
2756 #if defined(CONFIG_TPL_BUILD) || \
2757 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
2758 .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
2760 .probe = rk3399_dmc_probe,
2761 .priv_auto_alloc_size = sizeof(struct dram_info),
2762 #if defined(CONFIG_TPL_BUILD) || \
2763 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
2764 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),