1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * (C) Copyright 2016-2017 Rockchip Inc.
5 * Adapted from coreboot.
11 #include <dt-structs.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/cru_rk3399.h>
18 #include <asm/arch-rockchip/grf_rk3399.h>
19 #include <asm/arch-rockchip/hardware.h>
20 #include <asm/arch-rockchip/sdram_common.h>
21 #include <asm/arch-rockchip/sdram_rk3399.h>
22 #include <linux/err.h>
25 #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
26 #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
27 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
29 #define PHY_DRV_ODT_HI_Z 0x0
30 #define PHY_DRV_ODT_240 0x1
31 #define PHY_DRV_ODT_120 0x8
32 #define PHY_DRV_ODT_80 0x9
33 #define PHY_DRV_ODT_60 0xc
34 #define PHY_DRV_ODT_48 0xd
35 #define PHY_DRV_ODT_40 0xe
36 #define PHY_DRV_ODT_34_3 0xf
39 struct rk3399_ddr_pctl_regs *pctl;
40 struct rk3399_ddr_pi_regs *pi;
41 struct rk3399_ddr_publ_regs *publ;
42 struct rk3399_msch_regs *msch;
46 #if defined(CONFIG_TPL_BUILD) || \
47 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
48 struct chan_info chan[2];
50 struct rk3399_cru *cru;
51 struct rk3399_pmucru *pmucru;
52 struct rk3399_pmusgrf_regs *pmusgrf;
53 struct rk3399_ddr_cic_regs *cic;
56 struct rk3399_pmugrf_regs *pmugrf;
59 #if defined(CONFIG_TPL_BUILD) || \
60 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
62 struct rockchip_dmc_plat {
63 #if CONFIG_IS_ENABLED(OF_PLATDATA)
64 struct dtd_rockchip_rk3399_dmc dtplat;
66 struct rk3399_sdram_params sdram_params;
71 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
75 for (i = 0; i < n / sizeof(u32); i++) {
82 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
85 u32 *denali_phy = ddr_publ_regs->denali_phy;
87 /* From IP spec, only freq small than 125 can enter dll bypass mode */
89 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
90 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
91 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
92 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
93 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
95 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
96 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
97 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
98 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
100 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
101 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
102 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
103 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
104 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
106 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
107 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
108 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
109 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
113 static void set_memory_map(const struct chan_info *chan, u32 channel,
114 const struct rk3399_sdram_params *params)
116 const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel];
117 u32 *denali_ctl = chan->pctl->denali_ctl;
118 u32 *denali_pi = chan->pi->denali_pi;
123 /* Get row number from ddrconfig setting */
124 if (sdram_ch->cap_info.ddrconfig < 2 ||
125 sdram_ch->cap_info.ddrconfig == 4)
127 else if (sdram_ch->cap_info.ddrconfig == 3)
132 cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
133 reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
135 /* Set the dram configuration to ctrl */
136 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
137 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
138 ((3 - sdram_ch->cap_info.bk) << 16) |
141 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
142 cs_map | (reduc << 16));
144 /* PI_199 PI_COL_DIFF:RW:0:4 */
145 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
147 /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
148 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
149 ((3 - sdram_ch->cap_info.bk) << 16) |
151 /* PI_41 PI_CS_MAP:RW:24:4 */
152 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
153 if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
154 writel(0x2EC7FFFF, &denali_pi[34]);
157 static void set_ds_odt(const struct chan_info *chan,
158 const struct rk3399_sdram_params *params)
160 u32 *denali_phy = chan->publ->denali_phy;
162 u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
163 u32 tsel_idle_select_p, tsel_rd_select_p;
164 u32 tsel_idle_select_n, tsel_rd_select_n;
165 u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
166 u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
169 if (params->base.dramtype == LPDDR4) {
170 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
171 tsel_rd_select_n = PHY_DRV_ODT_240;
173 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
174 tsel_idle_select_n = PHY_DRV_ODT_240;
176 tsel_wr_select_dq_p = PHY_DRV_ODT_40;
177 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
179 tsel_wr_select_ca_p = PHY_DRV_ODT_40;
180 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
181 } else if (params->base.dramtype == LPDDR3) {
182 tsel_rd_select_p = PHY_DRV_ODT_240;
183 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
185 tsel_idle_select_p = PHY_DRV_ODT_240;
186 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
188 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
189 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
191 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
192 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
194 tsel_rd_select_p = PHY_DRV_ODT_240;
195 tsel_rd_select_n = PHY_DRV_ODT_240;
197 tsel_idle_select_p = PHY_DRV_ODT_240;
198 tsel_idle_select_n = PHY_DRV_ODT_240;
200 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
201 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
203 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
204 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
207 if (params->base.odt == 1)
216 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
217 * sets termination values for read/idle cycles and drive strength
218 * for write cycles for DQ/DM
220 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
221 (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
222 (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
223 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
224 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
225 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
226 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
229 * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
230 * sets termination values for read/idle cycles and drive strength
231 * for write cycles for DQS
233 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
234 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
235 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
236 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
238 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
239 reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
240 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
241 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
242 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
244 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
245 clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
247 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
248 clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
250 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
251 clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
253 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
254 clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
256 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
257 clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
259 /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
260 clrsetbits_le32(&denali_phy[924], 0xff,
261 tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
262 clrsetbits_le32(&denali_phy[925], 0xff,
263 tsel_rd_select_n | (tsel_rd_select_p << 4));
265 /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
266 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
268 clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
269 clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
270 clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
271 clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
273 /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
274 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
276 clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
277 clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
278 clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
279 clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
281 /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
282 reg_value = tsel_wr_en << 8;
283 clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
284 clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
285 clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
287 /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
288 reg_value = tsel_wr_en << 17;
289 clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
291 * pad_rst/cke/cs/clk_term tsel 1bits
292 * DENALI_PHY_938/936/940/934 offset_17
294 clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
295 clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
296 clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
297 clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
299 /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
300 clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
303 static int phy_io_config(const struct chan_info *chan,
304 const struct rk3399_sdram_params *params)
306 u32 *denali_phy = chan->publ->denali_phy;
307 u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
310 u32 drv_value, odt_value;
314 if (params->base.dramtype == LPDDR4) {
317 vref_value_dq = 0x1f;
319 vref_value_ac = 0x1f;
320 } else if (params->base.dramtype == LPDDR3) {
321 if (params->base.odt == 1) {
322 vref_mode_dq = 0x5; /* LPDDR3 ODT */
323 drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
324 odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
325 if (drv_value == PHY_DRV_ODT_48) {
327 case PHY_DRV_ODT_240:
328 vref_value_dq = 0x16;
330 case PHY_DRV_ODT_120:
331 vref_value_dq = 0x26;
334 vref_value_dq = 0x36;
337 debug("Invalid ODT value.\n");
340 } else if (drv_value == PHY_DRV_ODT_40) {
342 case PHY_DRV_ODT_240:
343 vref_value_dq = 0x19;
345 case PHY_DRV_ODT_120:
346 vref_value_dq = 0x23;
349 vref_value_dq = 0x31;
352 debug("Invalid ODT value.\n");
355 } else if (drv_value == PHY_DRV_ODT_34_3) {
357 case PHY_DRV_ODT_240:
358 vref_value_dq = 0x17;
360 case PHY_DRV_ODT_120:
361 vref_value_dq = 0x20;
364 vref_value_dq = 0x2e;
367 debug("Invalid ODT value.\n");
371 debug("Invalid DRV value.\n");
375 vref_mode_dq = 0x2; /* LPDDR3 */
376 vref_value_dq = 0x1f;
379 vref_value_ac = 0x1f;
380 } else if (params->base.dramtype == DDR3) {
383 vref_value_dq = 0x1f;
385 vref_value_ac = 0x1f;
387 debug("Unknown DRAM type.\n");
391 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
393 /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
394 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
395 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
396 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
397 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
398 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
399 /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
400 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
402 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
404 /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
405 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
407 if (params->base.dramtype == LPDDR4)
409 else if (params->base.dramtype == LPDDR3)
411 else if (params->base.dramtype == DDR3)
416 /* PHY_924 PHY_PAD_FDBK_DRIVE */
417 clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
418 /* PHY_926 PHY_PAD_DATA_DRIVE */
419 clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
420 /* PHY_927 PHY_PAD_DQS_DRIVE */
421 clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
422 /* PHY_928 PHY_PAD_ADDR_DRIVE */
423 clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
424 /* PHY_929 PHY_PAD_CLK_DRIVE */
425 clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
426 /* PHY_935 PHY_PAD_CKE_DRIVE */
427 clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
428 /* PHY_937 PHY_PAD_RST_DRIVE */
429 clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
430 /* PHY_939 PHY_PAD_CS_DRIVE */
431 clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
434 if (params->base.ddr_freq < 400)
436 else if (params->base.ddr_freq < 800)
438 else if (params->base.ddr_freq < 1200)
443 /* PHY_924 PHY_PAD_FDBK_DRIVE */
444 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
445 /* PHY_926 PHY_PAD_DATA_DRIVE */
446 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
447 /* PHY_927 PHY_PAD_DQS_DRIVE */
448 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
449 /* PHY_928 PHY_PAD_ADDR_DRIVE */
450 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
451 /* PHY_929 PHY_PAD_CLK_DRIVE */
452 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
453 /* PHY_935 PHY_PAD_CKE_DRIVE */
454 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
455 /* PHY_937 PHY_PAD_RST_DRIVE */
456 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
457 /* PHY_939 PHY_PAD_CS_DRIVE */
458 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
463 static int pctl_cfg(const struct chan_info *chan, u32 channel,
464 const struct rk3399_sdram_params *params)
466 u32 *denali_ctl = chan->pctl->denali_ctl;
467 u32 *denali_pi = chan->pi->denali_pi;
468 u32 *denali_phy = chan->publ->denali_phy;
469 const u32 *params_ctl = params->pctl_regs.denali_ctl;
470 const u32 *params_phy = params->phy_regs.denali_phy;
472 u32 pwrup_srefresh_exit;
474 const ulong timeout_ms = 200;
477 * work around controller bug:
478 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
480 copy_to_reg(&denali_ctl[1], ¶ms_ctl[1],
481 sizeof(struct rk3399_ddr_pctl_regs) - 4);
482 writel(params_ctl[0], &denali_ctl[0]);
484 copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0],
485 sizeof(struct rk3399_ddr_pi_regs));
487 /* rank count need to set for init */
488 set_memory_map(chan, channel, params);
490 writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
491 writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
492 writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
494 pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
495 clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
498 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
500 setbits_le32(&denali_pi[0], START);
501 setbits_le32(&denali_ctl[0], START);
503 /* Waiting for phy DLL lock */
505 tmp = readl(&denali_phy[920]);
506 tmp1 = readl(&denali_phy[921]);
507 tmp2 = readl(&denali_phy[922]);
508 if ((((tmp >> 16) & 0x1) == 0x1) &&
509 (((tmp1 >> 16) & 0x1) == 0x1) &&
510 (((tmp1 >> 0) & 0x1) == 0x1) &&
511 (((tmp2 >> 0) & 0x1) == 0x1))
515 copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4);
516 copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4);
517 copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4);
518 copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4);
519 copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4);
520 copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);
521 copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);
522 copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);
523 set_ds_odt(chan, params);
526 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
527 * dqs_tsel_wr_end[7:4] add Half cycle
529 tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
530 clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
531 tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
532 clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
533 tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
534 clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
535 tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
536 clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
539 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
540 * dq_tsel_wr_end[7:4] add Half cycle
542 tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
543 clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
544 tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
545 clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
546 tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
547 clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
548 tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
549 clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
551 ret = phy_io_config(chan, params);
556 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
558 /* Waiting for PHY and DRAM init complete */
561 if (get_timer(tmp) > timeout_ms) {
562 pr_err("DRAM (%s): phy failed to lock within %ld ms\n",
563 __func__, timeout_ms);
566 } while (!(readl(&denali_ctl[203]) & (1 << 3)));
567 debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
569 clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
570 pwrup_srefresh_exit);
574 static void select_per_cs_training_index(const struct chan_info *chan,
577 u32 *denali_phy = chan->publ->denali_phy;
579 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
580 if ((readl(&denali_phy[84]) >> 16) & 1) {
583 * phy_per_cs_training_index_X 1bit offset_24
585 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
586 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
587 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
588 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
592 static void override_write_leveling_value(const struct chan_info *chan)
594 u32 *denali_ctl = chan->pctl->denali_ctl;
595 u32 *denali_phy = chan->publ->denali_phy;
598 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
599 setbits_le32(&denali_phy[896], 1);
603 * phy_per_cs_training_multicast_en_X 1bit offset_16
605 clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
606 clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
607 clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
608 clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
610 for (byte = 0; byte < 4; byte++)
611 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
614 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
615 clrbits_le32(&denali_phy[896], 1);
617 /* CTL_200 ctrlupd_req 1bit offset_8 */
618 clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
621 static int data_training_ca(const struct chan_info *chan, u32 channel,
622 const struct rk3399_sdram_params *params)
624 u32 *denali_pi = chan->pi->denali_pi;
625 u32 *denali_phy = chan->publ->denali_phy;
627 u32 obs_0, obs_1, obs_2, obs_err = 0;
628 u32 rank = params->ch[channel].cap_info.rank;
631 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
632 writel(0x00003f7c, (&denali_pi[175]));
634 rank_mask = (rank == 1) ? 0x1 : 0x3;
636 for (i = 0; i < 4; i++) {
637 if (!(rank_mask & (1 << i)))
640 select_per_cs_training_index(chan, i);
642 /* PI_100 PI_CALVL_EN:RW:8:2 */
643 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
645 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
646 clrsetbits_le32(&denali_pi[92],
647 (0x1 << 16) | (0x3 << 24),
648 (0x1 << 16) | (i << 24));
650 /* Waiting for training complete */
652 /* PI_174 PI_INT_STATUS:RD:8:18 */
653 tmp = readl(&denali_pi[174]) >> 8;
656 * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
658 obs_0 = readl(&denali_phy[532]);
659 obs_1 = readl(&denali_phy[660]);
660 obs_2 = readl(&denali_phy[788]);
661 if (((obs_0 >> 30) & 0x3) ||
662 ((obs_1 >> 30) & 0x3) ||
663 ((obs_2 >> 30) & 0x3))
665 if ((((tmp >> 11) & 0x1) == 0x1) &&
666 (((tmp >> 13) & 0x1) == 0x1) &&
667 (((tmp >> 5) & 0x1) == 0x0) &&
670 else if ((((tmp >> 5) & 0x1) == 0x1) ||
675 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
676 writel(0x00003f7c, (&denali_pi[175]));
679 clrbits_le32(&denali_pi[100], 0x3 << 8);
684 static int data_training_wl(const struct chan_info *chan, u32 channel,
685 const struct rk3399_sdram_params *params)
687 u32 *denali_pi = chan->pi->denali_pi;
688 u32 *denali_phy = chan->publ->denali_phy;
690 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
691 u32 rank = params->ch[channel].cap_info.rank;
693 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
694 writel(0x00003f7c, (&denali_pi[175]));
696 for (i = 0; i < rank; i++) {
697 select_per_cs_training_index(chan, i);
699 /* PI_60 PI_WRLVL_EN:RW:8:2 */
700 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
702 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
703 clrsetbits_le32(&denali_pi[59],
704 (0x1 << 8) | (0x3 << 16),
705 (0x1 << 8) | (i << 16));
707 /* Waiting for training complete */
709 /* PI_174 PI_INT_STATUS:RD:8:18 */
710 tmp = readl(&denali_pi[174]) >> 8;
713 * check status obs, if error maybe can not
714 * get leveling done PHY_40/168/296/424
715 * phy_wrlvl_status_obs_X:0:13
717 obs_0 = readl(&denali_phy[40]);
718 obs_1 = readl(&denali_phy[168]);
719 obs_2 = readl(&denali_phy[296]);
720 obs_3 = readl(&denali_phy[424]);
721 if (((obs_0 >> 12) & 0x1) ||
722 ((obs_1 >> 12) & 0x1) ||
723 ((obs_2 >> 12) & 0x1) ||
724 ((obs_3 >> 12) & 0x1))
726 if ((((tmp >> 10) & 0x1) == 0x1) &&
727 (((tmp >> 13) & 0x1) == 0x1) &&
728 (((tmp >> 4) & 0x1) == 0x0) &&
731 else if ((((tmp >> 4) & 0x1) == 0x1) ||
736 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
737 writel(0x00003f7c, (&denali_pi[175]));
740 override_write_leveling_value(chan);
741 clrbits_le32(&denali_pi[60], 0x3 << 8);
746 static int data_training_rg(const struct chan_info *chan, u32 channel,
747 const struct rk3399_sdram_params *params)
749 u32 *denali_pi = chan->pi->denali_pi;
750 u32 *denali_phy = chan->publ->denali_phy;
752 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
753 u32 rank = params->ch[channel].cap_info.rank;
755 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
756 writel(0x00003f7c, (&denali_pi[175]));
758 for (i = 0; i < rank; i++) {
759 select_per_cs_training_index(chan, i);
761 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
762 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
765 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
766 * PI_RDLVL_CS:RW:24:2
768 clrsetbits_le32(&denali_pi[74],
769 (0x1 << 16) | (0x3 << 24),
770 (0x1 << 16) | (i << 24));
772 /* Waiting for training complete */
774 /* PI_174 PI_INT_STATUS:RD:8:18 */
775 tmp = readl(&denali_pi[174]) >> 8;
780 * PHY_GTLVL_STATUS_OBS_x:16:8
782 obs_0 = readl(&denali_phy[43]);
783 obs_1 = readl(&denali_phy[171]);
784 obs_2 = readl(&denali_phy[299]);
785 obs_3 = readl(&denali_phy[427]);
786 if (((obs_0 >> (16 + 6)) & 0x3) ||
787 ((obs_1 >> (16 + 6)) & 0x3) ||
788 ((obs_2 >> (16 + 6)) & 0x3) ||
789 ((obs_3 >> (16 + 6)) & 0x3))
791 if ((((tmp >> 9) & 0x1) == 0x1) &&
792 (((tmp >> 13) & 0x1) == 0x1) &&
793 (((tmp >> 3) & 0x1) == 0x0) &&
796 else if ((((tmp >> 3) & 0x1) == 0x1) ||
801 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
802 writel(0x00003f7c, (&denali_pi[175]));
805 clrbits_le32(&denali_pi[80], 0x3 << 24);
810 static int data_training_rl(const struct chan_info *chan, u32 channel,
811 const struct rk3399_sdram_params *params)
813 u32 *denali_pi = chan->pi->denali_pi;
815 u32 rank = params->ch[channel].cap_info.rank;
817 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
818 writel(0x00003f7c, (&denali_pi[175]));
820 for (i = 0; i < rank; i++) {
821 select_per_cs_training_index(chan, i);
823 /* PI_80 PI_RDLVL_EN:RW:16:2 */
824 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
826 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
827 clrsetbits_le32(&denali_pi[74],
828 (0x1 << 8) | (0x3 << 24),
829 (0x1 << 8) | (i << 24));
831 /* Waiting for training complete */
833 /* PI_174 PI_INT_STATUS:RD:8:18 */
834 tmp = readl(&denali_pi[174]) >> 8;
837 * make sure status obs not report error bit
839 * phy_rdlvl_status_obs_X:16:8
841 if ((((tmp >> 8) & 0x1) == 0x1) &&
842 (((tmp >> 13) & 0x1) == 0x1) &&
843 (((tmp >> 2) & 0x1) == 0x0))
845 else if (((tmp >> 2) & 0x1) == 0x1)
849 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
850 writel(0x00003f7c, (&denali_pi[175]));
853 clrbits_le32(&denali_pi[80], 0x3 << 16);
858 static int data_training_wdql(const struct chan_info *chan, u32 channel,
859 const struct rk3399_sdram_params *params)
861 u32 *denali_pi = chan->pi->denali_pi;
863 u32 rank = params->ch[channel].cap_info.rank;
865 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
866 writel(0x00003f7c, (&denali_pi[175]));
868 for (i = 0; i < rank; i++) {
869 select_per_cs_training_index(chan, i);
872 * disable PI_WDQLVL_VREF_EN before wdq leveling?
873 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
875 clrbits_le32(&denali_pi[181], 0x1 << 8);
877 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
878 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
880 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
881 clrsetbits_le32(&denali_pi[121],
882 (0x1 << 8) | (0x3 << 16),
883 (0x1 << 8) | (i << 16));
885 /* Waiting for training complete */
887 /* PI_174 PI_INT_STATUS:RD:8:18 */
888 tmp = readl(&denali_pi[174]) >> 8;
889 if ((((tmp >> 12) & 0x1) == 0x1) &&
890 (((tmp >> 13) & 0x1) == 0x1) &&
891 (((tmp >> 6) & 0x1) == 0x0))
893 else if (((tmp >> 6) & 0x1) == 0x1)
897 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
898 writel(0x00003f7c, (&denali_pi[175]));
901 clrbits_le32(&denali_pi[124], 0x3 << 16);
906 static int data_training(const struct chan_info *chan, u32 channel,
907 const struct rk3399_sdram_params *params,
910 u32 *denali_phy = chan->publ->denali_phy;
913 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
914 setbits_le32(&denali_phy[927], (1 << 22));
916 if (training_flag == PI_FULL_TRAINING) {
917 if (params->base.dramtype == LPDDR4) {
918 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
919 PI_READ_GATE_TRAINING |
920 PI_READ_LEVELING | PI_WDQ_LEVELING;
921 } else if (params->base.dramtype == LPDDR3) {
922 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
923 PI_READ_GATE_TRAINING;
924 } else if (params->base.dramtype == DDR3) {
925 training_flag = PI_WRITE_LEVELING |
926 PI_READ_GATE_TRAINING |
931 /* ca training(LPDDR4,LPDDR3 support) */
932 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
933 ret = data_training_ca(chan, channel, params);
935 debug("%s: data training ca failed\n", __func__);
940 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
941 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
942 ret = data_training_wl(chan, channel, params);
944 debug("%s: data training wl failed\n", __func__);
949 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
950 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
951 ret = data_training_rg(chan, channel, params);
953 debug("%s: data training rg failed\n", __func__);
958 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
959 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
960 ret = data_training_rl(chan, channel, params);
962 debug("%s: data training rl failed\n", __func__);
967 /* wdq leveling(LPDDR4 support) */
968 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
969 ret = data_training_wdql(chan, channel, params);
971 debug("%s: data training wdql failed\n", __func__);
976 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
977 clrbits_le32(&denali_phy[927], (1 << 22));
982 static void set_ddrconfig(const struct chan_info *chan,
983 const struct rk3399_sdram_params *params,
984 unsigned char channel, u32 ddrconfig)
986 /* only need to set ddrconfig */
987 struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
988 unsigned int cs0_cap = 0;
989 unsigned int cs1_cap = 0;
991 cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
992 + params->ch[channel].cap_info.col
993 + params->ch[channel].cap_info.bk
994 + params->ch[channel].cap_info.bw - 20));
995 if (params->ch[channel].cap_info.rank > 1)
996 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
997 - params->ch[channel].cap_info.cs1_row);
998 if (params->ch[channel].cap_info.row_3_4) {
999 cs0_cap = cs0_cap * 3 / 4;
1000 cs1_cap = cs1_cap * 3 / 4;
1003 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1004 writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1005 &ddr_msch_regs->ddrsize);
1008 static void dram_all_config(struct dram_info *dram,
1009 const struct rk3399_sdram_params *params)
1012 unsigned int channel, idx;
1014 sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
1015 sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
1017 for (channel = 0, idx = 0;
1018 (idx < params->base.num_channels) && (channel < 2);
1020 const struct rk3399_sdram_channel *info = ¶ms->ch[channel];
1021 struct rk3399_msch_regs *ddr_msch_regs;
1022 const struct rk3399_msch_timings *noc_timing;
1024 if (params->ch[channel].cap_info.col == 0)
1027 sys_reg |= info->cap_info.row_3_4 <<
1028 SYS_REG_ROW_3_4_SHIFT(channel);
1029 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
1030 sys_reg |= (info->cap_info.rank - 1) <<
1031 SYS_REG_RANK_SHIFT(channel);
1032 sys_reg |= (info->cap_info.col - 9) <<
1033 SYS_REG_COL_SHIFT(channel);
1034 sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
1035 SYS_REG_BK_SHIFT(channel);
1036 sys_reg |= (info->cap_info.cs0_row - 13) <<
1037 SYS_REG_CS0_ROW_SHIFT(channel);
1038 sys_reg |= (info->cap_info.cs1_row - 13) <<
1039 SYS_REG_CS1_ROW_SHIFT(channel);
1040 sys_reg |= (2 >> info->cap_info.bw) <<
1041 SYS_REG_BW_SHIFT(channel);
1042 sys_reg |= (2 >> info->cap_info.dbw) <<
1043 SYS_REG_DBW_SHIFT(channel);
1045 ddr_msch_regs = dram->chan[channel].msch;
1046 noc_timing = ¶ms->ch[channel].noc_timings;
1047 writel(noc_timing->ddrtiminga0,
1048 &ddr_msch_regs->ddrtiminga0);
1049 writel(noc_timing->ddrtimingb0,
1050 &ddr_msch_regs->ddrtimingb0);
1051 writel(noc_timing->ddrtimingc0,
1052 &ddr_msch_regs->ddrtimingc0);
1053 writel(noc_timing->devtodev0,
1054 &ddr_msch_regs->devtodev0);
1055 writel(noc_timing->ddrmode,
1056 &ddr_msch_regs->ddrmode);
1058 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1059 if (params->ch[channel].cap_info.rank == 1)
1060 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1064 writel(sys_reg, &dram->pmugrf->os_reg2);
1065 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1066 params->base.stride << 10);
1068 /* reboot hold register set */
1069 writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1070 PRESET_GPIO1_HOLD(1),
1071 &dram->pmucru->pmucru_rstnhold_con[1]);
1072 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1075 static int switch_to_phy_index1(struct dram_info *dram,
1076 const struct rk3399_sdram_params *params)
1080 u32 ch_count = params->base.num_channels;
1084 writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1085 1 << 4 | 1 << 2 | 1),
1086 &dram->cic->cic_ctrl0);
1087 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1091 debug("index1 frequency change overtime\n");
1097 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1098 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1102 debug("index1 frequency done overtime\n");
1107 for (channel = 0; channel < ch_count; channel++) {
1108 denali_phy = dram->chan[channel].publ->denali_phy;
1109 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1110 ret = data_training(&dram->chan[channel], channel,
1111 params, PI_FULL_TRAINING);
1113 debug("index1 training failed\n");
1121 static int sdram_init(struct dram_info *dram,
1122 const struct rk3399_sdram_params *params)
1124 unsigned char dramtype = params->base.dramtype;
1125 unsigned int ddr_freq = params->base.ddr_freq;
1129 debug("Starting SDRAM initialization...\n");
1131 if ((dramtype == DDR3 && ddr_freq > 933) ||
1132 (dramtype == LPDDR3 && ddr_freq > 933) ||
1133 (dramtype == LPDDR4 && ddr_freq > 800)) {
1134 debug("SDRAM frequency is to high!");
1138 for (channel = 0; channel < 2; channel++) {
1139 const struct chan_info *chan = &dram->chan[channel];
1140 struct rk3399_ddr_publ_regs *publ = chan->publ;
1142 phy_dll_bypass_set(publ, ddr_freq);
1144 if (channel >= params->base.num_channels)
1147 ret = pctl_cfg(chan, channel, params);
1149 printf("%s: pctl config failed\n", __func__);
1153 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1154 if (dramtype == LPDDR3)
1157 if (data_training(chan, channel, params, PI_FULL_TRAINING)) {
1158 printf("%s: data training failed\n", __func__);
1162 set_ddrconfig(chan, params, channel,
1163 params->ch[channel].cap_info.ddrconfig);
1165 dram_all_config(dram, params);
1166 switch_to_phy_index1(dram, params);
1168 debug("Finish SDRAM initialization...\n");
1172 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1174 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1175 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1178 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1179 (u32 *)&plat->sdram_params,
1180 sizeof(plat->sdram_params) / sizeof(u32));
1182 printf("%s: Cannot read rockchip,sdram-params %d\n",
1186 ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1188 printf("%s: regmap failed %d\n", __func__, ret);
1194 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1195 static int conv_of_platdata(struct udevice *dev)
1197 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1198 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1201 ret = regmap_init_mem_platdata(dev, dtplat->reg,
1202 ARRAY_SIZE(dtplat->reg) / 2,
1211 static int rk3399_dmc_init(struct udevice *dev)
1213 struct dram_info *priv = dev_get_priv(dev);
1214 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1216 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1217 struct rk3399_sdram_params *params = &plat->sdram_params;
1219 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1220 struct rk3399_sdram_params *params =
1221 (void *)dtplat->rockchip_sdram_params;
1223 ret = conv_of_platdata(dev);
1228 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1229 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1230 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1231 priv->pmucru = rockchip_get_pmucru();
1232 priv->cru = rockchip_get_cru();
1233 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1234 priv->chan[0].pi = regmap_get_range(plat->map, 1);
1235 priv->chan[0].publ = regmap_get_range(plat->map, 2);
1236 priv->chan[0].msch = regmap_get_range(plat->map, 3);
1237 priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1238 priv->chan[1].pi = regmap_get_range(plat->map, 5);
1239 priv->chan[1].publ = regmap_get_range(plat->map, 6);
1240 priv->chan[1].msch = regmap_get_range(plat->map, 7);
1242 debug("con reg %p %p %p %p %p %p %p %p\n",
1243 priv->chan[0].pctl, priv->chan[0].pi,
1244 priv->chan[0].publ, priv->chan[0].msch,
1245 priv->chan[1].pctl, priv->chan[1].pi,
1246 priv->chan[1].publ, priv->chan[1].msch);
1247 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1248 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1250 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1251 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1253 ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1256 printf("%s clk get failed %d\n", __func__, ret);
1260 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1262 printf("%s clk set failed %d\n", __func__, ret);
1266 ret = sdram_init(priv, params);
1268 printf("%s DRAM init failed %d\n", __func__, ret);
1276 static int rk3399_dmc_probe(struct udevice *dev)
1278 #if defined(CONFIG_TPL_BUILD) || \
1279 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1280 if (rk3399_dmc_init(dev))
1283 struct dram_info *priv = dev_get_priv(dev);
1285 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1286 debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1287 priv->info.base = CONFIG_SYS_SDRAM_BASE;
1289 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1294 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1296 struct dram_info *priv = dev_get_priv(dev);
1303 static struct ram_ops rk3399_dmc_ops = {
1304 .get_info = rk3399_dmc_get_info,
1307 static const struct udevice_id rk3399_dmc_ids[] = {
1308 { .compatible = "rockchip,rk3399-dmc" },
1312 U_BOOT_DRIVER(dmc_rk3399) = {
1313 .name = "rockchip_rk3399_dmc",
1315 .of_match = rk3399_dmc_ids,
1316 .ops = &rk3399_dmc_ops,
1317 #if defined(CONFIG_TPL_BUILD) || \
1318 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1319 .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1321 .probe = rk3399_dmc_probe,
1322 .priv_auto_alloc_size = sizeof(struct dram_info),
1323 #if defined(CONFIG_TPL_BUILD) || \
1324 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1325 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),