drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/sdram_common.h>
  21 #include <asm/arch-rockchip/sdram_rk3399.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  26 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  27 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  28
  29 #define PHY_DRV_ODT_HI_Z        0x0
  30 #define PHY_DRV_ODT_240         0x1
  31 #define PHY_DRV_ODT_120         0x8
  32 #define PHY_DRV_ODT_80          0x9
  33 #define PHY_DRV_ODT_60          0xc
  34 #define PHY_DRV_ODT_48          0xd
  35 #define PHY_DRV_ODT_40          0xe
  36 #define PHY_DRV_ODT_34_3        0xf
  37
  38 #define PHY_BOOSTP_EN           0x1
  39 #define PHY_BOOSTN_EN           0x1
  40 #define PHY_SLEWP_EN            0x1
  41 #define PHY_SLEWN_EN            0x1
  42 #define PHY_RX_CM_INPUT         0x1
  43
  44 #define CRU_SFTRST_DDR_CTRL(ch, n)      ((0x1 << (8 + 16 + (ch) * 4)) | \
  45                                         ((n) << (8 + (ch) * 4)))
  46 #define CRU_SFTRST_DDR_PHY(ch, n)       ((0x1 << (9 + 16 + (ch) * 4)) | \
  47                                         ((n) << (9 + (ch) * 4)))
  48 struct chan_info {
  49         struct rk3399_ddr_pctl_regs *pctl;
  50         struct rk3399_ddr_pi_regs *pi;
  51         struct rk3399_ddr_publ_regs *publ;
  52         struct rk3399_msch_regs *msch;
  53 };
  54
  55 struct dram_info {
  56 #if defined(CONFIG_TPL_BUILD) || \
  57         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  58         u32 pwrup_srefresh_exit[2];
  59         struct chan_info chan[2];
  60         struct clk ddr_clk;
  61         struct rk3399_cru *cru;
  62         struct rk3399_grf_regs *grf;
  63         struct rk3399_pmucru *pmucru;
  64         struct rk3399_pmusgrf_regs *pmusgrf;
  65         struct rk3399_ddr_cic_regs *cic;
  66 #endif
  67         struct ram_info info;
  68         struct rk3399_pmugrf_regs *pmugrf;
  69 };
  70
  71 #if defined(CONFIG_TPL_BUILD) || \
  72         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  73
  74 struct rockchip_dmc_plat {
  75 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  76         struct dtd_rockchip_rk3399_dmc dtplat;
  77 #else
  78         struct rk3399_sdram_params sdram_params;
  79 #endif
  80         struct regmap *map;
  81 };
  82
  83 struct io_setting {
  84         u32 mhz;
  85         u32 mr5;
  86         /* dram side */
  87         u32 dq_odt;
  88         u32 ca_odt;
  89         u32 pdds;
  90         u32 dq_vref;
  91         u32 ca_vref;
  92         /* phy side */
  93         u32 rd_odt;
  94         u32 wr_dq_drv;
  95         u32 wr_ca_drv;
  96         u32 wr_ckcs_drv;
  97         u32 rd_odt_en;
  98         u32 rd_vref;
  99 } lpddr4_io_setting[] = {
 100         {
 101                 50 * MHz,
 102                 0,
 103                 /* dram side */
 104                 0,      /* dq_odt; */
 105                 0,      /* ca_odt; */
 106                 6,      /* pdds; */
 107                 0x72,   /* dq_vref; */
 108                 0x72,   /* ca_vref; */
 109                 /* phy side */
 110                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 111                 PHY_DRV_ODT_40, /* wr_dq_drv; */
 112                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 113                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 114                 0,      /* rd_odt_en;*/
 115                 41,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 116         },
 117         {
 118                 600 * MHz,
 119                 0,
 120                 /* dram side */
 121                 1,      /* dq_odt; */
 122                 0,      /* ca_odt; */
 123                 6,      /* pdds; */
 124                 0x72,   /* dq_vref; */
 125                 0x72,   /* ca_vref; */
 126                 /* phy side */
 127                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 128                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 129                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 130                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 131                 0,      /* rd_odt_en; */
 132                 32,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 133         },
 134         {
 135                 800 * MHz,
 136                 0,
 137                 /* dram side */
 138                 1,      /* dq_odt; */
 139                 0,      /* ca_odt; */
 140                 1,      /* pdds; */
 141                 0x72,   /* dq_vref; */
 142                 0x72,   /* ca_vref; */
 143                 /* phy side */
 144                 PHY_DRV_ODT_40, /* rd_odt; */
 145                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 146                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 147                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 148                 1,      /* rd_odt_en; */
 149                 17,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 150         },
 151         {
 152                 933 * MHz,
 153                 0,
 154                 /* dram side */
 155                 3,      /* dq_odt; */
 156                 0,      /* ca_odt; */
 157                 6,      /* pdds; */
 158                 0x59,   /* dq_vref; 32% */
 159                 0x72,   /* ca_vref; */
 160                 /* phy side */
 161                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 162                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 163                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 164                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 165                 0,      /* rd_odt_en; */
 166                 32,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 167         },
 168         {
 169                 1066 * MHz,
 170                 0,
 171                 /* dram side */
 172                 6,      /* dq_odt; */
 173                 0,      /* ca_odt; */
 174                 1,      /* pdds; */
 175                 0x10,   /* dq_vref; */
 176                 0x72,   /* ca_vref; */
 177                 /* phy side */
 178                 PHY_DRV_ODT_40, /* rd_odt; */
 179                 PHY_DRV_ODT_60, /* wr_dq_drv; */
 180                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 181                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 182                 1,      /* rd_odt_en; */
 183                 17,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 184         },
 185 };
 186
 187 /**
 188  * phy = 0, PHY boot freq
 189  * phy = 1, PHY index 0
 190  * phy = 2, PHY index 1
 191  */
 192 static struct io_setting *
 193 lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
 194 {
 195         struct io_setting *io = NULL;
 196         u32 n;
 197
 198         for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
 199                 io = &lpddr4_io_setting[n];
 200
 201                 if (io->mr5 != 0) {
 202                         if (io->mhz >= params->base.ddr_freq &&
 203                             io->mr5 == mr5)
 204                                 break;
 205                 } else {
 206                         if (io->mhz >= params->base.ddr_freq)
 207                                 break;
 208                 }
 209         }
 210
 211         return io;
 212 }
 213
 214 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
 215 {
 216         return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
 217 }
 218
 219 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
 220 {
 221         int i;
 222
 223         for (i = 0; i < n / sizeof(u32); i++) {
 224                 writel(*src, dest);
 225                 src++;
 226                 dest++;
 227         }
 228 }
 229
 230 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
 231                             u32 phy)
 232 {
 233         channel &= 0x1;
 234         ctl &= 0x1;
 235         phy &= 0x1;
 236         writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
 237                                    CRU_SFTRST_DDR_PHY(channel, phy),
 238                                    &cru->softrst_con[4]);
 239 }
 240
 241 static void phy_pctrl_reset(struct rk3399_cru *cru,  u32 channel)
 242 {
 243         rkclk_ddr_reset(cru, channel, 1, 1);
 244         udelay(10);
 245
 246         rkclk_ddr_reset(cru, channel, 1, 0);
 247         udelay(10);
 248
 249         rkclk_ddr_reset(cru, channel, 0, 0);
 250         udelay(10);
 251 }
 252
 253 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
 254                                u32 freq)
 255 {
 256         u32 *denali_phy = ddr_publ_regs->denali_phy;
 257
 258         /* From IP spec, only freq small than 125 can enter dll bypass mode */
 259         if (freq <= 125) {
 260                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 261                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 262                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 263                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 264                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 265
 266                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 267                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 268                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 269                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 270         } else {
 271                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 272                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 273                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 274                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 275                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 276
 277                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 278                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 279                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 280                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 281         }
 282 }
 283
 284 static void set_memory_map(const struct chan_info *chan, u32 channel,
 285                            const struct rk3399_sdram_params *params)
 286 {
 287         const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
 288         u32 *denali_ctl = chan->pctl->denali_ctl;
 289         u32 *denali_pi = chan->pi->denali_pi;
 290         u32 cs_map;
 291         u32 reduc;
 292         u32 row;
 293
 294         /* Get row number from ddrconfig setting */
 295         if (sdram_ch->cap_info.ddrconfig < 2 ||
 296             sdram_ch->cap_info.ddrconfig == 4)
 297                 row = 16;
 298         else if (sdram_ch->cap_info.ddrconfig == 3)
 299                 row = 14;
 300         else
 301                 row = 15;
 302
 303         cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
 304         reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
 305
 306         /* Set the dram configuration to ctrl */
 307         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
 308         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 309                         ((3 - sdram_ch->cap_info.bk) << 16) |
 310                         ((16 - row) << 24));
 311
 312         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 313                         cs_map | (reduc << 16));
 314
 315         /* PI_199 PI_COL_DIFF:RW:0:4 */
 316         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
 317
 318         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 319         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 320                         ((3 - sdram_ch->cap_info.bk) << 16) |
 321                         ((16 - row) << 24));
 322
 323         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 324                 if (cs_map == 1)
 325                         cs_map = 0x5;
 326                 else if (cs_map == 2)
 327                         cs_map = 0xa;
 328                 else
 329                         cs_map = 0xF;
 330         }
 331
 332         /* PI_41 PI_CS_MAP:RW:24:4 */
 333         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 334         if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
 335                 writel(0x2EC7FFFF, &denali_pi[34]);
 336 }
 337
 338 static int phy_io_config(const struct chan_info *chan,
 339                          const struct rk3399_sdram_params *params)
 340 {
 341         u32 *denali_phy = chan->publ->denali_phy;
 342         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 343         u32 mode_sel;
 344         u32 reg_value;
 345         u32 drv_value, odt_value;
 346         u32 speed;
 347
 348         /* vref setting */
 349         if (params->base.dramtype == LPDDR4) {
 350                 /* LPDDR4 */
 351                 vref_mode_dq = 0x6;
 352                 vref_value_dq = 0x1f;
 353                 vref_mode_ac = 0x6;
 354                 vref_value_ac = 0x1f;
 355                 mode_sel = 0x6;
 356         } else if (params->base.dramtype == LPDDR3) {
 357                 if (params->base.odt == 1) {
 358                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 359                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 360                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 361                         if (drv_value == PHY_DRV_ODT_48) {
 362                                 switch (odt_value) {
 363                                 case PHY_DRV_ODT_240:
 364                                         vref_value_dq = 0x16;
 365                                         break;
 366                                 case PHY_DRV_ODT_120:
 367                                         vref_value_dq = 0x26;
 368                                         break;
 369                                 case PHY_DRV_ODT_60:
 370                                         vref_value_dq = 0x36;
 371                                         break;
 372                                 default:
 373                                         debug("Invalid ODT value.\n");
 374                                         return -EINVAL;
 375                                 }
 376                         } else if (drv_value == PHY_DRV_ODT_40) {
 377                                 switch (odt_value) {
 378                                 case PHY_DRV_ODT_240:
 379                                         vref_value_dq = 0x19;
 380                                         break;
 381                                 case PHY_DRV_ODT_120:
 382                                         vref_value_dq = 0x23;
 383                                         break;
 384                                 case PHY_DRV_ODT_60:
 385                                         vref_value_dq = 0x31;
 386                                         break;
 387                                 default:
 388                                         debug("Invalid ODT value.\n");
 389                                         return -EINVAL;
 390                                 }
 391                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 392                                 switch (odt_value) {
 393                                 case PHY_DRV_ODT_240:
 394                                         vref_value_dq = 0x17;
 395                                         break;
 396                                 case PHY_DRV_ODT_120:
 397                                         vref_value_dq = 0x20;
 398                                         break;
 399                                 case PHY_DRV_ODT_60:
 400                                         vref_value_dq = 0x2e;
 401                                         break;
 402                                 default:
 403                                         debug("Invalid ODT value.\n");
 404                                         return -EINVAL;
 405                                 }
 406                         } else {
 407                                 debug("Invalid DRV value.\n");
 408                                 return -EINVAL;
 409                         }
 410                 } else {
 411                         vref_mode_dq = 0x2;  /* LPDDR3 */
 412                         vref_value_dq = 0x1f;
 413                 }
 414                 vref_mode_ac = 0x2;
 415                 vref_value_ac = 0x1f;
 416                 mode_sel = 0x0;
 417         } else if (params->base.dramtype == DDR3) {
 418                 /* DDR3L */
 419                 vref_mode_dq = 0x1;
 420                 vref_value_dq = 0x1f;
 421                 vref_mode_ac = 0x1;
 422                 vref_value_ac = 0x1f;
 423                 mode_sel = 0x1;
 424         } else {
 425                 debug("Unknown DRAM type.\n");
 426                 return -EINVAL;
 427         }
 428
 429         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 430
 431         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 432         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 433         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 434         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 435         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 436         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 437         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 438         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 439
 440         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 441
 442         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 443         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 444
 445         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 446         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 447         /* PHY_926 PHY_PAD_DATA_DRIVE */
 448         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 449         /* PHY_927 PHY_PAD_DQS_DRIVE */
 450         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 451         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 452         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 453         /* PHY_929 PHY_PAD_CLK_DRIVE */
 454         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 455         /* PHY_935 PHY_PAD_CKE_DRIVE */
 456         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 457         /* PHY_937 PHY_PAD_RST_DRIVE */
 458         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 459         /* PHY_939 PHY_PAD_CS_DRIVE */
 460         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 461
 462         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 463                 /* BOOSTP_EN & BOOSTN_EN */
 464                 reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
 465                 /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
 466                 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
 467                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 468                 clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
 469                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 470                 clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
 471                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 472                 clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
 473                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 474                 clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
 475                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 476                 clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
 477                 /* PHY_937 PHY_PAD_RST_DRIVE */
 478                 clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
 479                 /* PHY_939 PHY_PAD_CS_DRIVE */
 480                 clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
 481
 482                 /* SLEWP_EN & SLEWN_EN */
 483                 reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
 484                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 485                 clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
 486                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 487                 clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
 488                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 489                 clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
 490                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 491                 clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
 492                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 493                 clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
 494                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 495                 clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
 496                 /* PHY_937 PHY_PAD_RST_DRIVE */
 497                 clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
 498                 /* PHY_939 PHY_PAD_CS_DRIVE */
 499                 clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
 500         }
 501
 502         /* speed setting */
 503         if (params->base.ddr_freq < 400)
 504                 speed = 0x0;
 505         else if (params->base.ddr_freq < 800)
 506                 speed = 0x1;
 507         else if (params->base.ddr_freq < 1200)
 508                 speed = 0x2;
 509         else
 510                 speed = 0x3;
 511
 512         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 513         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 514         /* PHY_926 PHY_PAD_DATA_DRIVE */
 515         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 516         /* PHY_927 PHY_PAD_DQS_DRIVE */
 517         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 518         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 519         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 520         /* PHY_929 PHY_PAD_CLK_DRIVE */
 521         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 522         /* PHY_935 PHY_PAD_CKE_DRIVE */
 523         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 524         /* PHY_937 PHY_PAD_RST_DRIVE */
 525         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 526         /* PHY_939 PHY_PAD_CS_DRIVE */
 527         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 528
 529         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 530                 /* RX_CM_INPUT */
 531                 reg_value = PHY_RX_CM_INPUT;
 532                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 533                 clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
 534                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 535                 clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
 536                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 537                 clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
 538                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 539                 clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
 540                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 541                 clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
 542                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 543                 clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
 544                 /* PHY_937 PHY_PAD_RST_DRIVE */
 545                 clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
 546                 /* PHY_939 PHY_PAD_CS_DRIVE */
 547                 clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
 548         }
 549
 550         return 0;
 551 }
 552
 553 static void set_ds_odt(const struct chan_info *chan,
 554                        const struct rk3399_sdram_params *params, u32 mr5)
 555 {
 556         u32 *denali_phy = chan->publ->denali_phy;
 557
 558         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 559         u32 tsel_idle_select_p, tsel_rd_select_p;
 560         u32 tsel_idle_select_n, tsel_rd_select_n;
 561         u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 562         u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 563         u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
 564         struct io_setting *io = NULL;
 565         u32 reg_value;
 566
 567         if (params->base.dramtype == LPDDR4) {
 568                 io = lpddr4_get_io_settings(params, mr5);
 569
 570                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 571                 tsel_rd_select_n = io->rd_odt;
 572
 573                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 574                 tsel_idle_select_n = PHY_DRV_ODT_240;
 575
 576                 tsel_wr_select_dq_p = io->wr_dq_drv;
 577                 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 578
 579                 tsel_wr_select_ca_p = io->wr_ca_drv;
 580                 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
 581
 582                 tsel_ckcs_select_p = io->wr_ckcs_drv;
 583                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 584         } else if (params->base.dramtype == LPDDR3) {
 585                 tsel_rd_select_p = PHY_DRV_ODT_240;
 586                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 587
 588                 tsel_idle_select_p = PHY_DRV_ODT_240;
 589                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 590
 591                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 592                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 593
 594                 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 595                 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
 596
 597                 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
 598                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 599         } else {
 600                 tsel_rd_select_p = PHY_DRV_ODT_240;
 601                 tsel_rd_select_n = PHY_DRV_ODT_240;
 602
 603                 tsel_idle_select_p = PHY_DRV_ODT_240;
 604                 tsel_idle_select_n = PHY_DRV_ODT_240;
 605
 606                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 607                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 608
 609                 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 610                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 611
 612                 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
 613                 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 614         }
 615
 616         if (params->base.odt == 1)
 617                 tsel_rd_en = 1;
 618         else
 619                 tsel_rd_en = 0;
 620
 621         tsel_wr_en = 0;
 622         tsel_idle_en = 0;
 623
 624         /*
 625          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 626          * sets termination values for read/idle cycles and drive strength
 627          * for write cycles for DQ/DM
 628          */
 629         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 630                     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
 631                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 632         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 633         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 634         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 635         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 636
 637         /*
 638          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 639          * sets termination values for read/idle cycles and drive strength
 640          * for write cycles for DQS
 641          */
 642         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 643         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 644         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 645         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 646
 647         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 648         reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
 649         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 650                 /* LPDDR4 these register read always return 0, so
 651                  * can not use clrsetbits_le32(), need to write32
 652                  */
 653                 writel((0x300 << 8) | reg_value, &denali_phy[544]);
 654                 writel((0x300 << 8) | reg_value, &denali_phy[672]);
 655                 writel((0x300 << 8) | reg_value, &denali_phy[800]);
 656         } else {
 657                 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 658                 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 659                 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 660         }
 661
 662         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 663         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 664
 665         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 666         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 667
 668         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 669         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 670
 671         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 672         clrsetbits_le32(&denali_phy[939], 0xff,
 673                         tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 674
 675         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 676         clrsetbits_le32(&denali_phy[929], 0xff,
 677                         tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 678
 679         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 680         clrsetbits_le32(&denali_phy[924], 0xff,
 681                         tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
 682         clrsetbits_le32(&denali_phy[925], 0xff,
 683                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 684
 685         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 686         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 687                 << 16;
 688         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 689         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 690         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 691         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 692
 693         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 694         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 695                 << 24;
 696         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 697         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 698         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 699         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 700
 701         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 702         reg_value = tsel_wr_en << 8;
 703         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 704         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 705         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 706
 707         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 708         reg_value = tsel_wr_en << 17;
 709         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 710         /*
 711          * pad_rst/cke/cs/clk_term tsel 1bits
 712          * DENALI_PHY_938/936/940/934 offset_17
 713          */
 714         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 715         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 716         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 717         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 718
 719         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 720         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 721
 722         phy_io_config(chan, params);
 723 }
 724
 725 static void pctl_start(struct dram_info *dram, u8 channel)
 726 {
 727         const struct chan_info *chan = &dram->chan[channel];
 728         u32 *denali_ctl = chan->pctl->denali_ctl;
 729         u32 *denali_phy = chan->publ->denali_phy;
 730         u32 *ddrc0_con = get_ddrc0_con(dram, channel);
 731         u32 count = 0;
 732         u32 byte, tmp;
 733
 734         writel(0x01000000, &ddrc0_con);
 735
 736         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 737
 738         while (!(readl(&denali_ctl[203]) & (1 << 3))) {
 739                 if (count > 1000) {
 740                         printf("%s: Failed to init pctl for channel %d\n",
 741                                __func__, channel);
 742                         while (1)
 743                                 ;
 744                 }
 745
 746                 udelay(1);
 747                 count++;
 748         }
 749
 750         writel(0x01000100, &ddrc0_con);
 751
 752         for (byte = 0; byte < 4; byte++) {
 753                 tmp = 0x820;
 754                 writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
 755                 writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
 756                 writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
 757                 writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
 758                 writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
 759
 760                 clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
 761         }
 762
 763         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 764                         dram->pwrup_srefresh_exit[channel]);
 765 }
 766
 767 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 768                     u32 channel, struct rk3399_sdram_params *params)
 769 {
 770         u32 *denali_ctl = chan->pctl->denali_ctl;
 771         u32 *denali_pi = chan->pi->denali_pi;
 772         u32 *denali_phy = chan->publ->denali_phy;
 773         const u32 *params_ctl = params->pctl_regs.denali_ctl;
 774         const u32 *params_phy = params->phy_regs.denali_phy;
 775         u32 tmp, tmp1, tmp2;
 776
 777         /*
 778          * work around controller bug:
 779          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 780          */
 781         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 782                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 783         writel(params_ctl[0], &denali_ctl[0]);
 784
 785         /*
 786          * two channel init at the same time, then ZQ Cal Start
 787          * at the same time, it will use the same RZQ, but cannot
 788          * start at the same time.
 789          *
 790          * So, increase tINIT3 for channel 1, will avoid two
 791          * channel ZQ Cal Start at the same time
 792          */
 793         if (params->base.dramtype == LPDDR4 && channel == 1) {
 794                 tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
 795                 tmp1 = readl(&denali_ctl[14]);
 796                 writel(tmp + tmp1, &denali_ctl[14]);
 797         }
 798
 799         copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 800                     sizeof(struct rk3399_ddr_pi_regs));
 801
 802         /* rank count need to set for init */
 803         set_memory_map(chan, channel, params);
 804
 805         writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
 806         writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 807         writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 808
 809         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 810                 writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
 811                 writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
 812         }
 813
 814         dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
 815                                              PWRUP_SREFRESH_EXIT;
 816         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 817
 818         /* PHY_DLL_RST_EN */
 819         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 820
 821         setbits_le32(&denali_pi[0], START);
 822         setbits_le32(&denali_ctl[0], START);
 823
 824         /**
 825          * LPDDR4 use PLL bypass mode for init
 826          * not need to wait for the PLL to lock
 827          */
 828         if (params->base.dramtype != LPDDR4) {
 829                 /* Waiting for phy DLL lock */
 830                 while (1) {
 831                         tmp = readl(&denali_phy[920]);
 832                         tmp1 = readl(&denali_phy[921]);
 833                         tmp2 = readl(&denali_phy[922]);
 834                         if ((((tmp >> 16) & 0x1) == 0x1) &&
 835                             (((tmp1 >> 16) & 0x1) == 0x1) &&
 836                             (((tmp1 >> 0) & 0x1) == 0x1) &&
 837                             (((tmp2 >> 0) & 0x1) == 0x1))
 838                                 break;
 839                 }
 840         }
 841
 842         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 843         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 844         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 845         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 846         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 847         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 848         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 849         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 850         set_ds_odt(chan, params, 0);
 851
 852         /*
 853          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 854          * dqs_tsel_wr_end[7:4] add Half cycle
 855          */
 856         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 857         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 858         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 859         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 860         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 861         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 862         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 863         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 864
 865         /*
 866          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 867          * dq_tsel_wr_end[7:4] add Half cycle
 868          */
 869         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 870         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 871         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 872         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 873         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 874         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 875         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 876         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 877
 878         return 0;
 879 }
 880
 881 static void select_per_cs_training_index(const struct chan_info *chan,
 882                                          u32 rank)
 883 {
 884         u32 *denali_phy = chan->publ->denali_phy;
 885
 886         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 887         if ((readl(&denali_phy[84]) >> 16) & 1) {
 888                 /*
 889                  * PHY_8/136/264/392
 890                  * phy_per_cs_training_index_X 1bit offset_24
 891                  */
 892                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 893                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 894                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 895                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 896         }
 897 }
 898
 899 static void override_write_leveling_value(const struct chan_info *chan)
 900 {
 901         u32 *denali_ctl = chan->pctl->denali_ctl;
 902         u32 *denali_phy = chan->publ->denali_phy;
 903         u32 byte;
 904
 905         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 906         setbits_le32(&denali_phy[896], 1);
 907
 908         /*
 909          * PHY_8/136/264/392
 910          * phy_per_cs_training_multicast_en_X 1bit offset_16
 911          */
 912         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 913         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 914         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 915         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 916
 917         for (byte = 0; byte < 4; byte++)
 918                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 919                                 0x200 << 16);
 920
 921         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 922         clrbits_le32(&denali_phy[896], 1);
 923
 924         /* CTL_200 ctrlupd_req 1bit offset_8 */
 925         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 926 }
 927
 928 static int data_training_ca(const struct chan_info *chan, u32 channel,
 929                             const struct rk3399_sdram_params *params)
 930 {
 931         u32 *denali_pi = chan->pi->denali_pi;
 932         u32 *denali_phy = chan->publ->denali_phy;
 933         u32 i, tmp;
 934         u32 obs_0, obs_1, obs_2, obs_err = 0;
 935         u32 rank = params->ch[channel].cap_info.rank;
 936         u32 rank_mask;
 937
 938         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 939         writel(0x00003f7c, (&denali_pi[175]));
 940
 941         if (params->base.dramtype == LPDDR4)
 942                 rank_mask = (rank == 1) ? 0x5 : 0xf;
 943         else
 944                 rank_mask = (rank == 1) ? 0x1 : 0x3;
 945
 946         for (i = 0; i < 4; i++) {
 947                 if (!(rank_mask & (1 << i)))
 948                         continue;
 949
 950                 select_per_cs_training_index(chan, i);
 951
 952                 /* PI_100 PI_CALVL_EN:RW:8:2 */
 953                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
 954
 955                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 956                 clrsetbits_le32(&denali_pi[92],
 957                                 (0x1 << 16) | (0x3 << 24),
 958                                 (0x1 << 16) | (i << 24));
 959
 960                 /* Waiting for training complete */
 961                 while (1) {
 962                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 963                         tmp = readl(&denali_pi[174]) >> 8;
 964                         /*
 965                          * check status obs
 966                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
 967                          */
 968                         obs_0 = readl(&denali_phy[532]);
 969                         obs_1 = readl(&denali_phy[660]);
 970                         obs_2 = readl(&denali_phy[788]);
 971                         if (((obs_0 >> 30) & 0x3) ||
 972                             ((obs_1 >> 30) & 0x3) ||
 973                             ((obs_2 >> 30) & 0x3))
 974                                 obs_err = 1;
 975                         if ((((tmp >> 11) & 0x1) == 0x1) &&
 976                             (((tmp >> 13) & 0x1) == 0x1) &&
 977                             (((tmp >> 5) & 0x1) == 0x0) &&
 978                             obs_err == 0)
 979                                 break;
 980                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
 981                                  (obs_err == 1))
 982                                 return -EIO;
 983                 }
 984
 985                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 986                 writel(0x00003f7c, (&denali_pi[175]));
 987         }
 988
 989         clrbits_le32(&denali_pi[100], 0x3 << 8);
 990
 991         return 0;
 992 }
 993
 994 static int data_training_wl(const struct chan_info *chan, u32 channel,
 995                             const struct rk3399_sdram_params *params)
 996 {
 997         u32 *denali_pi = chan->pi->denali_pi;
 998         u32 *denali_phy = chan->publ->denali_phy;
 999         u32 i, tmp;
1000         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1001         u32 rank = params->ch[channel].cap_info.rank;
1002
1003         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1004         writel(0x00003f7c, (&denali_pi[175]));
1005
1006         for (i = 0; i < rank; i++) {
1007                 select_per_cs_training_index(chan, i);
1008
1009                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
1010                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
1011
1012                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
1013                 clrsetbits_le32(&denali_pi[59],
1014                                 (0x1 << 8) | (0x3 << 16),
1015                                 (0x1 << 8) | (i << 16));
1016
1017                 /* Waiting for training complete */
1018                 while (1) {
1019                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1020                         tmp = readl(&denali_pi[174]) >> 8;
1021
1022                         /*
1023                          * check status obs, if error maybe can not
1024                          * get leveling done PHY_40/168/296/424
1025                          * phy_wrlvl_status_obs_X:0:13
1026                          */
1027                         obs_0 = readl(&denali_phy[40]);
1028                         obs_1 = readl(&denali_phy[168]);
1029                         obs_2 = readl(&denali_phy[296]);
1030                         obs_3 = readl(&denali_phy[424]);
1031                         if (((obs_0 >> 12) & 0x1) ||
1032                             ((obs_1 >> 12) & 0x1) ||
1033                             ((obs_2 >> 12) & 0x1) ||
1034                             ((obs_3 >> 12) & 0x1))
1035                                 obs_err = 1;
1036                         if ((((tmp >> 10) & 0x1) == 0x1) &&
1037                             (((tmp >> 13) & 0x1) == 0x1) &&
1038                             (((tmp >> 4) & 0x1) == 0x0) &&
1039                             obs_err == 0)
1040                                 break;
1041                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
1042                                  (obs_err == 1))
1043                                 return -EIO;
1044                 }
1045
1046                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1047                 writel(0x00003f7c, (&denali_pi[175]));
1048         }
1049
1050         override_write_leveling_value(chan);
1051         clrbits_le32(&denali_pi[60], 0x3 << 8);
1052
1053         return 0;
1054 }
1055
1056 static int data_training_rg(const struct chan_info *chan, u32 channel,
1057                             const struct rk3399_sdram_params *params)
1058 {
1059         u32 *denali_pi = chan->pi->denali_pi;
1060         u32 *denali_phy = chan->publ->denali_phy;
1061         u32 i, tmp;
1062         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1063         u32 rank = params->ch[channel].cap_info.rank;
1064
1065         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1066         writel(0x00003f7c, (&denali_pi[175]));
1067
1068         for (i = 0; i < rank; i++) {
1069                 select_per_cs_training_index(chan, i);
1070
1071                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
1072                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
1073
1074                 /*
1075                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
1076                  * PI_RDLVL_CS:RW:24:2
1077                  */
1078                 clrsetbits_le32(&denali_pi[74],
1079                                 (0x1 << 16) | (0x3 << 24),
1080                                 (0x1 << 16) | (i << 24));
1081
1082                 /* Waiting for training complete */
1083                 while (1) {
1084                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1085                         tmp = readl(&denali_pi[174]) >> 8;
1086
1087                         /*
1088                          * check status obs
1089                          * PHY_43/171/299/427
1090                          *     PHY_GTLVL_STATUS_OBS_x:16:8
1091                          */
1092                         obs_0 = readl(&denali_phy[43]);
1093                         obs_1 = readl(&denali_phy[171]);
1094                         obs_2 = readl(&denali_phy[299]);
1095                         obs_3 = readl(&denali_phy[427]);
1096                         if (((obs_0 >> (16 + 6)) & 0x3) ||
1097                             ((obs_1 >> (16 + 6)) & 0x3) ||
1098                             ((obs_2 >> (16 + 6)) & 0x3) ||
1099                             ((obs_3 >> (16 + 6)) & 0x3))
1100                                 obs_err = 1;
1101                         if ((((tmp >> 9) & 0x1) == 0x1) &&
1102                             (((tmp >> 13) & 0x1) == 0x1) &&
1103                             (((tmp >> 3) & 0x1) == 0x0) &&
1104                             obs_err == 0)
1105                                 break;
1106                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
1107                                  (obs_err == 1))
1108                                 return -EIO;
1109                 }
1110
1111                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1112                 writel(0x00003f7c, (&denali_pi[175]));
1113         }
1114
1115         clrbits_le32(&denali_pi[80], 0x3 << 24);
1116
1117         return 0;
1118 }
1119
1120 static int data_training_rl(const struct chan_info *chan, u32 channel,
1121                             const struct rk3399_sdram_params *params)
1122 {
1123         u32 *denali_pi = chan->pi->denali_pi;
1124         u32 i, tmp;
1125         u32 rank = params->ch[channel].cap_info.rank;
1126
1127         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1128         writel(0x00003f7c, (&denali_pi[175]));
1129
1130         for (i = 0; i < rank; i++) {
1131                 select_per_cs_training_index(chan, i);
1132
1133                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
1134                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
1135
1136                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
1137                 clrsetbits_le32(&denali_pi[74],
1138                                 (0x1 << 8) | (0x3 << 24),
1139                                 (0x1 << 8) | (i << 24));
1140
1141                 /* Waiting for training complete */
1142                 while (1) {
1143                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1144                         tmp = readl(&denali_pi[174]) >> 8;
1145
1146                         /*
1147                          * make sure status obs not report error bit
1148                          * PHY_46/174/302/430
1149                          *     phy_rdlvl_status_obs_X:16:8
1150                          */
1151                         if ((((tmp >> 8) & 0x1) == 0x1) &&
1152                             (((tmp >> 13) & 0x1) == 0x1) &&
1153                             (((tmp >> 2) & 0x1) == 0x0))
1154                                 break;
1155                         else if (((tmp >> 2) & 0x1) == 0x1)
1156                                 return -EIO;
1157                 }
1158
1159                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1160                 writel(0x00003f7c, (&denali_pi[175]));
1161         }
1162
1163         clrbits_le32(&denali_pi[80], 0x3 << 16);
1164
1165         return 0;
1166 }
1167
1168 static int data_training_wdql(const struct chan_info *chan, u32 channel,
1169                               const struct rk3399_sdram_params *params)
1170 {
1171         u32 *denali_pi = chan->pi->denali_pi;
1172         u32 i, tmp;
1173         u32 rank = params->ch[channel].cap_info.rank;
1174         u32 rank_mask;
1175
1176         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1177         writel(0x00003f7c, (&denali_pi[175]));
1178
1179         if (params->base.dramtype == LPDDR4)
1180                 rank_mask = (rank == 1) ? 0x5 : 0xf;
1181         else
1182                 rank_mask = (rank == 1) ? 0x1 : 0x3;
1183
1184         for (i = 0; i < 4; i++) {
1185                 if (!(rank_mask & (1 << i)))
1186                         continue;
1187
1188                 select_per_cs_training_index(chan, i);
1189
1190                 /*
1191                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
1192                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
1193                  */
1194                 clrbits_le32(&denali_pi[181], 0x1 << 8);
1195
1196                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
1197                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
1198
1199                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
1200                 clrsetbits_le32(&denali_pi[121],
1201                                 (0x1 << 8) | (0x3 << 16),
1202                                 (0x1 << 8) | (i << 16));
1203
1204                 /* Waiting for training complete */
1205                 while (1) {
1206                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1207                         tmp = readl(&denali_pi[174]) >> 8;
1208                         if ((((tmp >> 12) & 0x1) == 0x1) &&
1209                             (((tmp >> 13) & 0x1) == 0x1) &&
1210                             (((tmp >> 6) & 0x1) == 0x0))
1211                                 break;
1212                         else if (((tmp >> 6) & 0x1) == 0x1)
1213                                 return -EIO;
1214                 }
1215
1216                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1217                 writel(0x00003f7c, (&denali_pi[175]));
1218         }
1219
1220         clrbits_le32(&denali_pi[124], 0x3 << 16);
1221
1222         return 0;
1223 }
1224
1225 static int data_training(const struct chan_info *chan, u32 channel,
1226                          const struct rk3399_sdram_params *params,
1227                          u32 training_flag)
1228 {
1229         u32 *denali_phy = chan->publ->denali_phy;
1230         int ret;
1231
1232         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1233         setbits_le32(&denali_phy[927], (1 << 22));
1234
1235         if (training_flag == PI_FULL_TRAINING) {
1236                 if (params->base.dramtype == LPDDR4) {
1237                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1238                                         PI_READ_GATE_TRAINING |
1239                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
1240                 } else if (params->base.dramtype == LPDDR3) {
1241                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1242                                         PI_READ_GATE_TRAINING;
1243                 } else if (params->base.dramtype == DDR3) {
1244                         training_flag = PI_WRITE_LEVELING |
1245                                         PI_READ_GATE_TRAINING |
1246                                         PI_READ_LEVELING;
1247                 }
1248         }
1249
1250         /* ca training(LPDDR4,LPDDR3 support) */
1251         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
1252                 ret = data_training_ca(chan, channel, params);
1253                 if (ret < 0) {
1254                         debug("%s: data training ca failed\n", __func__);
1255                         return ret;
1256                 }
1257         }
1258
1259         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1260         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
1261                 ret = data_training_wl(chan, channel, params);
1262                 if (ret < 0) {
1263                         debug("%s: data training wl failed\n", __func__);
1264                         return ret;
1265                 }
1266         }
1267
1268         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1269         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
1270                 ret = data_training_rg(chan, channel, params);
1271                 if (ret < 0) {
1272                         debug("%s: data training rg failed\n", __func__);
1273                         return ret;
1274                 }
1275         }
1276
1277         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1278         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
1279                 ret = data_training_rl(chan, channel, params);
1280                 if (ret < 0) {
1281                         debug("%s: data training rl failed\n", __func__);
1282                         return ret;
1283                 }
1284         }
1285
1286         /* wdq leveling(LPDDR4 support) */
1287         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1288                 ret = data_training_wdql(chan, channel, params);
1289                 if (ret < 0) {
1290                         debug("%s: data training wdql failed\n", __func__);
1291                         return ret;
1292                 }
1293         }
1294
1295         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1296         clrbits_le32(&denali_phy[927], (1 << 22));
1297
1298         return 0;
1299 }
1300
1301 static void set_ddrconfig(const struct chan_info *chan,
1302                           const struct rk3399_sdram_params *params,
1303                           unsigned char channel, u32 ddrconfig)
1304 {
1305         /* only need to set ddrconfig */
1306         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
1307         unsigned int cs0_cap = 0;
1308         unsigned int cs1_cap = 0;
1309
1310         cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1311                         + params->ch[channel].cap_info.col
1312                         + params->ch[channel].cap_info.bk
1313                         + params->ch[channel].cap_info.bw - 20));
1314         if (params->ch[channel].cap_info.rank > 1)
1315                 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1316                                 - params->ch[channel].cap_info.cs1_row);
1317         if (params->ch[channel].cap_info.row_3_4) {
1318                 cs0_cap = cs0_cap * 3 / 4;
1319                 cs1_cap = cs1_cap * 3 / 4;
1320         }
1321
1322         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1323         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1324                &ddr_msch_regs->ddrsize);
1325 }
1326
1327 static void dram_all_config(struct dram_info *dram,
1328                             const struct rk3399_sdram_params *params)
1329 {
1330         u32 sys_reg2 = 0;
1331         u32 sys_reg3 = 0;
1332         unsigned int channel, idx;
1333
1334         sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
1335         sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
1336
1337         for (channel = 0, idx = 0;
1338              (idx < params->base.num_channels) && (channel < 2);
1339              channel++) {
1340                 const struct rk3399_sdram_channel *info = &params->ch[channel];
1341                 struct rk3399_msch_regs *ddr_msch_regs;
1342                 const struct rk3399_msch_timings *noc_timing;
1343
1344                 if (params->ch[channel].cap_info.col == 0)
1345                         continue;
1346                 idx++;
1347                 sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
1348                 sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
1349                 sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
1350                 sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
1351                 sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
1352                 sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
1353                 sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
1354                 SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
1355                 if (info->cap_info.cs1_row)
1356                         SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
1357                                             sys_reg3, channel);
1358                 sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
1359                 sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
1360
1361                 ddr_msch_regs = dram->chan[channel].msch;
1362                 noc_timing = &params->ch[channel].noc_timings;
1363                 writel(noc_timing->ddrtiminga0,
1364                        &ddr_msch_regs->ddrtiminga0);
1365                 writel(noc_timing->ddrtimingb0,
1366                        &ddr_msch_regs->ddrtimingb0);
1367                 writel(noc_timing->ddrtimingc0.d32,
1368                        &ddr_msch_regs->ddrtimingc0);
1369                 writel(noc_timing->devtodev0,
1370                        &ddr_msch_regs->devtodev0);
1371                 writel(noc_timing->ddrmode.d32,
1372                        &ddr_msch_regs->ddrmode);
1373
1374                 /**
1375                  * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
1376                  *
1377                  * The hardware for LPDDR4 with
1378                  * - CLK0P/N connect to lower 16-bits
1379                  * - CLK1P/N connect to higher 16-bits
1380                  *
1381                  * dfi dram clk is configured via CLK1P/N, so disabling
1382                  * dfi dram clk will disable the CLK1P/N as well for lpddr4.
1383                  */
1384                 if (params->ch[channel].cap_info.rank == 1 &&
1385                     params->base.dramtype != LPDDR4)
1386                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1387                                      1 << 17);
1388         }
1389
1390         writel(sys_reg2, &dram->pmugrf->os_reg2);
1391         writel(sys_reg3, &dram->pmugrf->os_reg3);
1392         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1393                      params->base.stride << 10);
1394
1395         /* reboot hold register set */
1396         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1397                 PRESET_GPIO1_HOLD(1),
1398                 &dram->pmucru->pmucru_rstnhold_con[1]);
1399         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1400 }
1401
1402 static int switch_to_phy_index1(struct dram_info *dram,
1403                                 const struct rk3399_sdram_params *params)
1404 {
1405         u32 channel;
1406         u32 *denali_phy;
1407         u32 ch_count = params->base.num_channels;
1408         int ret;
1409         int i = 0;
1410
1411         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1412                              1 << 4 | 1 << 2 | 1),
1413                         &dram->cic->cic_ctrl0);
1414         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1415                 mdelay(10);
1416                 i++;
1417                 if (i > 10) {
1418                         debug("index1 frequency change overtime\n");
1419                         return -ETIME;
1420                 }
1421         }
1422
1423         i = 0;
1424         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1425         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1426                 mdelay(10);
1427                 i++;
1428                 if (i > 10) {
1429                         debug("index1 frequency done overtime\n");
1430                         return -ETIME;
1431                 }
1432         }
1433
1434         for (channel = 0; channel < ch_count; channel++) {
1435                 denali_phy = dram->chan[channel].publ->denali_phy;
1436                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1437                 ret = data_training(&dram->chan[channel], channel,
1438                                     params, PI_FULL_TRAINING);
1439                 if (ret < 0) {
1440                         debug("index1 training failed\n");
1441                         return ret;
1442                 }
1443         }
1444
1445         return 0;
1446 }
1447
1448 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
1449 {
1450         unsigned int stride = params->base.stride;
1451         unsigned int channel, chinfo = 0;
1452         unsigned int ch_cap[2] = {0, 0};
1453         u64 cap;
1454
1455         for (channel = 0; channel < 2; channel++) {
1456                 unsigned int cs0_cap = 0;
1457                 unsigned int cs1_cap = 0;
1458                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
1459
1460                 if (cap_info->col == 0)
1461                         continue;
1462
1463                 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
1464                                  cap_info->bk + cap_info->bw - 20));
1465                 if (cap_info->rank > 1)
1466                         cs1_cap = cs0_cap >> (cap_info->cs0_row
1467                                               - cap_info->cs1_row);
1468                 if (cap_info->row_3_4) {
1469                         cs0_cap = cs0_cap * 3 / 4;
1470                         cs1_cap = cs1_cap * 3 / 4;
1471                 }
1472                 ch_cap[channel] = cs0_cap + cs1_cap;
1473                 chinfo |= 1 << channel;
1474         }
1475
1476         /* stride calculation for 1 channel */
1477         if (params->base.num_channels == 1 && chinfo & 1)
1478                 return 0x17;    /* channel a */
1479
1480         /* stride calculation for 2 channels, default gstride type is 256B */
1481         if (ch_cap[0] == ch_cap[1]) {
1482                 cap = ch_cap[0] + ch_cap[1];
1483                 switch (cap) {
1484                 /* 512MB */
1485                 case 512:
1486                         stride = 0;
1487                         break;
1488                 /* 1GB */
1489                 case 1024:
1490                         stride = 0x5;
1491                         break;
1492                 /*
1493                  * 768MB + 768MB same as total 2GB memory
1494                  * useful space: 0-768MB 1GB-1792MB
1495                  */
1496                 case 1536:
1497                 /* 2GB */
1498                 case 2048:
1499                         stride = 0x9;
1500                         break;
1501                 /* 1536MB + 1536MB */
1502                 case 3072:
1503                         stride = 0x11;
1504                         break;
1505                 /* 4GB */
1506                 case 4096:
1507                         stride = 0xD;
1508                         break;
1509                 default:
1510                         printf("%s: Unable to calculate stride for ", __func__);
1511                         print_size((cap * (1 << 20)), " capacity\n");
1512                         break;
1513                 }
1514         }
1515
1516         sdram_print_stride(stride);
1517
1518         return stride;
1519 }
1520
1521 static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
1522 {
1523         params->ch[channel].cap_info.rank = 0;
1524         params->ch[channel].cap_info.col = 0;
1525         params->ch[channel].cap_info.bk = 0;
1526         params->ch[channel].cap_info.bw = 32;
1527         params->ch[channel].cap_info.dbw = 32;
1528         params->ch[channel].cap_info.row_3_4 = 0;
1529         params->ch[channel].cap_info.cs0_row = 0;
1530         params->ch[channel].cap_info.cs1_row = 0;
1531         params->ch[channel].cap_info.ddrconfig = 0;
1532 }
1533
1534 static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
1535 {
1536         int channel;
1537         int ret;
1538
1539         for (channel = 0; channel < 2; channel++) {
1540                 const struct chan_info *chan = &dram->chan[channel];
1541                 struct rk3399_cru *cru = dram->cru;
1542                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1543
1544                 phy_pctrl_reset(cru, channel);
1545                 phy_dll_bypass_set(publ, params->base.ddr_freq);
1546
1547                 ret = pctl_cfg(dram, chan, channel, params);
1548                 if (ret < 0) {
1549                         printf("%s: pctl config failed\n", __func__);
1550                         return ret;
1551                 }
1552
1553                 /* start to trigger initialization */
1554                 pctl_start(dram, channel);
1555         }
1556
1557         return 0;
1558 }
1559
1560 static int sdram_init(struct dram_info *dram,
1561                       struct rk3399_sdram_params *params)
1562 {
1563         unsigned char dramtype = params->base.dramtype;
1564         unsigned int ddr_freq = params->base.ddr_freq;
1565         u32 training_flag = PI_READ_GATE_TRAINING;
1566         int channel, ch, rank;
1567         int ret;
1568
1569         debug("Starting SDRAM initialization...\n");
1570
1571         if ((dramtype == DDR3 && ddr_freq > 933) ||
1572             (dramtype == LPDDR3 && ddr_freq > 933) ||
1573             (dramtype == LPDDR4 && ddr_freq > 800)) {
1574                 debug("SDRAM frequency is to high!");
1575                 return -E2BIG;
1576         }
1577
1578         for (ch = 0; ch < 2; ch++) {
1579                 params->ch[ch].cap_info.rank = 2;
1580                 for (rank = 2; rank != 0; rank--) {
1581                         ret = pctl_init(dram, params);
1582                         if (ret < 0) {
1583                                 printf("%s: pctl init failed\n", __func__);
1584                                 return ret;
1585                         }
1586
1587                         /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1588                         if (dramtype == LPDDR3)
1589                                 udelay(10);
1590
1591                         params->ch[ch].cap_info.rank = rank;
1592
1593                         /*
1594                          * LPDDR3 CA training msut be trigger before
1595                          * other training.
1596                          * DDR3 is not have CA training.
1597                          */
1598                         if (params->base.dramtype == LPDDR3)
1599                                 training_flag |= PI_CA_TRAINING;
1600
1601                         if (!(data_training(&dram->chan[ch], ch,
1602                                             params, training_flag)))
1603                                 break;
1604                 }
1605                 /* Computed rank with associated channel number */
1606                 params->ch[ch].cap_info.rank = rank;
1607         }
1608
1609         params->base.num_channels = 0;
1610         for (channel = 0; channel < 2; channel++) {
1611                 const struct chan_info *chan = &dram->chan[channel];
1612                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
1613                 u8 training_flag = PI_FULL_TRAINING;
1614
1615                 if (cap_info->rank == 0) {
1616                         clear_channel_params(params, channel);
1617                         continue;
1618                 } else {
1619                         params->base.num_channels++;
1620                 }
1621
1622                 debug("Channel ");
1623                 debug(channel ? "1: " : "0: ");
1624
1625                 /* LPDDR3 should have write and read gate training */
1626                 if (params->base.dramtype == LPDDR3)
1627                         training_flag = PI_WRITE_LEVELING |
1628                                         PI_READ_GATE_TRAINING;
1629
1630                 if (params->base.dramtype != LPDDR4) {
1631                         ret = data_training(dram, channel, params,
1632                                             training_flag);
1633                         if (!ret) {
1634                                 debug("%s: data train failed for channel %d\n",
1635                                       __func__, ret);
1636                                 continue;
1637                         }
1638                 }
1639
1640                 sdram_print_ddr_info(cap_info, &params->base);
1641
1642                 set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
1643         }
1644
1645         if (params->base.num_channels == 0) {
1646                 printf("%s: ", __func__);
1647                 sdram_print_dram_type(params->base.dramtype);
1648                 printf(" - %dMHz failed!\n", params->base.ddr_freq);
1649                 return -EINVAL;
1650         }
1651
1652         params->base.stride = calculate_stride(params);
1653         dram_all_config(dram, params);
1654         switch_to_phy_index1(dram, params);
1655
1656         debug("Finish SDRAM initialization...\n");
1657         return 0;
1658 }
1659
1660 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1661 {
1662 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1663         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1664         int ret;
1665
1666         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1667                                  (u32 *)&plat->sdram_params,
1668                                  sizeof(plat->sdram_params) / sizeof(u32));
1669         if (ret) {
1670                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1671                        __func__, ret);
1672                 return ret;
1673         }
1674         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1675         if (ret)
1676                 printf("%s: regmap failed %d\n", __func__, ret);
1677
1678 #endif
1679         return 0;
1680 }
1681
1682 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1683 static int conv_of_platdata(struct udevice *dev)
1684 {
1685         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1686         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1687         int ret;
1688
1689         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1690                                        ARRAY_SIZE(dtplat->reg) / 2,
1691                                        &plat->map);
1692         if (ret)
1693                 return ret;
1694
1695         return 0;
1696 }
1697 #endif
1698
1699 static int rk3399_dmc_init(struct udevice *dev)
1700 {
1701         struct dram_info *priv = dev_get_priv(dev);
1702         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1703         int ret;
1704 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1705         struct rk3399_sdram_params *params = &plat->sdram_params;
1706 #else
1707         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1708         struct rk3399_sdram_params *params =
1709                                         (void *)dtplat->rockchip_sdram_params;
1710
1711         ret = conv_of_platdata(dev);
1712         if (ret)
1713                 return ret;
1714 #endif
1715
1716         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1717         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1718         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1719         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1720         priv->pmucru = rockchip_get_pmucru();
1721         priv->cru = rockchip_get_cru();
1722         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1723         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1724         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1725         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1726         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1727         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1728         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1729         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1730
1731         debug("con reg %p %p %p %p %p %p %p %p\n",
1732               priv->chan[0].pctl, priv->chan[0].pi,
1733               priv->chan[0].publ, priv->chan[0].msch,
1734               priv->chan[1].pctl, priv->chan[1].pi,
1735               priv->chan[1].publ, priv->chan[1].msch);
1736         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1737               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1738
1739 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1740         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1741 #else
1742         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1743 #endif
1744         if (ret) {
1745                 printf("%s clk get failed %d\n", __func__, ret);
1746                 return ret;
1747         }
1748
1749         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1750         if (ret < 0) {
1751                 printf("%s clk set failed %d\n", __func__, ret);
1752                 return ret;
1753         }
1754
1755         ret = sdram_init(priv, params);
1756         if (ret < 0) {
1757                 printf("%s DRAM init failed %d\n", __func__, ret);
1758                 return ret;
1759         }
1760
1761         return 0;
1762 }
1763 #endif
1764
1765 static int rk3399_dmc_probe(struct udevice *dev)
1766 {
1767 #if defined(CONFIG_TPL_BUILD) || \
1768         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1769         if (rk3399_dmc_init(dev))
1770                 return 0;
1771 #else
1772         struct dram_info *priv = dev_get_priv(dev);
1773
1774         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1775         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1776         priv->info.base = CONFIG_SYS_SDRAM_BASE;
1777         priv->info.size =
1778                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1779 #endif
1780         return 0;
1781 }
1782
1783 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1784 {
1785         struct dram_info *priv = dev_get_priv(dev);
1786
1787         *info = priv->info;
1788
1789         return 0;
1790 }
1791
1792 static struct ram_ops rk3399_dmc_ops = {
1793         .get_info = rk3399_dmc_get_info,
1794 };
1795
1796 static const struct udevice_id rk3399_dmc_ids[] = {
1797         { .compatible = "rockchip,rk3399-dmc" },
1798         { }
1799 };
1800
1801 U_BOOT_DRIVER(dmc_rk3399) = {
1802         .name = "rockchip_rk3399_dmc",
1803         .id = UCLASS_RAM,
1804         .of_match = rk3399_dmc_ids,
1805         .ops = &rk3399_dmc_ops,
1806 #if defined(CONFIG_TPL_BUILD) || \
1807         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1808         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1809 #endif
1810         .probe = rk3399_dmc_probe,
1811         .priv_auto_alloc_size = sizeof(struct dram_info),
1812 #if defined(CONFIG_TPL_BUILD) || \
1813         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1814         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1815 #endif
1816 };