1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * (C) Copyright 2016-2017 Rockchip Inc.
5 * Adapted from coreboot.
11 #include <dt-structs.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/cru_rk3399.h>
18 #include <asm/arch-rockchip/grf_rk3399.h>
19 #include <asm/arch-rockchip/hardware.h>
20 #include <asm/arch-rockchip/sdram_common.h>
21 #include <asm/arch-rockchip/sdram_rk3399.h>
22 #include <linux/err.h>
25 #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
26 #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
27 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
29 #define PHY_DRV_ODT_HI_Z 0x0
30 #define PHY_DRV_ODT_240 0x1
31 #define PHY_DRV_ODT_120 0x8
32 #define PHY_DRV_ODT_80 0x9
33 #define PHY_DRV_ODT_60 0xc
34 #define PHY_DRV_ODT_48 0xd
35 #define PHY_DRV_ODT_40 0xe
36 #define PHY_DRV_ODT_34_3 0xf
38 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
39 ((n) << (8 + (ch) * 4)))
40 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
41 ((n) << (9 + (ch) * 4)))
43 struct rk3399_ddr_pctl_regs *pctl;
44 struct rk3399_ddr_pi_regs *pi;
45 struct rk3399_ddr_publ_regs *publ;
46 struct rk3399_msch_regs *msch;
50 #if defined(CONFIG_TPL_BUILD) || \
51 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
52 u32 pwrup_srefresh_exit[2];
53 struct chan_info chan[2];
55 struct rk3399_cru *cru;
56 struct rk3399_grf_regs *grf;
57 struct rk3399_pmucru *pmucru;
58 struct rk3399_pmusgrf_regs *pmusgrf;
59 struct rk3399_ddr_cic_regs *cic;
62 struct rk3399_pmugrf_regs *pmugrf;
65 #if defined(CONFIG_TPL_BUILD) || \
66 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
68 struct rockchip_dmc_plat {
69 #if CONFIG_IS_ENABLED(OF_PLATDATA)
70 struct dtd_rockchip_rk3399_dmc dtplat;
72 struct rk3399_sdram_params sdram_params;
77 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
79 return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
82 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
86 for (i = 0; i < n / sizeof(u32); i++) {
93 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
99 writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
100 CRU_SFTRST_DDR_PHY(channel, phy),
101 &cru->softrst_con[4]);
104 static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
106 rkclk_ddr_reset(cru, channel, 1, 1);
109 rkclk_ddr_reset(cru, channel, 1, 0);
112 rkclk_ddr_reset(cru, channel, 0, 0);
116 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
119 u32 *denali_phy = ddr_publ_regs->denali_phy;
121 /* From IP spec, only freq small than 125 can enter dll bypass mode */
123 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
124 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
125 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
126 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
127 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
129 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
130 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
131 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
132 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
134 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
135 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
136 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
137 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
138 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
140 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
141 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
142 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
143 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
147 static void set_memory_map(const struct chan_info *chan, u32 channel,
148 const struct rk3399_sdram_params *params)
150 const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel];
151 u32 *denali_ctl = chan->pctl->denali_ctl;
152 u32 *denali_pi = chan->pi->denali_pi;
157 /* Get row number from ddrconfig setting */
158 if (sdram_ch->cap_info.ddrconfig < 2 ||
159 sdram_ch->cap_info.ddrconfig == 4)
161 else if (sdram_ch->cap_info.ddrconfig == 3)
166 cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
167 reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
169 /* Set the dram configuration to ctrl */
170 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
171 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
172 ((3 - sdram_ch->cap_info.bk) << 16) |
175 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
176 cs_map | (reduc << 16));
178 /* PI_199 PI_COL_DIFF:RW:0:4 */
179 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
181 /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
182 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
183 ((3 - sdram_ch->cap_info.bk) << 16) |
185 /* PI_41 PI_CS_MAP:RW:24:4 */
186 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
187 if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
188 writel(0x2EC7FFFF, &denali_pi[34]);
191 static void set_ds_odt(const struct chan_info *chan,
192 const struct rk3399_sdram_params *params)
194 u32 *denali_phy = chan->publ->denali_phy;
196 u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
197 u32 tsel_idle_select_p, tsel_rd_select_p;
198 u32 tsel_idle_select_n, tsel_rd_select_n;
199 u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
200 u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
203 if (params->base.dramtype == LPDDR4) {
204 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
205 tsel_rd_select_n = PHY_DRV_ODT_240;
207 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
208 tsel_idle_select_n = PHY_DRV_ODT_240;
210 tsel_wr_select_dq_p = PHY_DRV_ODT_40;
211 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
213 tsel_wr_select_ca_p = PHY_DRV_ODT_40;
214 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
215 } else if (params->base.dramtype == LPDDR3) {
216 tsel_rd_select_p = PHY_DRV_ODT_240;
217 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
219 tsel_idle_select_p = PHY_DRV_ODT_240;
220 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
222 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
223 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
225 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
226 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
228 tsel_rd_select_p = PHY_DRV_ODT_240;
229 tsel_rd_select_n = PHY_DRV_ODT_240;
231 tsel_idle_select_p = PHY_DRV_ODT_240;
232 tsel_idle_select_n = PHY_DRV_ODT_240;
234 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
235 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
237 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
238 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
241 if (params->base.odt == 1)
250 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
251 * sets termination values for read/idle cycles and drive strength
252 * for write cycles for DQ/DM
254 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
255 (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
256 (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
257 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
258 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
259 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
260 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
263 * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
264 * sets termination values for read/idle cycles and drive strength
265 * for write cycles for DQS
267 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
268 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
269 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
270 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
272 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
273 reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
274 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
275 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
276 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
278 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
279 clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
281 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
282 clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
284 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
285 clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
287 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
288 clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
290 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
291 clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
293 /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
294 clrsetbits_le32(&denali_phy[924], 0xff,
295 tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
296 clrsetbits_le32(&denali_phy[925], 0xff,
297 tsel_rd_select_n | (tsel_rd_select_p << 4));
299 /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
300 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
302 clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
303 clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
304 clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
305 clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
307 /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
308 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
310 clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
311 clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
312 clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
313 clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
315 /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
316 reg_value = tsel_wr_en << 8;
317 clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
318 clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
319 clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
321 /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
322 reg_value = tsel_wr_en << 17;
323 clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
325 * pad_rst/cke/cs/clk_term tsel 1bits
326 * DENALI_PHY_938/936/940/934 offset_17
328 clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
329 clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
330 clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
331 clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
333 /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
334 clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
337 static void pctl_start(struct dram_info *dram, u8 channel)
339 const struct chan_info *chan = &dram->chan[channel];
340 u32 *denali_ctl = chan->pctl->denali_ctl;
341 u32 *denali_phy = chan->publ->denali_phy;
342 u32 *ddrc0_con = get_ddrc0_con(dram, channel);
346 writel(0x01000000, &ddrc0_con);
348 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
350 while (!(readl(&denali_ctl[203]) & (1 << 3))) {
352 printf("%s: Failed to init pctl for channel %d\n",
362 writel(0x01000100, &ddrc0_con);
364 for (byte = 0; byte < 4; byte++) {
366 writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
367 writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
368 writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
369 writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
370 writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
372 clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
375 clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
376 dram->pwrup_srefresh_exit[channel]);
379 static int phy_io_config(const struct chan_info *chan,
380 const struct rk3399_sdram_params *params)
382 u32 *denali_phy = chan->publ->denali_phy;
383 u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
386 u32 drv_value, odt_value;
390 if (params->base.dramtype == LPDDR4) {
393 vref_value_dq = 0x1f;
395 vref_value_ac = 0x1f;
396 } else if (params->base.dramtype == LPDDR3) {
397 if (params->base.odt == 1) {
398 vref_mode_dq = 0x5; /* LPDDR3 ODT */
399 drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
400 odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
401 if (drv_value == PHY_DRV_ODT_48) {
403 case PHY_DRV_ODT_240:
404 vref_value_dq = 0x16;
406 case PHY_DRV_ODT_120:
407 vref_value_dq = 0x26;
410 vref_value_dq = 0x36;
413 debug("Invalid ODT value.\n");
416 } else if (drv_value == PHY_DRV_ODT_40) {
418 case PHY_DRV_ODT_240:
419 vref_value_dq = 0x19;
421 case PHY_DRV_ODT_120:
422 vref_value_dq = 0x23;
425 vref_value_dq = 0x31;
428 debug("Invalid ODT value.\n");
431 } else if (drv_value == PHY_DRV_ODT_34_3) {
433 case PHY_DRV_ODT_240:
434 vref_value_dq = 0x17;
436 case PHY_DRV_ODT_120:
437 vref_value_dq = 0x20;
440 vref_value_dq = 0x2e;
443 debug("Invalid ODT value.\n");
447 debug("Invalid DRV value.\n");
451 vref_mode_dq = 0x2; /* LPDDR3 */
452 vref_value_dq = 0x1f;
455 vref_value_ac = 0x1f;
456 } else if (params->base.dramtype == DDR3) {
459 vref_value_dq = 0x1f;
461 vref_value_ac = 0x1f;
463 debug("Unknown DRAM type.\n");
467 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
469 /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
470 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
471 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
472 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
473 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
474 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
475 /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
476 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
478 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
480 /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
481 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
483 if (params->base.dramtype == LPDDR4)
485 else if (params->base.dramtype == LPDDR3)
487 else if (params->base.dramtype == DDR3)
492 /* PHY_924 PHY_PAD_FDBK_DRIVE */
493 clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
494 /* PHY_926 PHY_PAD_DATA_DRIVE */
495 clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
496 /* PHY_927 PHY_PAD_DQS_DRIVE */
497 clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
498 /* PHY_928 PHY_PAD_ADDR_DRIVE */
499 clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
500 /* PHY_929 PHY_PAD_CLK_DRIVE */
501 clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
502 /* PHY_935 PHY_PAD_CKE_DRIVE */
503 clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
504 /* PHY_937 PHY_PAD_RST_DRIVE */
505 clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
506 /* PHY_939 PHY_PAD_CS_DRIVE */
507 clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
510 if (params->base.ddr_freq < 400)
512 else if (params->base.ddr_freq < 800)
514 else if (params->base.ddr_freq < 1200)
519 /* PHY_924 PHY_PAD_FDBK_DRIVE */
520 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
521 /* PHY_926 PHY_PAD_DATA_DRIVE */
522 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
523 /* PHY_927 PHY_PAD_DQS_DRIVE */
524 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
525 /* PHY_928 PHY_PAD_ADDR_DRIVE */
526 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
527 /* PHY_929 PHY_PAD_CLK_DRIVE */
528 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
529 /* PHY_935 PHY_PAD_CKE_DRIVE */
530 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
531 /* PHY_937 PHY_PAD_RST_DRIVE */
532 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
533 /* PHY_939 PHY_PAD_CS_DRIVE */
534 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
539 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
540 u32 channel, const struct rk3399_sdram_params *params)
542 u32 *denali_ctl = chan->pctl->denali_ctl;
543 u32 *denali_pi = chan->pi->denali_pi;
544 u32 *denali_phy = chan->publ->denali_phy;
545 const u32 *params_ctl = params->pctl_regs.denali_ctl;
546 const u32 *params_phy = params->phy_regs.denali_phy;
551 * work around controller bug:
552 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
554 copy_to_reg(&denali_ctl[1], ¶ms_ctl[1],
555 sizeof(struct rk3399_ddr_pctl_regs) - 4);
556 writel(params_ctl[0], &denali_ctl[0]);
558 copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0],
559 sizeof(struct rk3399_ddr_pi_regs));
561 /* rank count need to set for init */
562 set_memory_map(chan, channel, params);
564 writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
565 writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
566 writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
568 dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
570 clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
573 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
575 setbits_le32(&denali_pi[0], START);
576 setbits_le32(&denali_ctl[0], START);
578 /* Waiting for phy DLL lock */
580 tmp = readl(&denali_phy[920]);
581 tmp1 = readl(&denali_phy[921]);
582 tmp2 = readl(&denali_phy[922]);
583 if ((((tmp >> 16) & 0x1) == 0x1) &&
584 (((tmp1 >> 16) & 0x1) == 0x1) &&
585 (((tmp1 >> 0) & 0x1) == 0x1) &&
586 (((tmp2 >> 0) & 0x1) == 0x1))
590 copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4);
591 copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4);
592 copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4);
593 copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4);
594 copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4);
595 copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);
596 copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);
597 copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);
598 set_ds_odt(chan, params);
601 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
602 * dqs_tsel_wr_end[7:4] add Half cycle
604 tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
605 clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
606 tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
607 clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
608 tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
609 clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
610 tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
611 clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
614 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
615 * dq_tsel_wr_end[7:4] add Half cycle
617 tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
618 clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
619 tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
620 clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
621 tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
622 clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
623 tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
624 clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
626 ret = phy_io_config(chan, params);
633 static void select_per_cs_training_index(const struct chan_info *chan,
636 u32 *denali_phy = chan->publ->denali_phy;
638 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
639 if ((readl(&denali_phy[84]) >> 16) & 1) {
642 * phy_per_cs_training_index_X 1bit offset_24
644 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
645 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
646 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
647 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
651 static void override_write_leveling_value(const struct chan_info *chan)
653 u32 *denali_ctl = chan->pctl->denali_ctl;
654 u32 *denali_phy = chan->publ->denali_phy;
657 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
658 setbits_le32(&denali_phy[896], 1);
662 * phy_per_cs_training_multicast_en_X 1bit offset_16
664 clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
665 clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
666 clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
667 clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
669 for (byte = 0; byte < 4; byte++)
670 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
673 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
674 clrbits_le32(&denali_phy[896], 1);
676 /* CTL_200 ctrlupd_req 1bit offset_8 */
677 clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
680 static int data_training_ca(const struct chan_info *chan, u32 channel,
681 const struct rk3399_sdram_params *params)
683 u32 *denali_pi = chan->pi->denali_pi;
684 u32 *denali_phy = chan->publ->denali_phy;
686 u32 obs_0, obs_1, obs_2, obs_err = 0;
687 u32 rank = params->ch[channel].cap_info.rank;
690 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
691 writel(0x00003f7c, (&denali_pi[175]));
693 rank_mask = (rank == 1) ? 0x1 : 0x3;
695 for (i = 0; i < 4; i++) {
696 if (!(rank_mask & (1 << i)))
699 select_per_cs_training_index(chan, i);
701 /* PI_100 PI_CALVL_EN:RW:8:2 */
702 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
704 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
705 clrsetbits_le32(&denali_pi[92],
706 (0x1 << 16) | (0x3 << 24),
707 (0x1 << 16) | (i << 24));
709 /* Waiting for training complete */
711 /* PI_174 PI_INT_STATUS:RD:8:18 */
712 tmp = readl(&denali_pi[174]) >> 8;
715 * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
717 obs_0 = readl(&denali_phy[532]);
718 obs_1 = readl(&denali_phy[660]);
719 obs_2 = readl(&denali_phy[788]);
720 if (((obs_0 >> 30) & 0x3) ||
721 ((obs_1 >> 30) & 0x3) ||
722 ((obs_2 >> 30) & 0x3))
724 if ((((tmp >> 11) & 0x1) == 0x1) &&
725 (((tmp >> 13) & 0x1) == 0x1) &&
726 (((tmp >> 5) & 0x1) == 0x0) &&
729 else if ((((tmp >> 5) & 0x1) == 0x1) ||
734 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
735 writel(0x00003f7c, (&denali_pi[175]));
738 clrbits_le32(&denali_pi[100], 0x3 << 8);
743 static int data_training_wl(const struct chan_info *chan, u32 channel,
744 const struct rk3399_sdram_params *params)
746 u32 *denali_pi = chan->pi->denali_pi;
747 u32 *denali_phy = chan->publ->denali_phy;
749 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
750 u32 rank = params->ch[channel].cap_info.rank;
752 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
753 writel(0x00003f7c, (&denali_pi[175]));
755 for (i = 0; i < rank; i++) {
756 select_per_cs_training_index(chan, i);
758 /* PI_60 PI_WRLVL_EN:RW:8:2 */
759 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
761 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
762 clrsetbits_le32(&denali_pi[59],
763 (0x1 << 8) | (0x3 << 16),
764 (0x1 << 8) | (i << 16));
766 /* Waiting for training complete */
768 /* PI_174 PI_INT_STATUS:RD:8:18 */
769 tmp = readl(&denali_pi[174]) >> 8;
772 * check status obs, if error maybe can not
773 * get leveling done PHY_40/168/296/424
774 * phy_wrlvl_status_obs_X:0:13
776 obs_0 = readl(&denali_phy[40]);
777 obs_1 = readl(&denali_phy[168]);
778 obs_2 = readl(&denali_phy[296]);
779 obs_3 = readl(&denali_phy[424]);
780 if (((obs_0 >> 12) & 0x1) ||
781 ((obs_1 >> 12) & 0x1) ||
782 ((obs_2 >> 12) & 0x1) ||
783 ((obs_3 >> 12) & 0x1))
785 if ((((tmp >> 10) & 0x1) == 0x1) &&
786 (((tmp >> 13) & 0x1) == 0x1) &&
787 (((tmp >> 4) & 0x1) == 0x0) &&
790 else if ((((tmp >> 4) & 0x1) == 0x1) ||
795 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
796 writel(0x00003f7c, (&denali_pi[175]));
799 override_write_leveling_value(chan);
800 clrbits_le32(&denali_pi[60], 0x3 << 8);
805 static int data_training_rg(const struct chan_info *chan, u32 channel,
806 const struct rk3399_sdram_params *params)
808 u32 *denali_pi = chan->pi->denali_pi;
809 u32 *denali_phy = chan->publ->denali_phy;
811 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
812 u32 rank = params->ch[channel].cap_info.rank;
814 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
815 writel(0x00003f7c, (&denali_pi[175]));
817 for (i = 0; i < rank; i++) {
818 select_per_cs_training_index(chan, i);
820 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
821 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
824 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
825 * PI_RDLVL_CS:RW:24:2
827 clrsetbits_le32(&denali_pi[74],
828 (0x1 << 16) | (0x3 << 24),
829 (0x1 << 16) | (i << 24));
831 /* Waiting for training complete */
833 /* PI_174 PI_INT_STATUS:RD:8:18 */
834 tmp = readl(&denali_pi[174]) >> 8;
839 * PHY_GTLVL_STATUS_OBS_x:16:8
841 obs_0 = readl(&denali_phy[43]);
842 obs_1 = readl(&denali_phy[171]);
843 obs_2 = readl(&denali_phy[299]);
844 obs_3 = readl(&denali_phy[427]);
845 if (((obs_0 >> (16 + 6)) & 0x3) ||
846 ((obs_1 >> (16 + 6)) & 0x3) ||
847 ((obs_2 >> (16 + 6)) & 0x3) ||
848 ((obs_3 >> (16 + 6)) & 0x3))
850 if ((((tmp >> 9) & 0x1) == 0x1) &&
851 (((tmp >> 13) & 0x1) == 0x1) &&
852 (((tmp >> 3) & 0x1) == 0x0) &&
855 else if ((((tmp >> 3) & 0x1) == 0x1) ||
860 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
861 writel(0x00003f7c, (&denali_pi[175]));
864 clrbits_le32(&denali_pi[80], 0x3 << 24);
869 static int data_training_rl(const struct chan_info *chan, u32 channel,
870 const struct rk3399_sdram_params *params)
872 u32 *denali_pi = chan->pi->denali_pi;
874 u32 rank = params->ch[channel].cap_info.rank;
876 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
877 writel(0x00003f7c, (&denali_pi[175]));
879 for (i = 0; i < rank; i++) {
880 select_per_cs_training_index(chan, i);
882 /* PI_80 PI_RDLVL_EN:RW:16:2 */
883 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
885 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
886 clrsetbits_le32(&denali_pi[74],
887 (0x1 << 8) | (0x3 << 24),
888 (0x1 << 8) | (i << 24));
890 /* Waiting for training complete */
892 /* PI_174 PI_INT_STATUS:RD:8:18 */
893 tmp = readl(&denali_pi[174]) >> 8;
896 * make sure status obs not report error bit
898 * phy_rdlvl_status_obs_X:16:8
900 if ((((tmp >> 8) & 0x1) == 0x1) &&
901 (((tmp >> 13) & 0x1) == 0x1) &&
902 (((tmp >> 2) & 0x1) == 0x0))
904 else if (((tmp >> 2) & 0x1) == 0x1)
908 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
909 writel(0x00003f7c, (&denali_pi[175]));
912 clrbits_le32(&denali_pi[80], 0x3 << 16);
917 static int data_training_wdql(const struct chan_info *chan, u32 channel,
918 const struct rk3399_sdram_params *params)
920 u32 *denali_pi = chan->pi->denali_pi;
922 u32 rank = params->ch[channel].cap_info.rank;
925 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
926 writel(0x00003f7c, (&denali_pi[175]));
928 rank_mask = (rank == 1) ? 0x1 : 0x3;
930 for (i = 0; i < 4; i++) {
931 if (!(rank_mask & (1 << i)))
934 select_per_cs_training_index(chan, i);
937 * disable PI_WDQLVL_VREF_EN before wdq leveling?
938 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
940 clrbits_le32(&denali_pi[181], 0x1 << 8);
942 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
943 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
945 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
946 clrsetbits_le32(&denali_pi[121],
947 (0x1 << 8) | (0x3 << 16),
948 (0x1 << 8) | (i << 16));
950 /* Waiting for training complete */
952 /* PI_174 PI_INT_STATUS:RD:8:18 */
953 tmp = readl(&denali_pi[174]) >> 8;
954 if ((((tmp >> 12) & 0x1) == 0x1) &&
955 (((tmp >> 13) & 0x1) == 0x1) &&
956 (((tmp >> 6) & 0x1) == 0x0))
958 else if (((tmp >> 6) & 0x1) == 0x1)
962 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
963 writel(0x00003f7c, (&denali_pi[175]));
966 clrbits_le32(&denali_pi[124], 0x3 << 16);
971 static int data_training(const struct chan_info *chan, u32 channel,
972 const struct rk3399_sdram_params *params,
975 u32 *denali_phy = chan->publ->denali_phy;
978 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
979 setbits_le32(&denali_phy[927], (1 << 22));
981 if (training_flag == PI_FULL_TRAINING) {
982 if (params->base.dramtype == LPDDR4) {
983 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
984 PI_READ_GATE_TRAINING |
985 PI_READ_LEVELING | PI_WDQ_LEVELING;
986 } else if (params->base.dramtype == LPDDR3) {
987 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
988 PI_READ_GATE_TRAINING;
989 } else if (params->base.dramtype == DDR3) {
990 training_flag = PI_WRITE_LEVELING |
991 PI_READ_GATE_TRAINING |
996 /* ca training(LPDDR4,LPDDR3 support) */
997 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
998 ret = data_training_ca(chan, channel, params);
1000 debug("%s: data training ca failed\n", __func__);
1005 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1006 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
1007 ret = data_training_wl(chan, channel, params);
1009 debug("%s: data training wl failed\n", __func__);
1014 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1015 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
1016 ret = data_training_rg(chan, channel, params);
1018 debug("%s: data training rg failed\n", __func__);
1023 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1024 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
1025 ret = data_training_rl(chan, channel, params);
1027 debug("%s: data training rl failed\n", __func__);
1032 /* wdq leveling(LPDDR4 support) */
1033 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1034 ret = data_training_wdql(chan, channel, params);
1036 debug("%s: data training wdql failed\n", __func__);
1041 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
1042 clrbits_le32(&denali_phy[927], (1 << 22));
1047 static void set_ddrconfig(const struct chan_info *chan,
1048 const struct rk3399_sdram_params *params,
1049 unsigned char channel, u32 ddrconfig)
1051 /* only need to set ddrconfig */
1052 struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
1053 unsigned int cs0_cap = 0;
1054 unsigned int cs1_cap = 0;
1056 cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1057 + params->ch[channel].cap_info.col
1058 + params->ch[channel].cap_info.bk
1059 + params->ch[channel].cap_info.bw - 20));
1060 if (params->ch[channel].cap_info.rank > 1)
1061 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1062 - params->ch[channel].cap_info.cs1_row);
1063 if (params->ch[channel].cap_info.row_3_4) {
1064 cs0_cap = cs0_cap * 3 / 4;
1065 cs1_cap = cs1_cap * 3 / 4;
1068 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1069 writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1070 &ddr_msch_regs->ddrsize);
1073 static void dram_all_config(struct dram_info *dram,
1074 const struct rk3399_sdram_params *params)
1077 unsigned int channel, idx;
1079 sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
1080 sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
1082 for (channel = 0, idx = 0;
1083 (idx < params->base.num_channels) && (channel < 2);
1085 const struct rk3399_sdram_channel *info = ¶ms->ch[channel];
1086 struct rk3399_msch_regs *ddr_msch_regs;
1087 const struct rk3399_msch_timings *noc_timing;
1089 if (params->ch[channel].cap_info.col == 0)
1092 sys_reg |= info->cap_info.row_3_4 <<
1093 SYS_REG_ROW_3_4_SHIFT(channel);
1094 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
1095 sys_reg |= (info->cap_info.rank - 1) <<
1096 SYS_REG_RANK_SHIFT(channel);
1097 sys_reg |= (info->cap_info.col - 9) <<
1098 SYS_REG_COL_SHIFT(channel);
1099 sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
1100 SYS_REG_BK_SHIFT(channel);
1101 sys_reg |= (info->cap_info.cs0_row - 13) <<
1102 SYS_REG_CS0_ROW_SHIFT(channel);
1103 sys_reg |= (info->cap_info.cs1_row - 13) <<
1104 SYS_REG_CS1_ROW_SHIFT(channel);
1105 sys_reg |= (2 >> info->cap_info.bw) <<
1106 SYS_REG_BW_SHIFT(channel);
1107 sys_reg |= (2 >> info->cap_info.dbw) <<
1108 SYS_REG_DBW_SHIFT(channel);
1110 ddr_msch_regs = dram->chan[channel].msch;
1111 noc_timing = ¶ms->ch[channel].noc_timings;
1112 writel(noc_timing->ddrtiminga0,
1113 &ddr_msch_regs->ddrtiminga0);
1114 writel(noc_timing->ddrtimingb0,
1115 &ddr_msch_regs->ddrtimingb0);
1116 writel(noc_timing->ddrtimingc0,
1117 &ddr_msch_regs->ddrtimingc0);
1118 writel(noc_timing->devtodev0,
1119 &ddr_msch_regs->devtodev0);
1120 writel(noc_timing->ddrmode,
1121 &ddr_msch_regs->ddrmode);
1123 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1124 if (params->ch[channel].cap_info.rank == 1)
1125 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1129 writel(sys_reg, &dram->pmugrf->os_reg2);
1130 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1131 params->base.stride << 10);
1133 /* reboot hold register set */
1134 writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1135 PRESET_GPIO1_HOLD(1),
1136 &dram->pmucru->pmucru_rstnhold_con[1]);
1137 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1140 static int switch_to_phy_index1(struct dram_info *dram,
1141 const struct rk3399_sdram_params *params)
1145 u32 ch_count = params->base.num_channels;
1149 writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1150 1 << 4 | 1 << 2 | 1),
1151 &dram->cic->cic_ctrl0);
1152 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1156 debug("index1 frequency change overtime\n");
1162 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1163 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1167 debug("index1 frequency done overtime\n");
1172 for (channel = 0; channel < ch_count; channel++) {
1173 denali_phy = dram->chan[channel].publ->denali_phy;
1174 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1175 ret = data_training(&dram->chan[channel], channel,
1176 params, PI_FULL_TRAINING);
1178 debug("index1 training failed\n");
1186 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
1188 unsigned int stride = params->base.stride;
1189 unsigned int channel, chinfo = 0;
1190 unsigned int ch_cap[2] = {0, 0};
1193 for (channel = 0; channel < 2; channel++) {
1194 unsigned int cs0_cap = 0;
1195 unsigned int cs1_cap = 0;
1196 struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;
1198 if (cap_info->col == 0)
1201 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
1202 cap_info->bk + cap_info->bw - 20));
1203 if (cap_info->rank > 1)
1204 cs1_cap = cs0_cap >> (cap_info->cs0_row
1205 - cap_info->cs1_row);
1206 if (cap_info->row_3_4) {
1207 cs0_cap = cs0_cap * 3 / 4;
1208 cs1_cap = cs1_cap * 3 / 4;
1210 ch_cap[channel] = cs0_cap + cs1_cap;
1211 chinfo |= 1 << channel;
1214 /* stride calculation for 1 channel */
1215 if (params->base.num_channels == 1 && chinfo & 1)
1216 return 0x17; /* channel a */
1218 /* stride calculation for 2 channels, default gstride type is 256B */
1219 if (ch_cap[0] == ch_cap[1]) {
1220 cap = ch_cap[0] + ch_cap[1];
1231 * 768MB + 768MB same as total 2GB memory
1232 * useful space: 0-768MB 1GB-1792MB
1239 /* 1536MB + 1536MB */
1248 printf("%s: Unable to calculate stride for ", __func__);
1249 print_size((cap * (1 << 20)), " capacity\n");
1254 sdram_print_stride(stride);
1259 static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
1261 params->ch[channel].cap_info.rank = 0;
1262 params->ch[channel].cap_info.col = 0;
1263 params->ch[channel].cap_info.bk = 0;
1264 params->ch[channel].cap_info.bw = 32;
1265 params->ch[channel].cap_info.dbw = 32;
1266 params->ch[channel].cap_info.row_3_4 = 0;
1267 params->ch[channel].cap_info.cs0_row = 0;
1268 params->ch[channel].cap_info.cs1_row = 0;
1269 params->ch[channel].cap_info.ddrconfig = 0;
1272 static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
1277 for (channel = 0; channel < 2; channel++) {
1278 const struct chan_info *chan = &dram->chan[channel];
1279 struct rk3399_cru *cru = dram->cru;
1280 struct rk3399_ddr_publ_regs *publ = chan->publ;
1282 phy_pctrl_reset(cru, channel);
1283 phy_dll_bypass_set(publ, params->base.ddr_freq);
1285 ret = pctl_cfg(dram, chan, channel, params);
1287 printf("%s: pctl config failed\n", __func__);
1291 /* start to trigger initialization */
1292 pctl_start(dram, channel);
1298 static int sdram_init(struct dram_info *dram,
1299 struct rk3399_sdram_params *params)
1301 unsigned char dramtype = params->base.dramtype;
1302 unsigned int ddr_freq = params->base.ddr_freq;
1303 u32 training_flag = PI_READ_GATE_TRAINING;
1304 int channel, ch, rank;
1307 debug("Starting SDRAM initialization...\n");
1309 if ((dramtype == DDR3 && ddr_freq > 933) ||
1310 (dramtype == LPDDR3 && ddr_freq > 933) ||
1311 (dramtype == LPDDR4 && ddr_freq > 800)) {
1312 debug("SDRAM frequency is to high!");
1316 for (ch = 0; ch < 2; ch++) {
1317 params->ch[ch].cap_info.rank = 2;
1318 for (rank = 2; rank != 0; rank--) {
1319 ret = pctl_init(dram, params);
1321 printf("%s: pctl init failed\n", __func__);
1325 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1326 if (dramtype == LPDDR3)
1329 params->ch[ch].cap_info.rank = rank;
1332 * LPDDR3 CA training msut be trigger before
1334 * DDR3 is not have CA training.
1336 if (params->base.dramtype == LPDDR3)
1337 training_flag |= PI_CA_TRAINING;
1339 if (!(data_training(&dram->chan[ch], ch,
1340 params, training_flag)))
1343 /* Computed rank with associated channel number */
1344 params->ch[ch].cap_info.rank = rank;
1347 params->base.num_channels = 0;
1348 for (channel = 0; channel < 2; channel++) {
1349 const struct chan_info *chan = &dram->chan[channel];
1350 struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;
1351 u8 training_flag = PI_FULL_TRAINING;
1353 if (cap_info->rank == 0) {
1354 clear_channel_params(params, channel);
1357 params->base.num_channels++;
1361 debug(channel ? "1: " : "0: ");
1363 /* LPDDR3 should have write and read gate training */
1364 if (params->base.dramtype == LPDDR3)
1365 training_flag = PI_WRITE_LEVELING |
1366 PI_READ_GATE_TRAINING;
1368 if (params->base.dramtype != LPDDR4) {
1369 ret = data_training(dram, channel, params,
1372 debug("%s: data train failed for channel %d\n",
1378 sdram_print_ddr_info(cap_info, ¶ms->base);
1380 set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
1383 if (params->base.num_channels == 0) {
1384 printf("%s: ", __func__);
1385 sdram_print_dram_type(params->base.dramtype);
1386 printf(" - %dMHz failed!\n", params->base.ddr_freq);
1390 params->base.stride = calculate_stride(params);
1391 dram_all_config(dram, params);
1392 switch_to_phy_index1(dram, params);
1394 debug("Finish SDRAM initialization...\n");
1398 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1400 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1401 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1404 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1405 (u32 *)&plat->sdram_params,
1406 sizeof(plat->sdram_params) / sizeof(u32));
1408 printf("%s: Cannot read rockchip,sdram-params %d\n",
1412 ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1414 printf("%s: regmap failed %d\n", __func__, ret);
1420 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1421 static int conv_of_platdata(struct udevice *dev)
1423 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1424 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1427 ret = regmap_init_mem_platdata(dev, dtplat->reg,
1428 ARRAY_SIZE(dtplat->reg) / 2,
1437 static int rk3399_dmc_init(struct udevice *dev)
1439 struct dram_info *priv = dev_get_priv(dev);
1440 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1442 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1443 struct rk3399_sdram_params *params = &plat->sdram_params;
1445 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1446 struct rk3399_sdram_params *params =
1447 (void *)dtplat->rockchip_sdram_params;
1449 ret = conv_of_platdata(dev);
1454 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1455 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1456 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1457 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1458 priv->pmucru = rockchip_get_pmucru();
1459 priv->cru = rockchip_get_cru();
1460 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1461 priv->chan[0].pi = regmap_get_range(plat->map, 1);
1462 priv->chan[0].publ = regmap_get_range(plat->map, 2);
1463 priv->chan[0].msch = regmap_get_range(plat->map, 3);
1464 priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1465 priv->chan[1].pi = regmap_get_range(plat->map, 5);
1466 priv->chan[1].publ = regmap_get_range(plat->map, 6);
1467 priv->chan[1].msch = regmap_get_range(plat->map, 7);
1469 debug("con reg %p %p %p %p %p %p %p %p\n",
1470 priv->chan[0].pctl, priv->chan[0].pi,
1471 priv->chan[0].publ, priv->chan[0].msch,
1472 priv->chan[1].pctl, priv->chan[1].pi,
1473 priv->chan[1].publ, priv->chan[1].msch);
1474 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1475 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1477 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1478 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1480 ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1483 printf("%s clk get failed %d\n", __func__, ret);
1487 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1489 printf("%s clk set failed %d\n", __func__, ret);
1493 ret = sdram_init(priv, params);
1495 printf("%s DRAM init failed %d\n", __func__, ret);
1503 static int rk3399_dmc_probe(struct udevice *dev)
1505 #if defined(CONFIG_TPL_BUILD) || \
1506 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1507 if (rk3399_dmc_init(dev))
1510 struct dram_info *priv = dev_get_priv(dev);
1512 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1513 debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1514 priv->info.base = CONFIG_SYS_SDRAM_BASE;
1516 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1521 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1523 struct dram_info *priv = dev_get_priv(dev);
1530 static struct ram_ops rk3399_dmc_ops = {
1531 .get_info = rk3399_dmc_get_info,
1534 static const struct udevice_id rk3399_dmc_ids[] = {
1535 { .compatible = "rockchip,rk3399-dmc" },
1539 U_BOOT_DRIVER(dmc_rk3399) = {
1540 .name = "rockchip_rk3399_dmc",
1542 .of_match = rk3399_dmc_ids,
1543 .ops = &rk3399_dmc_ops,
1544 #if defined(CONFIG_TPL_BUILD) || \
1545 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1546 .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1548 .probe = rk3399_dmc_probe,
1549 .priv_auto_alloc_size = sizeof(struct dram_info),
1550 #if defined(CONFIG_TPL_BUILD) || \
1551 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1552 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),