drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/sdram_common.h>
  21 #include <asm/arch-rockchip/sdram_rk3399.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  26 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  27 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  28
  29 #define PHY_DRV_ODT_HI_Z        0x0
  30 #define PHY_DRV_ODT_240         0x1
  31 #define PHY_DRV_ODT_120         0x8
  32 #define PHY_DRV_ODT_80          0x9
  33 #define PHY_DRV_ODT_60          0xc
  34 #define PHY_DRV_ODT_48          0xd
  35 #define PHY_DRV_ODT_40          0xe
  36 #define PHY_DRV_ODT_34_3        0xf
  37
  38 struct chan_info {
  39         struct rk3399_ddr_pctl_regs *pctl;
  40         struct rk3399_ddr_pi_regs *pi;
  41         struct rk3399_ddr_publ_regs *publ;
  42         struct rk3399_msch_regs *msch;
  43 };
  44
  45 struct dram_info {
  46 #if defined(CONFIG_TPL_BUILD) || \
  47         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  48         struct chan_info chan[2];
  49         struct clk ddr_clk;
  50         struct rk3399_cru *cru;
  51         struct rk3399_pmucru *pmucru;
  52         struct rk3399_pmusgrf_regs *pmusgrf;
  53         struct rk3399_ddr_cic_regs *cic;
  54 #endif
  55         struct ram_info info;
  56         struct rk3399_pmugrf_regs *pmugrf;
  57 };
  58
  59 #if defined(CONFIG_TPL_BUILD) || \
  60         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  61
  62 struct rockchip_dmc_plat {
  63 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  64         struct dtd_rockchip_rk3399_dmc dtplat;
  65 #else
  66         struct rk3399_sdram_params sdram_params;
  67 #endif
  68         struct regmap *map;
  69 };
  70
  71 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
  72 {
  73         int i;
  74
  75         for (i = 0; i < n / sizeof(u32); i++) {
  76                 writel(*src, dest);
  77                 src++;
  78                 dest++;
  79         }
  80 }
  81
  82 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
  83                                u32 freq)
  84 {
  85         u32 *denali_phy = ddr_publ_regs->denali_phy;
  86
  87         /* From IP spec, only freq small than 125 can enter dll bypass mode */
  88         if (freq <= 125) {
  89                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
  90                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
  91                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
  92                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
  93                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
  94
  95                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
  96                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
  97                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
  98                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
  99         } else {
 100                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 101                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 102                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 103                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 104                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 105
 106                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 107                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 108                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 109                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 110         }
 111 }
 112
 113 static void set_memory_map(const struct chan_info *chan, u32 channel,
 114                            const struct rk3399_sdram_params *sdram_params)
 115 {
 116         const struct rk3399_sdram_channel *sdram_ch =
 117                 &sdram_params->ch[channel];
 118         u32 *denali_ctl = chan->pctl->denali_ctl;
 119         u32 *denali_pi = chan->pi->denali_pi;
 120         u32 cs_map;
 121         u32 reduc;
 122         u32 row;
 123
 124         /* Get row number from ddrconfig setting */
 125         if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
 126                 row = 16;
 127         else if (sdram_ch->ddrconfig == 3)
 128                 row = 14;
 129         else
 130                 row = 15;
 131
 132         cs_map = (sdram_ch->rank > 1) ? 3 : 1;
 133         reduc = (sdram_ch->bw == 2) ? 0 : 1;
 134
 135         /* Set the dram configuration to ctrl */
 136         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
 137         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 138                         ((3 - sdram_ch->bk) << 16) |
 139                         ((16 - row) << 24));
 140
 141         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 142                         cs_map | (reduc << 16));
 143
 144         /* PI_199 PI_COL_DIFF:RW:0:4 */
 145         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
 146
 147         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 148         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 149                         ((3 - sdram_ch->bk) << 16) |
 150                         ((16 - row) << 24));
 151         /* PI_41 PI_CS_MAP:RW:24:4 */
 152         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 153         if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)
 154                 writel(0x2EC7FFFF, &denali_pi[34]);
 155 }
 156
 157 static void set_ds_odt(const struct chan_info *chan,
 158                        const struct rk3399_sdram_params *sdram_params)
 159 {
 160         u32 *denali_phy = chan->publ->denali_phy;
 161
 162         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 163         u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
 164         u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
 165         u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
 166         u32 reg_value;
 167
 168         if (sdram_params->base.dramtype == LPDDR4) {
 169                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 170                 tsel_wr_select_p = PHY_DRV_ODT_40;
 171                 ca_tsel_wr_select_p = PHY_DRV_ODT_40;
 172                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 173
 174                 tsel_rd_select_n = PHY_DRV_ODT_240;
 175                 tsel_wr_select_n = PHY_DRV_ODT_40;
 176                 ca_tsel_wr_select_n = PHY_DRV_ODT_40;
 177                 tsel_idle_select_n = PHY_DRV_ODT_240;
 178         } else if (sdram_params->base.dramtype == LPDDR3) {
 179                 tsel_rd_select_p = PHY_DRV_ODT_240;
 180                 tsel_wr_select_p = PHY_DRV_ODT_34_3;
 181                 ca_tsel_wr_select_p = PHY_DRV_ODT_48;
 182                 tsel_idle_select_p = PHY_DRV_ODT_240;
 183
 184                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 185                 tsel_wr_select_n = PHY_DRV_ODT_34_3;
 186                 ca_tsel_wr_select_n = PHY_DRV_ODT_48;
 187                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 188         } else {
 189                 tsel_rd_select_p = PHY_DRV_ODT_240;
 190                 tsel_wr_select_p = PHY_DRV_ODT_34_3;
 191                 ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
 192                 tsel_idle_select_p = PHY_DRV_ODT_240;
 193
 194                 tsel_rd_select_n = PHY_DRV_ODT_240;
 195                 tsel_wr_select_n = PHY_DRV_ODT_34_3;
 196                 ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
 197                 tsel_idle_select_n = PHY_DRV_ODT_240;
 198         }
 199
 200         if (sdram_params->base.odt == 1)
 201                 tsel_rd_en = 1;
 202         else
 203                 tsel_rd_en = 0;
 204
 205         tsel_wr_en = 0;
 206         tsel_idle_en = 0;
 207
 208         /*
 209          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 210          * sets termination values for read/idle cycles and drive strength
 211          * for write cycles for DQ/DM
 212          */
 213         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 214                     (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
 215                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 216         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 217         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 218         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 219         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 220
 221         /*
 222          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 223          * sets termination values for read/idle cycles and drive strength
 224          * for write cycles for DQS
 225          */
 226         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 227         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 228         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 229         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 230
 231         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 232         reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4);
 233         clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 234         clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 235         clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 236
 237         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 238         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 239
 240         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 241         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 242
 243         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 244         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 245
 246         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 247         clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
 248
 249         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 250         clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
 251
 252         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 253         clrsetbits_le32(&denali_phy[924], 0xff,
 254                         tsel_wr_select_n | (tsel_wr_select_p << 4));
 255         clrsetbits_le32(&denali_phy[925], 0xff,
 256                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 257
 258         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 259         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 260                 << 16;
 261         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 262         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 263         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 264         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 265
 266         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 267         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 268                 << 24;
 269         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 270         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 271         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 272         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 273
 274         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 275         reg_value = tsel_wr_en << 8;
 276         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 277         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 278         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 279
 280         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 281         reg_value = tsel_wr_en << 17;
 282         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 283         /*
 284          * pad_rst/cke/cs/clk_term tsel 1bits
 285          * DENALI_PHY_938/936/940/934 offset_17
 286          */
 287         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 288         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 289         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 290         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 291
 292         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 293         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 294 }
 295
 296 static int phy_io_config(const struct chan_info *chan,
 297                          const struct rk3399_sdram_params *sdram_params)
 298 {
 299         u32 *denali_phy = chan->publ->denali_phy;
 300         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 301         u32 mode_sel;
 302         u32 reg_value;
 303         u32 drv_value, odt_value;
 304         u32 speed;
 305
 306         /* vref setting */
 307         if (sdram_params->base.dramtype == LPDDR4) {
 308                 /* LPDDR4 */
 309                 vref_mode_dq = 0x6;
 310                 vref_value_dq = 0x1f;
 311                 vref_mode_ac = 0x6;
 312                 vref_value_ac = 0x1f;
 313         } else if (sdram_params->base.dramtype == LPDDR3) {
 314                 if (sdram_params->base.odt == 1) {
 315                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 316                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 317                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 318                         if (drv_value == PHY_DRV_ODT_48) {
 319                                 switch (odt_value) {
 320                                 case PHY_DRV_ODT_240:
 321                                         vref_value_dq = 0x16;
 322                                         break;
 323                                 case PHY_DRV_ODT_120:
 324                                         vref_value_dq = 0x26;
 325                                         break;
 326                                 case PHY_DRV_ODT_60:
 327                                         vref_value_dq = 0x36;
 328                                         break;
 329                                 default:
 330                                         debug("Invalid ODT value.\n");
 331                                         return -EINVAL;
 332                                 }
 333                         } else if (drv_value == PHY_DRV_ODT_40) {
 334                                 switch (odt_value) {
 335                                 case PHY_DRV_ODT_240:
 336                                         vref_value_dq = 0x19;
 337                                         break;
 338                                 case PHY_DRV_ODT_120:
 339                                         vref_value_dq = 0x23;
 340                                         break;
 341                                 case PHY_DRV_ODT_60:
 342                                         vref_value_dq = 0x31;
 343                                         break;
 344                                 default:
 345                                         debug("Invalid ODT value.\n");
 346                                         return -EINVAL;
 347                                 }
 348                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 349                                 switch (odt_value) {
 350                                 case PHY_DRV_ODT_240:
 351                                         vref_value_dq = 0x17;
 352                                         break;
 353                                 case PHY_DRV_ODT_120:
 354                                         vref_value_dq = 0x20;
 355                                         break;
 356                                 case PHY_DRV_ODT_60:
 357                                         vref_value_dq = 0x2e;
 358                                         break;
 359                                 default:
 360                                         debug("Invalid ODT value.\n");
 361                                         return -EINVAL;
 362                                 }
 363                         } else {
 364                                 debug("Invalid DRV value.\n");
 365                                 return -EINVAL;
 366                         }
 367                 } else {
 368                         vref_mode_dq = 0x2;  /* LPDDR3 */
 369                         vref_value_dq = 0x1f;
 370                 }
 371                 vref_mode_ac = 0x2;
 372                 vref_value_ac = 0x1f;
 373         } else if (sdram_params->base.dramtype == DDR3) {
 374                 /* DDR3L */
 375                 vref_mode_dq = 0x1;
 376                 vref_value_dq = 0x1f;
 377                 vref_mode_ac = 0x1;
 378                 vref_value_ac = 0x1f;
 379         } else {
 380                 debug("Unknown DRAM type.\n");
 381                 return -EINVAL;
 382         }
 383
 384         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 385
 386         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 387         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 388         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 389         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 390         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 391         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 392         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 393         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 394
 395         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 396
 397         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 398         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 399
 400         if (sdram_params->base.dramtype == LPDDR4)
 401                 mode_sel = 0x6;
 402         else if (sdram_params->base.dramtype == LPDDR3)
 403                 mode_sel = 0x0;
 404         else if (sdram_params->base.dramtype == DDR3)
 405                 mode_sel = 0x1;
 406         else
 407                 return -EINVAL;
 408
 409         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 410         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 411         /* PHY_926 PHY_PAD_DATA_DRIVE */
 412         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 413         /* PHY_927 PHY_PAD_DQS_DRIVE */
 414         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 415         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 416         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 417         /* PHY_929 PHY_PAD_CLK_DRIVE */
 418         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 419         /* PHY_935 PHY_PAD_CKE_DRIVE */
 420         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 421         /* PHY_937 PHY_PAD_RST_DRIVE */
 422         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 423         /* PHY_939 PHY_PAD_CS_DRIVE */
 424         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 425
 426         /* speed setting */
 427         if (sdram_params->base.ddr_freq < 400)
 428                 speed = 0x0;
 429         else if (sdram_params->base.ddr_freq < 800)
 430                 speed = 0x1;
 431         else if (sdram_params->base.ddr_freq < 1200)
 432                 speed = 0x2;
 433         else
 434                 speed = 0x3;
 435
 436         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 437         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 438         /* PHY_926 PHY_PAD_DATA_DRIVE */
 439         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 440         /* PHY_927 PHY_PAD_DQS_DRIVE */
 441         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 442         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 443         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 444         /* PHY_929 PHY_PAD_CLK_DRIVE */
 445         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 446         /* PHY_935 PHY_PAD_CKE_DRIVE */
 447         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 448         /* PHY_937 PHY_PAD_RST_DRIVE */
 449         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 450         /* PHY_939 PHY_PAD_CS_DRIVE */
 451         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 452
 453         return 0;
 454 }
 455
 456 static int pctl_cfg(const struct chan_info *chan, u32 channel,
 457                     const struct rk3399_sdram_params *sdram_params)
 458 {
 459         u32 *denali_ctl = chan->pctl->denali_ctl;
 460         u32 *denali_pi = chan->pi->denali_pi;
 461         u32 *denali_phy = chan->publ->denali_phy;
 462         const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
 463         const u32 *params_phy = sdram_params->phy_regs.denali_phy;
 464         u32 tmp, tmp1, tmp2;
 465         u32 pwrup_srefresh_exit;
 466         int ret;
 467         const ulong timeout_ms = 200;
 468
 469         /*
 470          * work around controller bug:
 471          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 472          */
 473         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 474                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 475         writel(params_ctl[0], &denali_ctl[0]);
 476
 477         copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
 478                     sizeof(struct rk3399_ddr_pi_regs));
 479
 480         /* rank count need to set for init */
 481         set_memory_map(chan, channel, sdram_params);
 482
 483         writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]);
 484         writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
 485         writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
 486
 487         pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
 488         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 489
 490         /* PHY_DLL_RST_EN */
 491         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 492
 493         setbits_le32(&denali_pi[0], START);
 494         setbits_le32(&denali_ctl[0], START);
 495
 496         /* Waiting for phy DLL lock */
 497         while (1) {
 498                 tmp = readl(&denali_phy[920]);
 499                 tmp1 = readl(&denali_phy[921]);
 500                 tmp2 = readl(&denali_phy[922]);
 501                 if ((((tmp >> 16) & 0x1) == 0x1) &&
 502                     (((tmp1 >> 16) & 0x1) == 0x1) &&
 503                     (((tmp1 >> 0) & 0x1) == 0x1) &&
 504                     (((tmp2 >> 0) & 0x1) == 0x1))
 505                         break;
 506         }
 507
 508         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 509         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 510         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 511         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 512         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 513         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 514         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 515         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 516         set_ds_odt(chan, sdram_params);
 517
 518         /*
 519          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 520          * dqs_tsel_wr_end[7:4] add Half cycle
 521          */
 522         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 523         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 524         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 525         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 526         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 527         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 528         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 529         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 530
 531         /*
 532          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 533          * dq_tsel_wr_end[7:4] add Half cycle
 534          */
 535         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 536         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 537         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 538         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 539         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 540         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 541         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 542         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 543
 544         ret = phy_io_config(chan, sdram_params);
 545         if (ret)
 546                 return ret;
 547
 548         /* PHY_DLL_RST_EN */
 549         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 550
 551         /* Waiting for PHY and DRAM init complete */
 552         tmp = get_timer(0);
 553         do {
 554                 if (get_timer(tmp) > timeout_ms) {
 555                         pr_err("DRAM (%s): phy failed to lock within  %ld ms\n",
 556                                __func__, timeout_ms);
 557                         return -ETIME;
 558                 }
 559         } while (!(readl(&denali_ctl[203]) & (1 << 3)));
 560         debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
 561
 562         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 563                         pwrup_srefresh_exit);
 564         return 0;
 565 }
 566
 567 static void select_per_cs_training_index(const struct chan_info *chan,
 568                                          u32 rank)
 569 {
 570         u32 *denali_phy = chan->publ->denali_phy;
 571
 572         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 573         if ((readl(&denali_phy[84]) >> 16) & 1) {
 574                 /*
 575                  * PHY_8/136/264/392
 576                  * phy_per_cs_training_index_X 1bit offset_24
 577                  */
 578                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 579                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 580                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 581                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 582         }
 583 }
 584
 585 static void override_write_leveling_value(const struct chan_info *chan)
 586 {
 587         u32 *denali_ctl = chan->pctl->denali_ctl;
 588         u32 *denali_phy = chan->publ->denali_phy;
 589         u32 byte;
 590
 591         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 592         setbits_le32(&denali_phy[896], 1);
 593
 594         /*
 595          * PHY_8/136/264/392
 596          * phy_per_cs_training_multicast_en_X 1bit offset_16
 597          */
 598         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 599         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 600         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 601         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 602
 603         for (byte = 0; byte < 4; byte++)
 604                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 605                                 0x200 << 16);
 606
 607         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 608         clrbits_le32(&denali_phy[896], 1);
 609
 610         /* CTL_200 ctrlupd_req 1bit offset_8 */
 611         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 612 }
 613
 614 static int data_training_ca(const struct chan_info *chan, u32 channel,
 615                             const struct rk3399_sdram_params *sdram_params)
 616 {
 617         u32 *denali_pi = chan->pi->denali_pi;
 618         u32 *denali_phy = chan->publ->denali_phy;
 619         u32 i, tmp;
 620         u32 obs_0, obs_1, obs_2, obs_err = 0;
 621         u32 rank = sdram_params->ch[channel].rank;
 622
 623         for (i = 0; i < rank; i++) {
 624                 select_per_cs_training_index(chan, i);
 625
 626                 /* PI_100 PI_CALVL_EN:RW:8:2 */
 627                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
 628
 629                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 630                 clrsetbits_le32(&denali_pi[92],
 631                                 (0x1 << 16) | (0x3 << 24),
 632                                 (0x1 << 16) | (i << 24));
 633
 634                 /* Waiting for training complete */
 635                 while (1) {
 636                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 637                         tmp = readl(&denali_pi[174]) >> 8;
 638                         /*
 639                          * check status obs
 640                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
 641                          */
 642                         obs_0 = readl(&denali_phy[532]);
 643                         obs_1 = readl(&denali_phy[660]);
 644                         obs_2 = readl(&denali_phy[788]);
 645                         if (((obs_0 >> 30) & 0x3) ||
 646                             ((obs_1 >> 30) & 0x3) ||
 647                             ((obs_2 >> 30) & 0x3))
 648                                 obs_err = 1;
 649                         if ((((tmp >> 11) & 0x1) == 0x1) &&
 650                             (((tmp >> 13) & 0x1) == 0x1) &&
 651                             (((tmp >> 5) & 0x1) == 0x0) &&
 652                             obs_err == 0)
 653                                 break;
 654                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
 655                                  (obs_err == 1))
 656                                 return -EIO;
 657                 }
 658
 659                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 660                 writel(0x00003f7c, (&denali_pi[175]));
 661         }
 662
 663         clrbits_le32(&denali_pi[100], 0x3 << 8);
 664
 665         return 0;
 666 }
 667
 668 static int data_training_wl(const struct chan_info *chan, u32 channel,
 669                             const struct rk3399_sdram_params *sdram_params)
 670 {
 671         u32 *denali_pi = chan->pi->denali_pi;
 672         u32 *denali_phy = chan->publ->denali_phy;
 673         u32 i, tmp;
 674         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 675         u32 rank = sdram_params->ch[channel].rank;
 676
 677         for (i = 0; i < rank; i++) {
 678                 select_per_cs_training_index(chan, i);
 679
 680                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
 681                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
 682
 683                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
 684                 clrsetbits_le32(&denali_pi[59],
 685                                 (0x1 << 8) | (0x3 << 16),
 686                                 (0x1 << 8) | (i << 16));
 687
 688                 /* Waiting for training complete */
 689                 while (1) {
 690                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 691                         tmp = readl(&denali_pi[174]) >> 8;
 692
 693                         /*
 694                          * check status obs, if error maybe can not
 695                          * get leveling done PHY_40/168/296/424
 696                          * phy_wrlvl_status_obs_X:0:13
 697                          */
 698                         obs_0 = readl(&denali_phy[40]);
 699                         obs_1 = readl(&denali_phy[168]);
 700                         obs_2 = readl(&denali_phy[296]);
 701                         obs_3 = readl(&denali_phy[424]);
 702                         if (((obs_0 >> 12) & 0x1) ||
 703                             ((obs_1 >> 12) & 0x1) ||
 704                             ((obs_2 >> 12) & 0x1) ||
 705                             ((obs_3 >> 12) & 0x1))
 706                                 obs_err = 1;
 707                         if ((((tmp >> 10) & 0x1) == 0x1) &&
 708                             (((tmp >> 13) & 0x1) == 0x1) &&
 709                             (((tmp >> 4) & 0x1) == 0x0) &&
 710                             obs_err == 0)
 711                                 break;
 712                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
 713                                  (obs_err == 1))
 714                                 return -EIO;
 715                 }
 716
 717                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 718                 writel(0x00003f7c, (&denali_pi[175]));
 719         }
 720
 721         override_write_leveling_value(chan);
 722         clrbits_le32(&denali_pi[60], 0x3 << 8);
 723
 724         return 0;
 725 }
 726
 727 static int data_training_rg(const struct chan_info *chan, u32 channel,
 728                             const struct rk3399_sdram_params *sdram_params)
 729 {
 730         u32 *denali_pi = chan->pi->denali_pi;
 731         u32 *denali_phy = chan->publ->denali_phy;
 732         u32 i, tmp;
 733         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 734         u32 rank = sdram_params->ch[channel].rank;
 735
 736         for (i = 0; i < rank; i++) {
 737                 select_per_cs_training_index(chan, i);
 738
 739                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
 740                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
 741
 742                 /*
 743                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
 744                  * PI_RDLVL_CS:RW:24:2
 745                  */
 746                 clrsetbits_le32(&denali_pi[74],
 747                                 (0x1 << 16) | (0x3 << 24),
 748                                 (0x1 << 16) | (i << 24));
 749
 750                 /* Waiting for training complete */
 751                 while (1) {
 752                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 753                         tmp = readl(&denali_pi[174]) >> 8;
 754
 755                         /*
 756                          * check status obs
 757                          * PHY_43/171/299/427
 758                          *     PHY_GTLVL_STATUS_OBS_x:16:8
 759                          */
 760                         obs_0 = readl(&denali_phy[43]);
 761                         obs_1 = readl(&denali_phy[171]);
 762                         obs_2 = readl(&denali_phy[299]);
 763                         obs_3 = readl(&denali_phy[427]);
 764                         if (((obs_0 >> (16 + 6)) & 0x3) ||
 765                             ((obs_1 >> (16 + 6)) & 0x3) ||
 766                             ((obs_2 >> (16 + 6)) & 0x3) ||
 767                             ((obs_3 >> (16 + 6)) & 0x3))
 768                                 obs_err = 1;
 769                         if ((((tmp >> 9) & 0x1) == 0x1) &&
 770                             (((tmp >> 13) & 0x1) == 0x1) &&
 771                             (((tmp >> 3) & 0x1) == 0x0) &&
 772                             obs_err == 0)
 773                                 break;
 774                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
 775                                  (obs_err == 1))
 776                                 return -EIO;
 777                 }
 778
 779                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 780                 writel(0x00003f7c, (&denali_pi[175]));
 781         }
 782
 783         clrbits_le32(&denali_pi[80], 0x3 << 24);
 784
 785         return 0;
 786 }
 787
 788 static int data_training_rl(const struct chan_info *chan, u32 channel,
 789                             const struct rk3399_sdram_params *sdram_params)
 790 {
 791         u32 *denali_pi = chan->pi->denali_pi;
 792         u32 i, tmp;
 793         u32 rank = sdram_params->ch[channel].rank;
 794
 795         for (i = 0; i < rank; i++) {
 796                 select_per_cs_training_index(chan, i);
 797
 798                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
 799                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
 800
 801                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
 802                 clrsetbits_le32(&denali_pi[74],
 803                                 (0x1 << 8) | (0x3 << 24),
 804                                 (0x1 << 8) | (i << 24));
 805
 806                 /* Waiting for training complete */
 807                 while (1) {
 808                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 809                         tmp = readl(&denali_pi[174]) >> 8;
 810
 811                         /*
 812                          * make sure status obs not report error bit
 813                          * PHY_46/174/302/430
 814                          *     phy_rdlvl_status_obs_X:16:8
 815                          */
 816                         if ((((tmp >> 8) & 0x1) == 0x1) &&
 817                             (((tmp >> 13) & 0x1) == 0x1) &&
 818                             (((tmp >> 2) & 0x1) == 0x0))
 819                                 break;
 820                         else if (((tmp >> 2) & 0x1) == 0x1)
 821                                 return -EIO;
 822                 }
 823
 824                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 825                 writel(0x00003f7c, (&denali_pi[175]));
 826         }
 827
 828         clrbits_le32(&denali_pi[80], 0x3 << 16);
 829
 830         return 0;
 831 }
 832
 833 static int data_training_wdql(const struct chan_info *chan, u32 channel,
 834                               const struct rk3399_sdram_params *sdram_params)
 835 {
 836         u32 *denali_pi = chan->pi->denali_pi;
 837         u32 i, tmp;
 838         u32 rank = sdram_params->ch[channel].rank;
 839
 840         for (i = 0; i < rank; i++) {
 841                 select_per_cs_training_index(chan, i);
 842
 843                 /*
 844                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
 845                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
 846                  */
 847                 clrbits_le32(&denali_pi[181], 0x1 << 8);
 848
 849                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
 850                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
 851
 852                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
 853                 clrsetbits_le32(&denali_pi[121],
 854                                 (0x1 << 8) | (0x3 << 16),
 855                                 (0x1 << 8) | (i << 16));
 856
 857                 /* Waiting for training complete */
 858                 while (1) {
 859                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 860                         tmp = readl(&denali_pi[174]) >> 8;
 861                         if ((((tmp >> 12) & 0x1) == 0x1) &&
 862                             (((tmp >> 13) & 0x1) == 0x1) &&
 863                             (((tmp >> 6) & 0x1) == 0x0))
 864                                 break;
 865                         else if (((tmp >> 6) & 0x1) == 0x1)
 866                                 return -EIO;
 867                 }
 868
 869                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 870                 writel(0x00003f7c, (&denali_pi[175]));
 871         }
 872
 873         clrbits_le32(&denali_pi[124], 0x3 << 16);
 874
 875         return 0;
 876 }
 877
 878 static int data_training(const struct chan_info *chan, u32 channel,
 879                          const struct rk3399_sdram_params *sdram_params,
 880                          u32 training_flag)
 881 {
 882         u32 *denali_phy = chan->publ->denali_phy;
 883
 884         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 885         setbits_le32(&denali_phy[927], (1 << 22));
 886
 887         if (training_flag == PI_FULL_TRAINING) {
 888                 if (sdram_params->base.dramtype == LPDDR4) {
 889                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 890                                         PI_READ_GATE_TRAINING |
 891                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
 892                 } else if (sdram_params->base.dramtype == LPDDR3) {
 893                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
 894                                         PI_READ_GATE_TRAINING;
 895                 } else if (sdram_params->base.dramtype == DDR3) {
 896                         training_flag = PI_WRITE_LEVELING |
 897                                         PI_READ_GATE_TRAINING |
 898                                         PI_READ_LEVELING;
 899                 }
 900         }
 901
 902         /* ca training(LPDDR4,LPDDR3 support) */
 903         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)
 904                 data_training_ca(chan, channel, sdram_params);
 905
 906         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
 907         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)
 908                 data_training_wl(chan, channel, sdram_params);
 909
 910         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
 911         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)
 912                 data_training_rg(chan, channel, sdram_params);
 913
 914         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
 915         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)
 916                 data_training_rl(chan, channel, sdram_params);
 917
 918         /* wdq leveling(LPDDR4 support) */
 919         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)
 920                 data_training_wdql(chan, channel, sdram_params);
 921
 922         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
 923         clrbits_le32(&denali_phy[927], (1 << 22));
 924
 925         return 0;
 926 }
 927
 928 static void set_ddrconfig(const struct chan_info *chan,
 929                           const struct rk3399_sdram_params *sdram_params,
 930                           unsigned char channel, u32 ddrconfig)
 931 {
 932         /* only need to set ddrconfig */
 933         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
 934         unsigned int cs0_cap = 0;
 935         unsigned int cs1_cap = 0;
 936
 937         cs0_cap = (1 << (sdram_params->ch[channel].cs0_row
 938                         + sdram_params->ch[channel].col
 939                         + sdram_params->ch[channel].bk
 940                         + sdram_params->ch[channel].bw - 20));
 941         if (sdram_params->ch[channel].rank > 1)
 942                 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row
 943                                 - sdram_params->ch[channel].cs1_row);
 944         if (sdram_params->ch[channel].row_3_4) {
 945                 cs0_cap = cs0_cap * 3 / 4;
 946                 cs1_cap = cs1_cap * 3 / 4;
 947         }
 948
 949         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
 950         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
 951                &ddr_msch_regs->ddrsize);
 952 }
 953
 954 static void dram_all_config(struct dram_info *dram,
 955                             const struct rk3399_sdram_params *sdram_params)
 956 {
 957         u32 sys_reg = 0;
 958         unsigned int channel, idx;
 959
 960         sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
 961         sys_reg |= (sdram_params->base.num_channels - 1)
 962                     << SYS_REG_NUM_CH_SHIFT;
 963
 964         for (channel = 0, idx = 0;
 965              (idx < sdram_params->base.num_channels) && (channel < 2);
 966              channel++) {
 967                 const struct rk3399_sdram_channel *info =
 968                         &sdram_params->ch[channel];
 969                 struct rk3399_msch_regs *ddr_msch_regs;
 970                 const struct rk3399_msch_timings *noc_timing;
 971
 972                 if (sdram_params->ch[channel].col == 0)
 973                         continue;
 974                 idx++;
 975                 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);
 976                 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
 977                 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
 978                 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
 979                 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
 980                 sys_reg |= (info->cs0_row - 13) <<
 981                             SYS_REG_CS0_ROW_SHIFT(channel);
 982                 sys_reg |= (info->cs1_row - 13) <<
 983                             SYS_REG_CS1_ROW_SHIFT(channel);
 984                 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
 985                 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
 986
 987                 ddr_msch_regs = dram->chan[channel].msch;
 988                 noc_timing = &sdram_params->ch[channel].noc_timings;
 989                 writel(noc_timing->ddrtiminga0,
 990                        &ddr_msch_regs->ddrtiminga0);
 991                 writel(noc_timing->ddrtimingb0,
 992                        &ddr_msch_regs->ddrtimingb0);
 993                 writel(noc_timing->ddrtimingc0,
 994                        &ddr_msch_regs->ddrtimingc0);
 995                 writel(noc_timing->devtodev0,
 996                        &ddr_msch_regs->devtodev0);
 997                 writel(noc_timing->ddrmode,
 998                        &ddr_msch_regs->ddrmode);
 999
1000                 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
1001                 if (sdram_params->ch[channel].rank == 1)
1002                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1003                                      1 << 17);
1004         }
1005
1006         writel(sys_reg, &dram->pmugrf->os_reg2);
1007         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1008                      sdram_params->base.stride << 10);
1009
1010         /* reboot hold register set */
1011         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1012                 PRESET_GPIO1_HOLD(1),
1013                 &dram->pmucru->pmucru_rstnhold_con[1]);
1014         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1015 }
1016
1017 static int switch_to_phy_index1(struct dram_info *dram,
1018                                 const struct rk3399_sdram_params *sdram_params)
1019 {
1020         u32 channel;
1021         u32 *denali_phy;
1022         u32 ch_count = sdram_params->base.num_channels;
1023         int ret;
1024         int i = 0;
1025
1026         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1027                              1 << 4 | 1 << 2 | 1),
1028                         &dram->cic->cic_ctrl0);
1029         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1030                 mdelay(10);
1031                 i++;
1032                 if (i > 10) {
1033                         debug("index1 frequency change overtime\n");
1034                         return -ETIME;
1035                 }
1036         }
1037
1038         i = 0;
1039         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1040         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1041                 mdelay(10);
1042                 i++;
1043                 if (i > 10) {
1044                         debug("index1 frequency done overtime\n");
1045                         return -ETIME;
1046                 }
1047         }
1048
1049         for (channel = 0; channel < ch_count; channel++) {
1050                 denali_phy = dram->chan[channel].publ->denali_phy;
1051                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1052                 ret = data_training(&dram->chan[channel], channel,
1053                                     sdram_params, PI_FULL_TRAINING);
1054                 if (ret) {
1055                         debug("index1 training failed\n");
1056                         return ret;
1057                 }
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int sdram_init(struct dram_info *dram,
1064                       const struct rk3399_sdram_params *sdram_params)
1065 {
1066         unsigned char dramtype = sdram_params->base.dramtype;
1067         unsigned int ddr_freq = sdram_params->base.ddr_freq;
1068         int channel;
1069
1070         debug("Starting SDRAM initialization...\n");
1071
1072         if ((dramtype == DDR3 && ddr_freq > 933) ||
1073             (dramtype == LPDDR3 && ddr_freq > 933) ||
1074             (dramtype == LPDDR4 && ddr_freq > 800)) {
1075                 debug("SDRAM frequency is to high!");
1076                 return -E2BIG;
1077         }
1078
1079         for (channel = 0; channel < 2; channel++) {
1080                 const struct chan_info *chan = &dram->chan[channel];
1081                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1082
1083                 phy_dll_bypass_set(publ, ddr_freq);
1084
1085                 if (channel >= sdram_params->base.num_channels)
1086                         continue;
1087
1088                 if (pctl_cfg(chan, channel, sdram_params) != 0) {
1089                         printf("pctl_cfg fail, reset\n");
1090                         return -EIO;
1091                 }
1092
1093                 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1094                 if (dramtype == LPDDR3)
1095                         udelay(10);
1096
1097                 if (data_training(chan, channel,
1098                                   sdram_params, PI_FULL_TRAINING)) {
1099                         printf("SDRAM initialization failed, reset\n");
1100                         return -EIO;
1101                 }
1102
1103                 set_ddrconfig(chan, sdram_params, channel,
1104                               sdram_params->ch[channel].ddrconfig);
1105         }
1106         dram_all_config(dram, sdram_params);
1107         switch_to_phy_index1(dram, sdram_params);
1108
1109         debug("Finish SDRAM initialization...\n");
1110         return 0;
1111 }
1112
1113 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1114 {
1115 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1116         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1117         int ret;
1118
1119         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1120                                  (u32 *)&plat->sdram_params,
1121                                  sizeof(plat->sdram_params) / sizeof(u32));
1122         if (ret) {
1123                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1124                        __func__, ret);
1125                 return ret;
1126         }
1127         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1128         if (ret)
1129                 printf("%s: regmap failed %d\n", __func__, ret);
1130
1131 #endif
1132         return 0;
1133 }
1134
1135 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1136 static int conv_of_platdata(struct udevice *dev)
1137 {
1138         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1139         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1140         int ret;
1141
1142         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1143                                        ARRAY_SIZE(dtplat->reg) / 2,
1144                                        &plat->map);
1145         if (ret)
1146                 return ret;
1147
1148         return 0;
1149 }
1150 #endif
1151
1152 static int rk3399_dmc_init(struct udevice *dev)
1153 {
1154         struct dram_info *priv = dev_get_priv(dev);
1155         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1156         int ret;
1157 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1158         struct rk3399_sdram_params *params = &plat->sdram_params;
1159 #else
1160         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1161         struct rk3399_sdram_params *params =
1162                                         (void *)dtplat->rockchip_sdram_params;
1163
1164         ret = conv_of_platdata(dev);
1165         if (ret)
1166                 return ret;
1167 #endif
1168
1169         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1170         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1171         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1172         priv->pmucru = rockchip_get_pmucru();
1173         priv->cru = rockchip_get_cru();
1174         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1175         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1176         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1177         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1178         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1179         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1180         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1181         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1182
1183         debug("con reg %p %p %p %p %p %p %p %p\n",
1184               priv->chan[0].pctl, priv->chan[0].pi,
1185               priv->chan[0].publ, priv->chan[0].msch,
1186               priv->chan[1].pctl, priv->chan[1].pi,
1187               priv->chan[1].publ, priv->chan[1].msch);
1188         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1189               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1190
1191 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1192         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1193 #else
1194         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1195 #endif
1196         if (ret) {
1197                 printf("%s clk get failed %d\n", __func__, ret);
1198                 return ret;
1199         }
1200
1201         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1202         if (ret < 0) {
1203                 printf("%s clk set failed %d\n", __func__, ret);
1204                 return ret;
1205         }
1206
1207         ret = sdram_init(priv, params);
1208         if (ret < 0) {
1209                 printf("%s DRAM init failed %d\n", __func__, ret);
1210                 return ret;
1211         }
1212
1213         return 0;
1214 }
1215 #endif
1216
1217 static int rk3399_dmc_probe(struct udevice *dev)
1218 {
1219 #if defined(CONFIG_TPL_BUILD) || \
1220         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1221         if (rk3399_dmc_init(dev))
1222                 return 0;
1223 #else
1224         struct dram_info *priv = dev_get_priv(dev);
1225
1226         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1227         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1228         priv->info.base = CONFIG_SYS_SDRAM_BASE;
1229         priv->info.size =
1230                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1231 #endif
1232         return 0;
1233 }
1234
1235 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1236 {
1237         struct dram_info *priv = dev_get_priv(dev);
1238
1239         *info = priv->info;
1240
1241         return 0;
1242 }
1243
1244 static struct ram_ops rk3399_dmc_ops = {
1245         .get_info = rk3399_dmc_get_info,
1246 };
1247
1248 static const struct udevice_id rk3399_dmc_ids[] = {
1249         { .compatible = "rockchip,rk3399-dmc" },
1250         { }
1251 };
1252
1253 U_BOOT_DRIVER(dmc_rk3399) = {
1254         .name = "rockchip_rk3399_dmc",
1255         .id = UCLASS_RAM,
1256         .of_match = rk3399_dmc_ids,
1257         .ops = &rk3399_dmc_ops,
1258 #if defined(CONFIG_TPL_BUILD) || \
1259         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1260         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1261 #endif
1262         .probe = rk3399_dmc_probe,
1263         .priv_auto_alloc_size = sizeof(struct dram_info),
1264 #if defined(CONFIG_TPL_BUILD) || \
1265         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1266         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1267 #endif
1268 };