drivers/ram/rockchip/sdram_rk3399.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * (C) Copyright 2016-2017 Rockchip Inc.
   4  *
   5  * Adapted from coreboot.
   6  */
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <dt-structs.h>
  12 #include <ram.h>
  13 #include <regmap.h>
  14 #include <syscon.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-rockchip/clock.h>
  17 #include <asm/arch-rockchip/cru_rk3399.h>
  18 #include <asm/arch-rockchip/grf_rk3399.h>
  19 #include <asm/arch-rockchip/hardware.h>
  20 #include <asm/arch-rockchip/sdram_common.h>
  21 #include <asm/arch-rockchip/sdram_rk3399.h>
  22 #include <linux/err.h>
  23 #include <time.h>
  24
  25 #define PRESET_SGRF_HOLD(n)     ((0x1 << (6 + 16)) | ((n) << 6))
  26 #define PRESET_GPIO0_HOLD(n)    ((0x1 << (7 + 16)) | ((n) << 7))
  27 #define PRESET_GPIO1_HOLD(n)    ((0x1 << (8 + 16)) | ((n) << 8))
  28
  29 #define PHY_DRV_ODT_HI_Z        0x0
  30 #define PHY_DRV_ODT_240         0x1
  31 #define PHY_DRV_ODT_120         0x8
  32 #define PHY_DRV_ODT_80          0x9
  33 #define PHY_DRV_ODT_60          0xc
  34 #define PHY_DRV_ODT_48          0xd
  35 #define PHY_DRV_ODT_40          0xe
  36 #define PHY_DRV_ODT_34_3        0xf
  37
  38 #define PHY_BOOSTP_EN           0x1
  39 #define PHY_BOOSTN_EN           0x1
  40 #define PHY_SLEWP_EN            0x1
  41 #define PHY_SLEWN_EN            0x1
  42 #define PHY_RX_CM_INPUT         0x1
  43
  44 #define CRU_SFTRST_DDR_CTRL(ch, n)      ((0x1 << (8 + 16 + (ch) * 4)) | \
  45                                         ((n) << (8 + (ch) * 4)))
  46 #define CRU_SFTRST_DDR_PHY(ch, n)       ((0x1 << (9 + 16 + (ch) * 4)) | \
  47                                         ((n) << (9 + (ch) * 4)))
  48 struct chan_info {
  49         struct rk3399_ddr_pctl_regs *pctl;
  50         struct rk3399_ddr_pi_regs *pi;
  51         struct rk3399_ddr_publ_regs *publ;
  52         struct rk3399_msch_regs *msch;
  53 };
  54
  55 struct dram_info {
  56 #if defined(CONFIG_TPL_BUILD) || \
  57         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  58         u32 pwrup_srefresh_exit[2];
  59         struct chan_info chan[2];
  60         struct clk ddr_clk;
  61         struct rk3399_cru *cru;
  62         struct rk3399_grf_regs *grf;
  63         struct rk3399_pmucru *pmucru;
  64         struct rk3399_pmusgrf_regs *pmusgrf;
  65         struct rk3399_ddr_cic_regs *cic;
  66 #endif
  67         struct ram_info info;
  68         struct rk3399_pmugrf_regs *pmugrf;
  69 };
  70
  71 #if defined(CONFIG_TPL_BUILD) || \
  72         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
  73
  74 struct rockchip_dmc_plat {
  75 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  76         struct dtd_rockchip_rk3399_dmc dtplat;
  77 #else
  78         struct rk3399_sdram_params sdram_params;
  79 #endif
  80         struct regmap *map;
  81 };
  82
  83 struct io_setting {
  84         u32 mhz;
  85         u32 mr5;
  86         /* dram side */
  87         u32 dq_odt;
  88         u32 ca_odt;
  89         u32 pdds;
  90         u32 dq_vref;
  91         u32 ca_vref;
  92         /* phy side */
  93         u32 rd_odt;
  94         u32 wr_dq_drv;
  95         u32 wr_ca_drv;
  96         u32 wr_ckcs_drv;
  97         u32 rd_odt_en;
  98         u32 rd_vref;
  99 } lpddr4_io_setting[] = {
 100         {
 101                 50 * MHz,
 102                 0,
 103                 /* dram side */
 104                 0,      /* dq_odt; */
 105                 0,      /* ca_odt; */
 106                 6,      /* pdds; */
 107                 0x72,   /* dq_vref; */
 108                 0x72,   /* ca_vref; */
 109                 /* phy side */
 110                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 111                 PHY_DRV_ODT_40, /* wr_dq_drv; */
 112                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 113                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 114                 0,      /* rd_odt_en;*/
 115                 41,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 116         },
 117         {
 118                 600 * MHz,
 119                 0,
 120                 /* dram side */
 121                 1,      /* dq_odt; */
 122                 0,      /* ca_odt; */
 123                 6,      /* pdds; */
 124                 0x72,   /* dq_vref; */
 125                 0x72,   /* ca_vref; */
 126                 /* phy side */
 127                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 128                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 129                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 130                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 131                 0,      /* rd_odt_en; */
 132                 32,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 133         },
 134         {
 135                 800 * MHz,
 136                 0,
 137                 /* dram side */
 138                 1,      /* dq_odt; */
 139                 0,      /* ca_odt; */
 140                 1,      /* pdds; */
 141                 0x72,   /* dq_vref; */
 142                 0x72,   /* ca_vref; */
 143                 /* phy side */
 144                 PHY_DRV_ODT_40, /* rd_odt; */
 145                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 146                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 147                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 148                 1,      /* rd_odt_en; */
 149                 17,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 150         },
 151         {
 152                 933 * MHz,
 153                 0,
 154                 /* dram side */
 155                 3,      /* dq_odt; */
 156                 0,      /* ca_odt; */
 157                 6,      /* pdds; */
 158                 0x59,   /* dq_vref; 32% */
 159                 0x72,   /* ca_vref; */
 160                 /* phy side */
 161                 PHY_DRV_ODT_HI_Z,       /* rd_odt; */
 162                 PHY_DRV_ODT_48, /* wr_dq_drv; */
 163                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 164                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 165                 0,      /* rd_odt_en; */
 166                 32,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 167         },
 168         {
 169                 1066 * MHz,
 170                 0,
 171                 /* dram side */
 172                 6,      /* dq_odt; */
 173                 0,      /* ca_odt; */
 174                 1,      /* pdds; */
 175                 0x10,   /* dq_vref; */
 176                 0x72,   /* ca_vref; */
 177                 /* phy side */
 178                 PHY_DRV_ODT_40, /* rd_odt; */
 179                 PHY_DRV_ODT_60, /* wr_dq_drv; */
 180                 PHY_DRV_ODT_40, /* wr_ca_drv; */
 181                 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
 182                 1,      /* rd_odt_en; */
 183                 17,     /* rd_vref; (unit %, range 3.3% - 48.7%) */
 184         },
 185 };
 186
 187 /**
 188  * phy = 0, PHY boot freq
 189  * phy = 1, PHY index 0
 190  * phy = 2, PHY index 1
 191  */
 192 static struct io_setting *
 193 lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
 194 {
 195         struct io_setting *io = NULL;
 196         u32 n;
 197
 198         for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
 199                 io = &lpddr4_io_setting[n];
 200
 201                 if (io->mr5 != 0) {
 202                         if (io->mhz >= params->base.ddr_freq &&
 203                             io->mr5 == mr5)
 204                                 break;
 205                 } else {
 206                         if (io->mhz >= params->base.ddr_freq)
 207                                 break;
 208                 }
 209         }
 210
 211         return io;
 212 }
 213
 214 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
 215 {
 216         return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
 217 }
 218
 219 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
 220 {
 221         int i;
 222
 223         for (i = 0; i < n / sizeof(u32); i++) {
 224                 writel(*src, dest);
 225                 src++;
 226                 dest++;
 227         }
 228 }
 229
 230 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
 231                             u32 phy)
 232 {
 233         channel &= 0x1;
 234         ctl &= 0x1;
 235         phy &= 0x1;
 236         writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
 237                                    CRU_SFTRST_DDR_PHY(channel, phy),
 238                                    &cru->softrst_con[4]);
 239 }
 240
 241 static void phy_pctrl_reset(struct rk3399_cru *cru,  u32 channel)
 242 {
 243         rkclk_ddr_reset(cru, channel, 1, 1);
 244         udelay(10);
 245
 246         rkclk_ddr_reset(cru, channel, 1, 0);
 247         udelay(10);
 248
 249         rkclk_ddr_reset(cru, channel, 0, 0);
 250         udelay(10);
 251 }
 252
 253 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
 254                                u32 freq)
 255 {
 256         u32 *denali_phy = ddr_publ_regs->denali_phy;
 257
 258         /* From IP spec, only freq small than 125 can enter dll bypass mode */
 259         if (freq <= 125) {
 260                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 261                 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 262                 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 263                 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 264                 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 265
 266                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 267                 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 268                 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 269                 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 270         } else {
 271                 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
 272                 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
 273                 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
 274                 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
 275                 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
 276
 277                 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
 278                 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
 279                 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
 280                 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
 281         }
 282 }
 283
 284 static void set_memory_map(const struct chan_info *chan, u32 channel,
 285                            const struct rk3399_sdram_params *params)
 286 {
 287         const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
 288         u32 *denali_ctl = chan->pctl->denali_ctl;
 289         u32 *denali_pi = chan->pi->denali_pi;
 290         u32 cs_map;
 291         u32 reduc;
 292         u32 row;
 293
 294         /* Get row number from ddrconfig setting */
 295         if (sdram_ch->cap_info.ddrconfig < 2 ||
 296             sdram_ch->cap_info.ddrconfig == 4)
 297                 row = 16;
 298         else if (sdram_ch->cap_info.ddrconfig == 3)
 299                 row = 14;
 300         else
 301                 row = 15;
 302
 303         cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
 304         reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
 305
 306         /* Set the dram configuration to ctrl */
 307         clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
 308         clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
 309                         ((3 - sdram_ch->cap_info.bk) << 16) |
 310                         ((16 - row) << 24));
 311
 312         clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
 313                         cs_map | (reduc << 16));
 314
 315         /* PI_199 PI_COL_DIFF:RW:0:4 */
 316         clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
 317
 318         /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
 319         clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 320                         ((3 - sdram_ch->cap_info.bk) << 16) |
 321                         ((16 - row) << 24));
 322
 323         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 324                 if (cs_map == 1)
 325                         cs_map = 0x5;
 326                 else if (cs_map == 2)
 327                         cs_map = 0xa;
 328                 else
 329                         cs_map = 0xF;
 330         }
 331
 332         /* PI_41 PI_CS_MAP:RW:24:4 */
 333         clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 334         if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
 335                 writel(0x2EC7FFFF, &denali_pi[34]);
 336 }
 337
 338 static int phy_io_config(const struct chan_info *chan,
 339                          const struct rk3399_sdram_params *params)
 340 {
 341         u32 *denali_phy = chan->publ->denali_phy;
 342         u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
 343         u32 mode_sel;
 344         u32 reg_value;
 345         u32 drv_value, odt_value;
 346         u32 speed;
 347
 348         /* vref setting */
 349         if (params->base.dramtype == LPDDR4) {
 350                 /* LPDDR4 */
 351                 vref_mode_dq = 0x6;
 352                 vref_value_dq = 0x1f;
 353                 vref_mode_ac = 0x6;
 354                 vref_value_ac = 0x1f;
 355                 mode_sel = 0x6;
 356         } else if (params->base.dramtype == LPDDR3) {
 357                 if (params->base.odt == 1) {
 358                         vref_mode_dq = 0x5;  /* LPDDR3 ODT */
 359                         drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
 360                         odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
 361                         if (drv_value == PHY_DRV_ODT_48) {
 362                                 switch (odt_value) {
 363                                 case PHY_DRV_ODT_240:
 364                                         vref_value_dq = 0x16;
 365                                         break;
 366                                 case PHY_DRV_ODT_120:
 367                                         vref_value_dq = 0x26;
 368                                         break;
 369                                 case PHY_DRV_ODT_60:
 370                                         vref_value_dq = 0x36;
 371                                         break;
 372                                 default:
 373                                         debug("Invalid ODT value.\n");
 374                                         return -EINVAL;
 375                                 }
 376                         } else if (drv_value == PHY_DRV_ODT_40) {
 377                                 switch (odt_value) {
 378                                 case PHY_DRV_ODT_240:
 379                                         vref_value_dq = 0x19;
 380                                         break;
 381                                 case PHY_DRV_ODT_120:
 382                                         vref_value_dq = 0x23;
 383                                         break;
 384                                 case PHY_DRV_ODT_60:
 385                                         vref_value_dq = 0x31;
 386                                         break;
 387                                 default:
 388                                         debug("Invalid ODT value.\n");
 389                                         return -EINVAL;
 390                                 }
 391                         } else if (drv_value == PHY_DRV_ODT_34_3) {
 392                                 switch (odt_value) {
 393                                 case PHY_DRV_ODT_240:
 394                                         vref_value_dq = 0x17;
 395                                         break;
 396                                 case PHY_DRV_ODT_120:
 397                                         vref_value_dq = 0x20;
 398                                         break;
 399                                 case PHY_DRV_ODT_60:
 400                                         vref_value_dq = 0x2e;
 401                                         break;
 402                                 default:
 403                                         debug("Invalid ODT value.\n");
 404                                         return -EINVAL;
 405                                 }
 406                         } else {
 407                                 debug("Invalid DRV value.\n");
 408                                 return -EINVAL;
 409                         }
 410                 } else {
 411                         vref_mode_dq = 0x2;  /* LPDDR3 */
 412                         vref_value_dq = 0x1f;
 413                 }
 414                 vref_mode_ac = 0x2;
 415                 vref_value_ac = 0x1f;
 416                 mode_sel = 0x0;
 417         } else if (params->base.dramtype == DDR3) {
 418                 /* DDR3L */
 419                 vref_mode_dq = 0x1;
 420                 vref_value_dq = 0x1f;
 421                 vref_mode_ac = 0x1;
 422                 vref_value_ac = 0x1f;
 423                 mode_sel = 0x1;
 424         } else {
 425                 debug("Unknown DRAM type.\n");
 426                 return -EINVAL;
 427         }
 428
 429         reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
 430
 431         /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
 432         clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
 433         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
 434         clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
 435         /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
 436         clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
 437         /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
 438         clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
 439
 440         reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
 441
 442         /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 443         clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 444
 445         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 446         clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 447         /* PHY_926 PHY_PAD_DATA_DRIVE */
 448         clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
 449         /* PHY_927 PHY_PAD_DQS_DRIVE */
 450         clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
 451         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 452         clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
 453         /* PHY_929 PHY_PAD_CLK_DRIVE */
 454         clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
 455         /* PHY_935 PHY_PAD_CKE_DRIVE */
 456         clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
 457         /* PHY_937 PHY_PAD_RST_DRIVE */
 458         clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
 459         /* PHY_939 PHY_PAD_CS_DRIVE */
 460         clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 461
 462         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 463                 /* BOOSTP_EN & BOOSTN_EN */
 464                 reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
 465                 /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
 466                 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
 467                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 468                 clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
 469                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 470                 clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
 471                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 472                 clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
 473                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 474                 clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
 475                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 476                 clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
 477                 /* PHY_937 PHY_PAD_RST_DRIVE */
 478                 clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
 479                 /* PHY_939 PHY_PAD_CS_DRIVE */
 480                 clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
 481
 482                 /* SLEWP_EN & SLEWN_EN */
 483                 reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
 484                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 485                 clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
 486                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 487                 clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
 488                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 489                 clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
 490                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 491                 clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
 492                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 493                 clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
 494                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 495                 clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
 496                 /* PHY_937 PHY_PAD_RST_DRIVE */
 497                 clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
 498                 /* PHY_939 PHY_PAD_CS_DRIVE */
 499                 clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
 500         }
 501
 502         /* speed setting */
 503         if (params->base.ddr_freq < 400)
 504                 speed = 0x0;
 505         else if (params->base.ddr_freq < 800)
 506                 speed = 0x1;
 507         else if (params->base.ddr_freq < 1200)
 508                 speed = 0x2;
 509         else
 510                 speed = 0x3;
 511
 512         /* PHY_924 PHY_PAD_FDBK_DRIVE */
 513         clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
 514         /* PHY_926 PHY_PAD_DATA_DRIVE */
 515         clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
 516         /* PHY_927 PHY_PAD_DQS_DRIVE */
 517         clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
 518         /* PHY_928 PHY_PAD_ADDR_DRIVE */
 519         clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
 520         /* PHY_929 PHY_PAD_CLK_DRIVE */
 521         clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
 522         /* PHY_935 PHY_PAD_CKE_DRIVE */
 523         clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
 524         /* PHY_937 PHY_PAD_RST_DRIVE */
 525         clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
 526         /* PHY_939 PHY_PAD_CS_DRIVE */
 527         clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 528
 529         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 530                 /* RX_CM_INPUT */
 531                 reg_value = PHY_RX_CM_INPUT;
 532                 /* PHY_924 PHY_PAD_FDBK_DRIVE */
 533                 clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
 534                 /* PHY_926 PHY_PAD_DATA_DRIVE */
 535                 clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
 536                 /* PHY_927 PHY_PAD_DQS_DRIVE */
 537                 clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
 538                 /* PHY_928 PHY_PAD_ADDR_DRIVE */
 539                 clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
 540                 /* PHY_929 PHY_PAD_CLK_DRIVE */
 541                 clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
 542                 /* PHY_935 PHY_PAD_CKE_DRIVE */
 543                 clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
 544                 /* PHY_937 PHY_PAD_RST_DRIVE */
 545                 clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
 546                 /* PHY_939 PHY_PAD_CS_DRIVE */
 547                 clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
 548         }
 549
 550         return 0;
 551 }
 552
 553 static void set_ds_odt(const struct chan_info *chan,
 554                        const struct rk3399_sdram_params *params, u32 mr5)
 555 {
 556         u32 *denali_phy = chan->publ->denali_phy;
 557
 558         u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 559         u32 tsel_idle_select_p, tsel_rd_select_p;
 560         u32 tsel_idle_select_n, tsel_rd_select_n;
 561         u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 562         u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 563         struct io_setting *io = NULL;
 564         u32 reg_value;
 565
 566         if (params->base.dramtype == LPDDR4) {
 567                 io = lpddr4_get_io_settings(params, mr5);
 568
 569                 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
 570                 tsel_rd_select_n = io->rd_odt;
 571
 572                 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 573                 tsel_idle_select_n = PHY_DRV_ODT_240;
 574
 575                 tsel_wr_select_dq_p = io->wr_dq_drv;
 576                 tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 577
 578                 tsel_wr_select_ca_p = io->wr_ca_drv;
 579                 tsel_wr_select_ca_n = PHY_DRV_ODT_40;
 580         } else if (params->base.dramtype == LPDDR3) {
 581                 tsel_rd_select_p = PHY_DRV_ODT_240;
 582                 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
 583
 584                 tsel_idle_select_p = PHY_DRV_ODT_240;
 585                 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 586
 587                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 588                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 589
 590                 tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 591                 tsel_wr_select_ca_n = PHY_DRV_ODT_48;
 592         } else {
 593                 tsel_rd_select_p = PHY_DRV_ODT_240;
 594                 tsel_rd_select_n = PHY_DRV_ODT_240;
 595
 596                 tsel_idle_select_p = PHY_DRV_ODT_240;
 597                 tsel_idle_select_n = PHY_DRV_ODT_240;
 598
 599                 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
 600                 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
 601
 602                 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 603                 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
 604         }
 605
 606         if (params->base.odt == 1)
 607                 tsel_rd_en = 1;
 608         else
 609                 tsel_rd_en = 0;
 610
 611         tsel_wr_en = 0;
 612         tsel_idle_en = 0;
 613
 614         /*
 615          * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 616          * sets termination values for read/idle cycles and drive strength
 617          * for write cycles for DQ/DM
 618          */
 619         reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
 620                     (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
 621                     (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
 622         clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
 623         clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
 624         clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
 625         clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
 626
 627         /*
 628          * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
 629          * sets termination values for read/idle cycles and drive strength
 630          * for write cycles for DQS
 631          */
 632         clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
 633         clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
 634         clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
 635         clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
 636
 637         /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 638         reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
 639         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 640                 /* LPDDR4 these register read always return 0, so
 641                  * can not use clrsetbits_le32(), need to write32
 642                  */
 643                 writel((0x300 << 8) | reg_value, &denali_phy[544]);
 644                 writel((0x300 << 8) | reg_value, &denali_phy[672]);
 645                 writel((0x300 << 8) | reg_value, &denali_phy[800]);
 646         } else {
 647                 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
 648                 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
 649                 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
 650         }
 651
 652         /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 653         clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 654
 655         /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
 656         clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 657
 658         /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 659         clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 660
 661         /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
 662         clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
 663
 664         /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
 665         clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
 666
 667         /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 668         clrsetbits_le32(&denali_phy[924], 0xff,
 669                         tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
 670         clrsetbits_le32(&denali_phy[925], 0xff,
 671                         tsel_rd_select_n | (tsel_rd_select_p << 4));
 672
 673         /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
 674         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 675                 << 16;
 676         clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
 677         clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
 678         clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
 679         clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
 680
 681         /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
 682         reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
 683                 << 24;
 684         clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
 685         clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
 686         clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
 687         clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
 688
 689         /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
 690         reg_value = tsel_wr_en << 8;
 691         clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
 692         clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
 693         clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
 694
 695         /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
 696         reg_value = tsel_wr_en << 17;
 697         clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
 698         /*
 699          * pad_rst/cke/cs/clk_term tsel 1bits
 700          * DENALI_PHY_938/936/940/934 offset_17
 701          */
 702         clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
 703         clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
 704         clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
 705         clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
 706
 707         /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 708         clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 709
 710         phy_io_config(chan, params);
 711 }
 712
 713 static void pctl_start(struct dram_info *dram, u8 channel)
 714 {
 715         const struct chan_info *chan = &dram->chan[channel];
 716         u32 *denali_ctl = chan->pctl->denali_ctl;
 717         u32 *denali_phy = chan->publ->denali_phy;
 718         u32 *ddrc0_con = get_ddrc0_con(dram, channel);
 719         u32 count = 0;
 720         u32 byte, tmp;
 721
 722         writel(0x01000000, &ddrc0_con);
 723
 724         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 725
 726         while (!(readl(&denali_ctl[203]) & (1 << 3))) {
 727                 if (count > 1000) {
 728                         printf("%s: Failed to init pctl for channel %d\n",
 729                                __func__, channel);
 730                         while (1)
 731                                 ;
 732                 }
 733
 734                 udelay(1);
 735                 count++;
 736         }
 737
 738         writel(0x01000100, &ddrc0_con);
 739
 740         for (byte = 0; byte < 4; byte++) {
 741                 tmp = 0x820;
 742                 writel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);
 743                 writel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);
 744                 writel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);
 745                 writel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);
 746                 writel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);
 747
 748                 clrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);
 749         }
 750
 751         clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,
 752                         dram->pwrup_srefresh_exit[channel]);
 753 }
 754
 755 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 756                     u32 channel, struct rk3399_sdram_params *params)
 757 {
 758         u32 *denali_ctl = chan->pctl->denali_ctl;
 759         u32 *denali_pi = chan->pi->denali_pi;
 760         u32 *denali_phy = chan->publ->denali_phy;
 761         const u32 *params_ctl = params->pctl_regs.denali_ctl;
 762         const u32 *params_phy = params->phy_regs.denali_phy;
 763         u32 tmp, tmp1, tmp2;
 764
 765         /*
 766          * work around controller bug:
 767          * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
 768          */
 769         copy_to_reg(&denali_ctl[1], &params_ctl[1],
 770                     sizeof(struct rk3399_ddr_pctl_regs) - 4);
 771         writel(params_ctl[0], &denali_ctl[0]);
 772
 773         /*
 774          * two channel init at the same time, then ZQ Cal Start
 775          * at the same time, it will use the same RZQ, but cannot
 776          * start at the same time.
 777          *
 778          * So, increase tINIT3 for channel 1, will avoid two
 779          * channel ZQ Cal Start at the same time
 780          */
 781         if (params->base.dramtype == LPDDR4 && channel == 1) {
 782                 tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
 783                 tmp1 = readl(&denali_ctl[14]);
 784                 writel(tmp + tmp1, &denali_ctl[14]);
 785         }
 786
 787         copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 788                     sizeof(struct rk3399_ddr_pi_regs));
 789
 790         /* rank count need to set for init */
 791         set_memory_map(chan, channel, params);
 792
 793         writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
 794         writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 795         writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 796
 797         if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
 798                 writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
 799                 writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
 800         }
 801
 802         dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
 803                                              PWRUP_SREFRESH_EXIT;
 804         clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
 805
 806         /* PHY_DLL_RST_EN */
 807         clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
 808
 809         setbits_le32(&denali_pi[0], START);
 810         setbits_le32(&denali_ctl[0], START);
 811
 812         /**
 813          * LPDDR4 use PLL bypass mode for init
 814          * not need to wait for the PLL to lock
 815          */
 816         if (params->base.dramtype != LPDDR4) {
 817                 /* Waiting for phy DLL lock */
 818                 while (1) {
 819                         tmp = readl(&denali_phy[920]);
 820                         tmp1 = readl(&denali_phy[921]);
 821                         tmp2 = readl(&denali_phy[922]);
 822                         if ((((tmp >> 16) & 0x1) == 0x1) &&
 823                             (((tmp1 >> 16) & 0x1) == 0x1) &&
 824                             (((tmp1 >> 0) & 0x1) == 0x1) &&
 825                             (((tmp2 >> 0) & 0x1) == 0x1))
 826                                 break;
 827                 }
 828         }
 829
 830         copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
 831         copy_to_reg(&denali_phy[0], &params_phy[0], (90 - 0 + 1) * 4);
 832         copy_to_reg(&denali_phy[128], &params_phy[128], (218 - 128 + 1) * 4);
 833         copy_to_reg(&denali_phy[256], &params_phy[256], (346 - 256 + 1) * 4);
 834         copy_to_reg(&denali_phy[384], &params_phy[384], (474 - 384 + 1) * 4);
 835         copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 836         copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 837         copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
 838         set_ds_odt(chan, params, 0);
 839
 840         /*
 841          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
 842          * dqs_tsel_wr_end[7:4] add Half cycle
 843          */
 844         tmp = (readl(&denali_phy[84]) >> 8) & 0xff;
 845         clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8);
 846         tmp = (readl(&denali_phy[212]) >> 8) & 0xff;
 847         clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8);
 848         tmp = (readl(&denali_phy[340]) >> 8) & 0xff;
 849         clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8);
 850         tmp = (readl(&denali_phy[468]) >> 8) & 0xff;
 851         clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8);
 852
 853         /*
 854          * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
 855          * dq_tsel_wr_end[7:4] add Half cycle
 856          */
 857         tmp = (readl(&denali_phy[83]) >> 16) & 0xff;
 858         clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16);
 859         tmp = (readl(&denali_phy[211]) >> 16) & 0xff;
 860         clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16);
 861         tmp = (readl(&denali_phy[339]) >> 16) & 0xff;
 862         clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16);
 863         tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 864         clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 865
 866         return 0;
 867 }
 868
 869 static void select_per_cs_training_index(const struct chan_info *chan,
 870                                          u32 rank)
 871 {
 872         u32 *denali_phy = chan->publ->denali_phy;
 873
 874         /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
 875         if ((readl(&denali_phy[84]) >> 16) & 1) {
 876                 /*
 877                  * PHY_8/136/264/392
 878                  * phy_per_cs_training_index_X 1bit offset_24
 879                  */
 880                 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
 881                 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
 882                 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
 883                 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
 884         }
 885 }
 886
 887 static void override_write_leveling_value(const struct chan_info *chan)
 888 {
 889         u32 *denali_ctl = chan->pctl->denali_ctl;
 890         u32 *denali_phy = chan->publ->denali_phy;
 891         u32 byte;
 892
 893         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 894         setbits_le32(&denali_phy[896], 1);
 895
 896         /*
 897          * PHY_8/136/264/392
 898          * phy_per_cs_training_multicast_en_X 1bit offset_16
 899          */
 900         clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
 901         clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
 902         clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
 903         clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
 904
 905         for (byte = 0; byte < 4; byte++)
 906                 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
 907                                 0x200 << 16);
 908
 909         /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
 910         clrbits_le32(&denali_phy[896], 1);
 911
 912         /* CTL_200 ctrlupd_req 1bit offset_8 */
 913         clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
 914 }
 915
 916 static int data_training_ca(const struct chan_info *chan, u32 channel,
 917                             const struct rk3399_sdram_params *params)
 918 {
 919         u32 *denali_pi = chan->pi->denali_pi;
 920         u32 *denali_phy = chan->publ->denali_phy;
 921         u32 i, tmp;
 922         u32 obs_0, obs_1, obs_2, obs_err = 0;
 923         u32 rank = params->ch[channel].cap_info.rank;
 924         u32 rank_mask;
 925
 926         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 927         writel(0x00003f7c, (&denali_pi[175]));
 928
 929         if (params->base.dramtype == LPDDR4)
 930                 rank_mask = (rank == 1) ? 0x5 : 0xf;
 931         else
 932                 rank_mask = (rank == 1) ? 0x1 : 0x3;
 933
 934         for (i = 0; i < 4; i++) {
 935                 if (!(rank_mask & (1 << i)))
 936                         continue;
 937
 938                 select_per_cs_training_index(chan, i);
 939
 940                 /* PI_100 PI_CALVL_EN:RW:8:2 */
 941                 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
 942
 943                 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
 944                 clrsetbits_le32(&denali_pi[92],
 945                                 (0x1 << 16) | (0x3 << 24),
 946                                 (0x1 << 16) | (i << 24));
 947
 948                 /* Waiting for training complete */
 949                 while (1) {
 950                         /* PI_174 PI_INT_STATUS:RD:8:18 */
 951                         tmp = readl(&denali_pi[174]) >> 8;
 952                         /*
 953                          * check status obs
 954                          * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
 955                          */
 956                         obs_0 = readl(&denali_phy[532]);
 957                         obs_1 = readl(&denali_phy[660]);
 958                         obs_2 = readl(&denali_phy[788]);
 959                         if (((obs_0 >> 30) & 0x3) ||
 960                             ((obs_1 >> 30) & 0x3) ||
 961                             ((obs_2 >> 30) & 0x3))
 962                                 obs_err = 1;
 963                         if ((((tmp >> 11) & 0x1) == 0x1) &&
 964                             (((tmp >> 13) & 0x1) == 0x1) &&
 965                             (((tmp >> 5) & 0x1) == 0x0) &&
 966                             obs_err == 0)
 967                                 break;
 968                         else if ((((tmp >> 5) & 0x1) == 0x1) ||
 969                                  (obs_err == 1))
 970                                 return -EIO;
 971                 }
 972
 973                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 974                 writel(0x00003f7c, (&denali_pi[175]));
 975         }
 976
 977         clrbits_le32(&denali_pi[100], 0x3 << 8);
 978
 979         return 0;
 980 }
 981
 982 static int data_training_wl(const struct chan_info *chan, u32 channel,
 983                             const struct rk3399_sdram_params *params)
 984 {
 985         u32 *denali_pi = chan->pi->denali_pi;
 986         u32 *denali_phy = chan->publ->denali_phy;
 987         u32 i, tmp;
 988         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
 989         u32 rank = params->ch[channel].cap_info.rank;
 990
 991         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 992         writel(0x00003f7c, (&denali_pi[175]));
 993
 994         for (i = 0; i < rank; i++) {
 995                 select_per_cs_training_index(chan, i);
 996
 997                 /* PI_60 PI_WRLVL_EN:RW:8:2 */
 998                 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
 999
1000                 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
1001                 clrsetbits_le32(&denali_pi[59],
1002                                 (0x1 << 8) | (0x3 << 16),
1003                                 (0x1 << 8) | (i << 16));
1004
1005                 /* Waiting for training complete */
1006                 while (1) {
1007                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1008                         tmp = readl(&denali_pi[174]) >> 8;
1009
1010                         /*
1011                          * check status obs, if error maybe can not
1012                          * get leveling done PHY_40/168/296/424
1013                          * phy_wrlvl_status_obs_X:0:13
1014                          */
1015                         obs_0 = readl(&denali_phy[40]);
1016                         obs_1 = readl(&denali_phy[168]);
1017                         obs_2 = readl(&denali_phy[296]);
1018                         obs_3 = readl(&denali_phy[424]);
1019                         if (((obs_0 >> 12) & 0x1) ||
1020                             ((obs_1 >> 12) & 0x1) ||
1021                             ((obs_2 >> 12) & 0x1) ||
1022                             ((obs_3 >> 12) & 0x1))
1023                                 obs_err = 1;
1024                         if ((((tmp >> 10) & 0x1) == 0x1) &&
1025                             (((tmp >> 13) & 0x1) == 0x1) &&
1026                             (((tmp >> 4) & 0x1) == 0x0) &&
1027                             obs_err == 0)
1028                                 break;
1029                         else if ((((tmp >> 4) & 0x1) == 0x1) ||
1030                                  (obs_err == 1))
1031                                 return -EIO;
1032                 }
1033
1034                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1035                 writel(0x00003f7c, (&denali_pi[175]));
1036         }
1037
1038         override_write_leveling_value(chan);
1039         clrbits_le32(&denali_pi[60], 0x3 << 8);
1040
1041         return 0;
1042 }
1043
1044 static int data_training_rg(const struct chan_info *chan, u32 channel,
1045                             const struct rk3399_sdram_params *params)
1046 {
1047         u32 *denali_pi = chan->pi->denali_pi;
1048         u32 *denali_phy = chan->publ->denali_phy;
1049         u32 i, tmp;
1050         u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1051         u32 rank = params->ch[channel].cap_info.rank;
1052
1053         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1054         writel(0x00003f7c, (&denali_pi[175]));
1055
1056         for (i = 0; i < rank; i++) {
1057                 select_per_cs_training_index(chan, i);
1058
1059                 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
1060                 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
1061
1062                 /*
1063                  * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
1064                  * PI_RDLVL_CS:RW:24:2
1065                  */
1066                 clrsetbits_le32(&denali_pi[74],
1067                                 (0x1 << 16) | (0x3 << 24),
1068                                 (0x1 << 16) | (i << 24));
1069
1070                 /* Waiting for training complete */
1071                 while (1) {
1072                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1073                         tmp = readl(&denali_pi[174]) >> 8;
1074
1075                         /*
1076                          * check status obs
1077                          * PHY_43/171/299/427
1078                          *     PHY_GTLVL_STATUS_OBS_x:16:8
1079                          */
1080                         obs_0 = readl(&denali_phy[43]);
1081                         obs_1 = readl(&denali_phy[171]);
1082                         obs_2 = readl(&denali_phy[299]);
1083                         obs_3 = readl(&denali_phy[427]);
1084                         if (((obs_0 >> (16 + 6)) & 0x3) ||
1085                             ((obs_1 >> (16 + 6)) & 0x3) ||
1086                             ((obs_2 >> (16 + 6)) & 0x3) ||
1087                             ((obs_3 >> (16 + 6)) & 0x3))
1088                                 obs_err = 1;
1089                         if ((((tmp >> 9) & 0x1) == 0x1) &&
1090                             (((tmp >> 13) & 0x1) == 0x1) &&
1091                             (((tmp >> 3) & 0x1) == 0x0) &&
1092                             obs_err == 0)
1093                                 break;
1094                         else if ((((tmp >> 3) & 0x1) == 0x1) ||
1095                                  (obs_err == 1))
1096                                 return -EIO;
1097                 }
1098
1099                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1100                 writel(0x00003f7c, (&denali_pi[175]));
1101         }
1102
1103         clrbits_le32(&denali_pi[80], 0x3 << 24);
1104
1105         return 0;
1106 }
1107
1108 static int data_training_rl(const struct chan_info *chan, u32 channel,
1109                             const struct rk3399_sdram_params *params)
1110 {
1111         u32 *denali_pi = chan->pi->denali_pi;
1112         u32 i, tmp;
1113         u32 rank = params->ch[channel].cap_info.rank;
1114
1115         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1116         writel(0x00003f7c, (&denali_pi[175]));
1117
1118         for (i = 0; i < rank; i++) {
1119                 select_per_cs_training_index(chan, i);
1120
1121                 /* PI_80 PI_RDLVL_EN:RW:16:2 */
1122                 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
1123
1124                 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
1125                 clrsetbits_le32(&denali_pi[74],
1126                                 (0x1 << 8) | (0x3 << 24),
1127                                 (0x1 << 8) | (i << 24));
1128
1129                 /* Waiting for training complete */
1130                 while (1) {
1131                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1132                         tmp = readl(&denali_pi[174]) >> 8;
1133
1134                         /*
1135                          * make sure status obs not report error bit
1136                          * PHY_46/174/302/430
1137                          *     phy_rdlvl_status_obs_X:16:8
1138                          */
1139                         if ((((tmp >> 8) & 0x1) == 0x1) &&
1140                             (((tmp >> 13) & 0x1) == 0x1) &&
1141                             (((tmp >> 2) & 0x1) == 0x0))
1142                                 break;
1143                         else if (((tmp >> 2) & 0x1) == 0x1)
1144                                 return -EIO;
1145                 }
1146
1147                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1148                 writel(0x00003f7c, (&denali_pi[175]));
1149         }
1150
1151         clrbits_le32(&denali_pi[80], 0x3 << 16);
1152
1153         return 0;
1154 }
1155
1156 static int data_training_wdql(const struct chan_info *chan, u32 channel,
1157                               const struct rk3399_sdram_params *params)
1158 {
1159         u32 *denali_pi = chan->pi->denali_pi;
1160         u32 i, tmp;
1161         u32 rank = params->ch[channel].cap_info.rank;
1162         u32 rank_mask;
1163
1164         /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1165         writel(0x00003f7c, (&denali_pi[175]));
1166
1167         if (params->base.dramtype == LPDDR4)
1168                 rank_mask = (rank == 1) ? 0x5 : 0xf;
1169         else
1170                 rank_mask = (rank == 1) ? 0x1 : 0x3;
1171
1172         for (i = 0; i < 4; i++) {
1173                 if (!(rank_mask & (1 << i)))
1174                         continue;
1175
1176                 select_per_cs_training_index(chan, i);
1177
1178                 /*
1179                  * disable PI_WDQLVL_VREF_EN before wdq leveling?
1180                  * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
1181                  */
1182                 clrbits_le32(&denali_pi[181], 0x1 << 8);
1183
1184                 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
1185                 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
1186
1187                 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
1188                 clrsetbits_le32(&denali_pi[121],
1189                                 (0x1 << 8) | (0x3 << 16),
1190                                 (0x1 << 8) | (i << 16));
1191
1192                 /* Waiting for training complete */
1193                 while (1) {
1194                         /* PI_174 PI_INT_STATUS:RD:8:18 */
1195                         tmp = readl(&denali_pi[174]) >> 8;
1196                         if ((((tmp >> 12) & 0x1) == 0x1) &&
1197                             (((tmp >> 13) & 0x1) == 0x1) &&
1198                             (((tmp >> 6) & 0x1) == 0x0))
1199                                 break;
1200                         else if (((tmp >> 6) & 0x1) == 0x1)
1201                                 return -EIO;
1202                 }
1203
1204                 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1205                 writel(0x00003f7c, (&denali_pi[175]));
1206         }
1207
1208         clrbits_le32(&denali_pi[124], 0x3 << 16);
1209
1210         return 0;
1211 }
1212
1213 static int data_training(const struct chan_info *chan, u32 channel,
1214                          const struct rk3399_sdram_params *params,
1215                          u32 training_flag)
1216 {
1217         u32 *denali_phy = chan->publ->denali_phy;
1218         int ret;
1219
1220         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1221         setbits_le32(&denali_phy[927], (1 << 22));
1222
1223         if (training_flag == PI_FULL_TRAINING) {
1224                 if (params->base.dramtype == LPDDR4) {
1225                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1226                                         PI_READ_GATE_TRAINING |
1227                                         PI_READ_LEVELING | PI_WDQ_LEVELING;
1228                 } else if (params->base.dramtype == LPDDR3) {
1229                         training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1230                                         PI_READ_GATE_TRAINING;
1231                 } else if (params->base.dramtype == DDR3) {
1232                         training_flag = PI_WRITE_LEVELING |
1233                                         PI_READ_GATE_TRAINING |
1234                                         PI_READ_LEVELING;
1235                 }
1236         }
1237
1238         /* ca training(LPDDR4,LPDDR3 support) */
1239         if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
1240                 ret = data_training_ca(chan, channel, params);
1241                 if (ret < 0) {
1242                         debug("%s: data training ca failed\n", __func__);
1243                         return ret;
1244                 }
1245         }
1246
1247         /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1248         if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
1249                 ret = data_training_wl(chan, channel, params);
1250                 if (ret < 0) {
1251                         debug("%s: data training wl failed\n", __func__);
1252                         return ret;
1253                 }
1254         }
1255
1256         /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1257         if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
1258                 ret = data_training_rg(chan, channel, params);
1259                 if (ret < 0) {
1260                         debug("%s: data training rg failed\n", __func__);
1261                         return ret;
1262                 }
1263         }
1264
1265         /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1266         if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
1267                 ret = data_training_rl(chan, channel, params);
1268                 if (ret < 0) {
1269                         debug("%s: data training rl failed\n", __func__);
1270                         return ret;
1271                 }
1272         }
1273
1274         /* wdq leveling(LPDDR4 support) */
1275         if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1276                 ret = data_training_wdql(chan, channel, params);
1277                 if (ret < 0) {
1278                         debug("%s: data training wdql failed\n", __func__);
1279                         return ret;
1280                 }
1281         }
1282
1283         /* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
1284         clrbits_le32(&denali_phy[927], (1 << 22));
1285
1286         return 0;
1287 }
1288
1289 static void set_ddrconfig(const struct chan_info *chan,
1290                           const struct rk3399_sdram_params *params,
1291                           unsigned char channel, u32 ddrconfig)
1292 {
1293         /* only need to set ddrconfig */
1294         struct rk3399_msch_regs *ddr_msch_regs = chan->msch;
1295         unsigned int cs0_cap = 0;
1296         unsigned int cs1_cap = 0;
1297
1298         cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1299                         + params->ch[channel].cap_info.col
1300                         + params->ch[channel].cap_info.bk
1301                         + params->ch[channel].cap_info.bw - 20));
1302         if (params->ch[channel].cap_info.rank > 1)
1303                 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1304                                 - params->ch[channel].cap_info.cs1_row);
1305         if (params->ch[channel].cap_info.row_3_4) {
1306                 cs0_cap = cs0_cap * 3 / 4;
1307                 cs1_cap = cs1_cap * 3 / 4;
1308         }
1309
1310         writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1311         writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1312                &ddr_msch_regs->ddrsize);
1313 }
1314
1315 static void dram_all_config(struct dram_info *dram,
1316                             const struct rk3399_sdram_params *params)
1317 {
1318         u32 sys_reg2 = 0;
1319         u32 sys_reg3 = 0;
1320         unsigned int channel, idx;
1321
1322         sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
1323         sys_reg2 |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
1324
1325         for (channel = 0, idx = 0;
1326              (idx < params->base.num_channels) && (channel < 2);
1327              channel++) {
1328                 const struct rk3399_sdram_channel *info = &params->ch[channel];
1329                 struct rk3399_msch_regs *ddr_msch_regs;
1330                 const struct rk3399_msch_timings *noc_timing;
1331
1332                 if (params->ch[channel].cap_info.col == 0)
1333                         continue;
1334                 idx++;
1335                 sys_reg2 |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
1336                 sys_reg2 |= SYS_REG_ENC_CHINFO(channel);
1337                 sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
1338                 sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
1339                 sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
1340                 sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
1341                 sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
1342                 SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
1343                 if (info->cap_info.cs1_row)
1344                         SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
1345                                             sys_reg3, channel);
1346                 sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
1347                 sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
1348
1349                 ddr_msch_regs = dram->chan[channel].msch;
1350                 noc_timing = &params->ch[channel].noc_timings;
1351                 writel(noc_timing->ddrtiminga0,
1352                        &ddr_msch_regs->ddrtiminga0);
1353                 writel(noc_timing->ddrtimingb0,
1354                        &ddr_msch_regs->ddrtimingb0);
1355                 writel(noc_timing->ddrtimingc0.d32,
1356                        &ddr_msch_regs->ddrtimingc0);
1357                 writel(noc_timing->devtodev0,
1358                        &ddr_msch_regs->devtodev0);
1359                 writel(noc_timing->ddrmode.d32,
1360                        &ddr_msch_regs->ddrmode);
1361
1362                 /**
1363                  * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
1364                  *
1365                  * The hardware for LPDDR4 with
1366                  * - CLK0P/N connect to lower 16-bits
1367                  * - CLK1P/N connect to higher 16-bits
1368                  *
1369                  * dfi dram clk is configured via CLK1P/N, so disabling
1370                  * dfi dram clk will disable the CLK1P/N as well for lpddr4.
1371                  */
1372                 if (params->ch[channel].cap_info.rank == 1 &&
1373                     params->base.dramtype != LPDDR4)
1374                         setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1375                                      1 << 17);
1376         }
1377
1378         writel(sys_reg2, &dram->pmugrf->os_reg2);
1379         writel(sys_reg3, &dram->pmugrf->os_reg3);
1380         rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1381                      params->base.stride << 10);
1382
1383         /* reboot hold register set */
1384         writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1385                 PRESET_GPIO1_HOLD(1),
1386                 &dram->pmucru->pmucru_rstnhold_con[1]);
1387         clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1388 }
1389
1390 static int switch_to_phy_index1(struct dram_info *dram,
1391                                 const struct rk3399_sdram_params *params)
1392 {
1393         u32 channel;
1394         u32 *denali_phy;
1395         u32 ch_count = params->base.num_channels;
1396         int ret;
1397         int i = 0;
1398
1399         writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1400                              1 << 4 | 1 << 2 | 1),
1401                         &dram->cic->cic_ctrl0);
1402         while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1403                 mdelay(10);
1404                 i++;
1405                 if (i > 10) {
1406                         debug("index1 frequency change overtime\n");
1407                         return -ETIME;
1408                 }
1409         }
1410
1411         i = 0;
1412         writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1413         while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1414                 mdelay(10);
1415                 i++;
1416                 if (i > 10) {
1417                         debug("index1 frequency done overtime\n");
1418                         return -ETIME;
1419                 }
1420         }
1421
1422         for (channel = 0; channel < ch_count; channel++) {
1423                 denali_phy = dram->chan[channel].publ->denali_phy;
1424                 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1425                 ret = data_training(&dram->chan[channel], channel,
1426                                     params, PI_FULL_TRAINING);
1427                 if (ret < 0) {
1428                         debug("index1 training failed\n");
1429                         return ret;
1430                 }
1431         }
1432
1433         return 0;
1434 }
1435
1436 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
1437 {
1438         unsigned int stride = params->base.stride;
1439         unsigned int channel, chinfo = 0;
1440         unsigned int ch_cap[2] = {0, 0};
1441         u64 cap;
1442
1443         for (channel = 0; channel < 2; channel++) {
1444                 unsigned int cs0_cap = 0;
1445                 unsigned int cs1_cap = 0;
1446                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
1447
1448                 if (cap_info->col == 0)
1449                         continue;
1450
1451                 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
1452                                  cap_info->bk + cap_info->bw - 20));
1453                 if (cap_info->rank > 1)
1454                         cs1_cap = cs0_cap >> (cap_info->cs0_row
1455                                               - cap_info->cs1_row);
1456                 if (cap_info->row_3_4) {
1457                         cs0_cap = cs0_cap * 3 / 4;
1458                         cs1_cap = cs1_cap * 3 / 4;
1459                 }
1460                 ch_cap[channel] = cs0_cap + cs1_cap;
1461                 chinfo |= 1 << channel;
1462         }
1463
1464         /* stride calculation for 1 channel */
1465         if (params->base.num_channels == 1 && chinfo & 1)
1466                 return 0x17;    /* channel a */
1467
1468         /* stride calculation for 2 channels, default gstride type is 256B */
1469         if (ch_cap[0] == ch_cap[1]) {
1470                 cap = ch_cap[0] + ch_cap[1];
1471                 switch (cap) {
1472                 /* 512MB */
1473                 case 512:
1474                         stride = 0;
1475                         break;
1476                 /* 1GB */
1477                 case 1024:
1478                         stride = 0x5;
1479                         break;
1480                 /*
1481                  * 768MB + 768MB same as total 2GB memory
1482                  * useful space: 0-768MB 1GB-1792MB
1483                  */
1484                 case 1536:
1485                 /* 2GB */
1486                 case 2048:
1487                         stride = 0x9;
1488                         break;
1489                 /* 1536MB + 1536MB */
1490                 case 3072:
1491                         stride = 0x11;
1492                         break;
1493                 /* 4GB */
1494                 case 4096:
1495                         stride = 0xD;
1496                         break;
1497                 default:
1498                         printf("%s: Unable to calculate stride for ", __func__);
1499                         print_size((cap * (1 << 20)), " capacity\n");
1500                         break;
1501                 }
1502         }
1503
1504         sdram_print_stride(stride);
1505
1506         return stride;
1507 }
1508
1509 static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
1510 {
1511         params->ch[channel].cap_info.rank = 0;
1512         params->ch[channel].cap_info.col = 0;
1513         params->ch[channel].cap_info.bk = 0;
1514         params->ch[channel].cap_info.bw = 32;
1515         params->ch[channel].cap_info.dbw = 32;
1516         params->ch[channel].cap_info.row_3_4 = 0;
1517         params->ch[channel].cap_info.cs0_row = 0;
1518         params->ch[channel].cap_info.cs1_row = 0;
1519         params->ch[channel].cap_info.ddrconfig = 0;
1520 }
1521
1522 static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)
1523 {
1524         int channel;
1525         int ret;
1526
1527         for (channel = 0; channel < 2; channel++) {
1528                 const struct chan_info *chan = &dram->chan[channel];
1529                 struct rk3399_cru *cru = dram->cru;
1530                 struct rk3399_ddr_publ_regs *publ = chan->publ;
1531
1532                 phy_pctrl_reset(cru, channel);
1533                 phy_dll_bypass_set(publ, params->base.ddr_freq);
1534
1535                 ret = pctl_cfg(dram, chan, channel, params);
1536                 if (ret < 0) {
1537                         printf("%s: pctl config failed\n", __func__);
1538                         return ret;
1539                 }
1540
1541                 /* start to trigger initialization */
1542                 pctl_start(dram, channel);
1543         }
1544
1545         return 0;
1546 }
1547
1548 static int sdram_init(struct dram_info *dram,
1549                       struct rk3399_sdram_params *params)
1550 {
1551         unsigned char dramtype = params->base.dramtype;
1552         unsigned int ddr_freq = params->base.ddr_freq;
1553         u32 training_flag = PI_READ_GATE_TRAINING;
1554         int channel, ch, rank;
1555         int ret;
1556
1557         debug("Starting SDRAM initialization...\n");
1558
1559         if ((dramtype == DDR3 && ddr_freq > 933) ||
1560             (dramtype == LPDDR3 && ddr_freq > 933) ||
1561             (dramtype == LPDDR4 && ddr_freq > 800)) {
1562                 debug("SDRAM frequency is to high!");
1563                 return -E2BIG;
1564         }
1565
1566         for (ch = 0; ch < 2; ch++) {
1567                 params->ch[ch].cap_info.rank = 2;
1568                 for (rank = 2; rank != 0; rank--) {
1569                         ret = pctl_init(dram, params);
1570                         if (ret < 0) {
1571                                 printf("%s: pctl init failed\n", __func__);
1572                                 return ret;
1573                         }
1574
1575                         /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
1576                         if (dramtype == LPDDR3)
1577                                 udelay(10);
1578
1579                         params->ch[ch].cap_info.rank = rank;
1580
1581                         /*
1582                          * LPDDR3 CA training msut be trigger before
1583                          * other training.
1584                          * DDR3 is not have CA training.
1585                          */
1586                         if (params->base.dramtype == LPDDR3)
1587                                 training_flag |= PI_CA_TRAINING;
1588
1589                         if (!(data_training(&dram->chan[ch], ch,
1590                                             params, training_flag)))
1591                                 break;
1592                 }
1593                 /* Computed rank with associated channel number */
1594                 params->ch[ch].cap_info.rank = rank;
1595         }
1596
1597         params->base.num_channels = 0;
1598         for (channel = 0; channel < 2; channel++) {
1599                 const struct chan_info *chan = &dram->chan[channel];
1600                 struct sdram_cap_info *cap_info = &params->ch[channel].cap_info;
1601                 u8 training_flag = PI_FULL_TRAINING;
1602
1603                 if (cap_info->rank == 0) {
1604                         clear_channel_params(params, channel);
1605                         continue;
1606                 } else {
1607                         params->base.num_channels++;
1608                 }
1609
1610                 debug("Channel ");
1611                 debug(channel ? "1: " : "0: ");
1612
1613                 /* LPDDR3 should have write and read gate training */
1614                 if (params->base.dramtype == LPDDR3)
1615                         training_flag = PI_WRITE_LEVELING |
1616                                         PI_READ_GATE_TRAINING;
1617
1618                 if (params->base.dramtype != LPDDR4) {
1619                         ret = data_training(dram, channel, params,
1620                                             training_flag);
1621                         if (!ret) {
1622                                 debug("%s: data train failed for channel %d\n",
1623                                       __func__, ret);
1624                                 continue;
1625                         }
1626                 }
1627
1628                 sdram_print_ddr_info(cap_info, &params->base);
1629
1630                 set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
1631         }
1632
1633         if (params->base.num_channels == 0) {
1634                 printf("%s: ", __func__);
1635                 sdram_print_dram_type(params->base.dramtype);
1636                 printf(" - %dMHz failed!\n", params->base.ddr_freq);
1637                 return -EINVAL;
1638         }
1639
1640         params->base.stride = calculate_stride(params);
1641         dram_all_config(dram, params);
1642         switch_to_phy_index1(dram, params);
1643
1644         debug("Finish SDRAM initialization...\n");
1645         return 0;
1646 }
1647
1648 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
1649 {
1650 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1651         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1652         int ret;
1653
1654         ret = dev_read_u32_array(dev, "rockchip,sdram-params",
1655                                  (u32 *)&plat->sdram_params,
1656                                  sizeof(plat->sdram_params) / sizeof(u32));
1657         if (ret) {
1658                 printf("%s: Cannot read rockchip,sdram-params %d\n",
1659                        __func__, ret);
1660                 return ret;
1661         }
1662         ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
1663         if (ret)
1664                 printf("%s: regmap failed %d\n", __func__, ret);
1665
1666 #endif
1667         return 0;
1668 }
1669
1670 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1671 static int conv_of_platdata(struct udevice *dev)
1672 {
1673         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1674         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1675         int ret;
1676
1677         ret = regmap_init_mem_platdata(dev, dtplat->reg,
1678                                        ARRAY_SIZE(dtplat->reg) / 2,
1679                                        &plat->map);
1680         if (ret)
1681                 return ret;
1682
1683         return 0;
1684 }
1685 #endif
1686
1687 static int rk3399_dmc_init(struct udevice *dev)
1688 {
1689         struct dram_info *priv = dev_get_priv(dev);
1690         struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
1691         int ret;
1692 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
1693         struct rk3399_sdram_params *params = &plat->sdram_params;
1694 #else
1695         struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
1696         struct rk3399_sdram_params *params =
1697                                         (void *)dtplat->rockchip_sdram_params;
1698
1699         ret = conv_of_platdata(dev);
1700         if (ret)
1701                 return ret;
1702 #endif
1703
1704         priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
1705         priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1706         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1707         priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
1708         priv->pmucru = rockchip_get_pmucru();
1709         priv->cru = rockchip_get_cru();
1710         priv->chan[0].pctl = regmap_get_range(plat->map, 0);
1711         priv->chan[0].pi = regmap_get_range(plat->map, 1);
1712         priv->chan[0].publ = regmap_get_range(plat->map, 2);
1713         priv->chan[0].msch = regmap_get_range(plat->map, 3);
1714         priv->chan[1].pctl = regmap_get_range(plat->map, 4);
1715         priv->chan[1].pi = regmap_get_range(plat->map, 5);
1716         priv->chan[1].publ = regmap_get_range(plat->map, 6);
1717         priv->chan[1].msch = regmap_get_range(plat->map, 7);
1718
1719         debug("con reg %p %p %p %p %p %p %p %p\n",
1720               priv->chan[0].pctl, priv->chan[0].pi,
1721               priv->chan[0].publ, priv->chan[0].msch,
1722               priv->chan[1].pctl, priv->chan[1].pi,
1723               priv->chan[1].publ, priv->chan[1].msch);
1724         debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
1725               priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
1726
1727 #if CONFIG_IS_ENABLED(OF_PLATDATA)
1728         ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
1729 #else
1730         ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
1731 #endif
1732         if (ret) {
1733                 printf("%s clk get failed %d\n", __func__, ret);
1734                 return ret;
1735         }
1736
1737         ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
1738         if (ret < 0) {
1739                 printf("%s clk set failed %d\n", __func__, ret);
1740                 return ret;
1741         }
1742
1743         ret = sdram_init(priv, params);
1744         if (ret < 0) {
1745                 printf("%s DRAM init failed %d\n", __func__, ret);
1746                 return ret;
1747         }
1748
1749         return 0;
1750 }
1751 #endif
1752
1753 static int rk3399_dmc_probe(struct udevice *dev)
1754 {
1755 #if defined(CONFIG_TPL_BUILD) || \
1756         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1757         if (rk3399_dmc_init(dev))
1758                 return 0;
1759 #else
1760         struct dram_info *priv = dev_get_priv(dev);
1761
1762         priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
1763         debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
1764         priv->info.base = CONFIG_SYS_SDRAM_BASE;
1765         priv->info.size =
1766                 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
1767 #endif
1768         return 0;
1769 }
1770
1771 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
1772 {
1773         struct dram_info *priv = dev_get_priv(dev);
1774
1775         *info = priv->info;
1776
1777         return 0;
1778 }
1779
1780 static struct ram_ops rk3399_dmc_ops = {
1781         .get_info = rk3399_dmc_get_info,
1782 };
1783
1784 static const struct udevice_id rk3399_dmc_ids[] = {
1785         { .compatible = "rockchip,rk3399-dmc" },
1786         { }
1787 };
1788
1789 U_BOOT_DRIVER(dmc_rk3399) = {
1790         .name = "rockchip_rk3399_dmc",
1791         .id = UCLASS_RAM,
1792         .of_match = rk3399_dmc_ids,
1793         .ops = &rk3399_dmc_ops,
1794 #if defined(CONFIG_TPL_BUILD) || \
1795         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1796         .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
1797 #endif
1798         .probe = rk3399_dmc_probe,
1799         .priv_auto_alloc_size = sizeof(struct dram_info),
1800 #if defined(CONFIG_TPL_BUILD) || \
1801         (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
1802         .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
1803 #endif
1804 };