1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * (C) Copyright 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
6 * Adapted from the very similar rk3288 ddr init.
12 #include <dt-structs.h>
19 #include <asm/arch-rockchip/clock.h>
20 #include <asm/arch-rockchip/cru_rk3188.h>
21 #include <asm/arch-rockchip/ddr_rk3188.h>
22 #include <asm/arch-rockchip/grf_rk3188.h>
23 #include <asm/arch-rockchip/pmu_rk3188.h>
24 #include <asm/arch-rockchip/sdram.h>
25 #include <asm/arch-rockchip/sdram_rk3288.h>
26 #include <linux/err.h>
29 struct rk3288_ddr_pctl *pctl;
30 struct rk3288_ddr_publ *publ;
31 struct rk3188_msch *msch;
35 struct chan_info chan[1];
38 struct rk3188_cru *cru;
39 struct rk3188_grf *grf;
40 struct rk3188_sgrf *sgrf;
41 struct rk3188_pmu *pmu;
44 struct rk3188_sdram_params {
45 #if CONFIG_IS_ENABLED(OF_PLATDATA)
46 struct dtd_rockchip_rk3188_dmc of_plat;
48 struct rk3288_sdram_channel ch[2];
49 struct rk3288_sdram_pctl_timing pctl_timing;
50 struct rk3288_sdram_phy_timing phy_timing;
51 struct rk3288_base_params base;
56 const int ddrconf_table[] = {
59 * [1:0] col(9+n), assume bw=2
63 ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
64 ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
65 ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT),
66 ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
67 ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
68 ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT),
69 ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
70 ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT),
80 #define TEST_PATTEN 0x5aa5f00f
81 #define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4)
82 #define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4)
84 #ifdef CONFIG_SPL_BUILD
85 static void copy_to_reg(u32 *dest, const u32 *src, u32 n)
89 for (i = 0; i < n / sizeof(u32); i++) {
96 static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy)
98 u32 phy_ctl_srstn_shift = 13;
99 u32 ctl_psrstn_shift = 11;
100 u32 ctl_srstn_shift = 10;
101 u32 phy_psrstn_shift = 9;
102 u32 phy_srstn_shift = 8;
104 rk_clrsetreg(&cru->cru_softrst_con[5],
105 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift |
106 1 << ctl_srstn_shift | 1 << phy_psrstn_shift |
107 1 << phy_srstn_shift,
108 phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift |
109 ctl << ctl_srstn_shift | phy << phy_psrstn_shift |
110 phy << phy_srstn_shift);
113 static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n)
115 u32 phy_ctl_srstn_shift = 13;
117 rk_clrsetreg(&cru->cru_softrst_con[5],
118 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift);
121 static void phy_pctrl_reset(struct rk3188_cru *cru,
122 struct rk3288_ddr_publ *publ,
127 ddr_reset(cru, channel, 1, 1);
129 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
130 for (i = 0; i < 4; i++)
131 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
134 setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST);
135 for (i = 0; i < 4; i++)
136 setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST);
139 ddr_reset(cru, channel, 1, 0);
141 ddr_reset(cru, channel, 0, 0);
145 static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ,
150 if (freq <= 250000000) {
151 if (freq <= 150000000)
152 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
154 setbits_le32(&publ->dllgcr, SBIAS_BYPASS);
155 setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
156 for (i = 0; i < 4; i++)
157 setbits_le32(&publ->datx8[i].dxdllcr,
160 setbits_le32(&publ->pir, PIR_DLLBYP);
162 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS);
163 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS);
164 for (i = 0; i < 4; i++) {
165 clrbits_le32(&publ->datx8[i].dxdllcr,
169 clrbits_le32(&publ->pir, PIR_DLLBYP);
173 static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype)
175 writel(DFI_INIT_START, &pctl->dfistcfg0);
176 writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN,
178 writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2);
179 writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN,
182 writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay);
183 writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata);
184 writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat);
185 writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis);
186 writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken);
187 writel(1, &pctl->dfitphyupdtype0);
189 /* cs0 and cs1 write odt enable */
190 writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL),
192 /* odt write length */
193 writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1);
194 /* phyupd and ctrlupd disabled */
195 writel(0, &pctl->dfiupdcfg);
198 static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable)
203 val = 1 << DDR_16BIT_EN_SHIFT;
205 rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val);
208 static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel,
213 mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT;
214 val = ddr3_mode << MSCH4_MAINDDR3_SHIFT;
215 rk_clrsetreg(&grf->soc_con2, mask, val);
218 static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable)
222 mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT;
223 val = enable << RANK_TO_ROW15_EN_SHIFT;
224 rk_clrsetreg(&grf->soc_con2, mask, val);
227 static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl,
228 struct rk3188_sdram_params *sdram_params,
229 struct rk3188_grf *grf)
231 copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u,
232 sizeof(sdram_params->pctl_timing));
233 switch (sdram_params->base.dramtype) {
235 if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) {
236 writel(sdram_params->pctl_timing.tcl - 3,
237 &pctl->dfitrddataen);
239 writel(sdram_params->pctl_timing.tcl - 2,
240 &pctl->dfitrddataen);
242 writel(sdram_params->pctl_timing.tcwl - 1,
243 &pctl->dfitphywrlat);
244 writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN |
245 DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW |
246 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT,
248 ddr_set_ddr3_mode(grf, channel, true);
249 ddr_set_enable(grf, channel, true);
253 setbits_le32(&pctl->scfg, 1);
256 static void phy_cfg(const struct chan_info *chan, int channel,
257 struct rk3188_sdram_params *sdram_params)
259 struct rk3288_ddr_publ *publ = chan->publ;
260 struct rk3188_msch *msch = chan->msch;
261 uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000;
265 dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000);
267 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0,
268 sizeof(sdram_params->phy_timing));
269 writel(sdram_params->base.noc_timing, &msch->ddrtiming);
270 writel(0x3f, &msch->readlatency);
271 writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT |
272 DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT |
273 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]);
274 writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT |
275 DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT,
277 writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT |
278 DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT,
281 switch (sdram_params->base.dramtype) {
283 clrbits_le32(&publ->pgcr, 0x1f);
284 clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT,
285 DDRMD_DDR3 << DDRMD_SHIFT);
288 if (sdram_params->base.odt) {
289 /*dynamic RTT enable */
290 for (i = 0; i < 4; i++)
291 setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
293 /*dynamic RTT disable */
294 for (i = 0; i < 4; i++)
295 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT);
299 static void phy_init(struct rk3288_ddr_publ *publ)
301 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST
302 | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR);
304 while ((readl(&publ->pgsr) &
305 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
306 (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
310 static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank,
313 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd);
315 while (readl(&pctl->mcmd) & START_CMD)
319 static inline void send_command_op(struct rk3288_ddr_pctl *pctl,
320 u32 rank, u32 cmd, u32 ma, u32 op)
322 send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT |
323 (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT);
326 static void memory_init(struct rk3288_ddr_publ *publ,
329 setbits_le32(&publ->pir,
330 (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP
331 | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC
332 | (dramtype == DDR3 ? PIR_DRAMRST : 0)));
334 while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE))
335 != (PGSR_IDONE | PGSR_DLDONE))
339 static void move_to_config_state(struct rk3288_ddr_publ *publ,
340 struct rk3288_ddr_pctl *pctl)
345 state = readl(&pctl->stat) & PCTL_STAT_MSK;
349 writel(WAKEUP_STATE, &pctl->sctl);
350 while ((readl(&pctl->stat) & PCTL_STAT_MSK)
354 while ((readl(&publ->pgsr) & PGSR_DLDONE)
358 * if at low power state,need wakeup first,
359 * and then enter the config, so
365 writel(CFG_STATE, &pctl->sctl);
366 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
377 static void set_bandwidth_ratio(const struct chan_info *chan, int channel,
378 u32 n, struct rk3188_grf *grf)
380 struct rk3288_ddr_pctl *pctl = chan->pctl;
381 struct rk3288_ddr_publ *publ = chan->publ;
382 struct rk3188_msch *msch = chan->msch;
385 setbits_le32(&pctl->ppcfg, 1);
386 ddr_set_enable(grf, channel, 1);
387 setbits_le32(&msch->ddrtiming, 1 << 31);
388 /* Data Byte disable*/
389 clrbits_le32(&publ->datx8[2].dxgcr, 1);
390 clrbits_le32(&publ->datx8[3].dxgcr, 1);
392 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
393 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
395 clrbits_le32(&pctl->ppcfg, 1);
396 ddr_set_enable(grf, channel, 0);
397 clrbits_le32(&msch->ddrtiming, 1 << 31);
398 /* Data Byte enable*/
399 setbits_le32(&publ->datx8[2].dxgcr, 1);
400 setbits_le32(&publ->datx8[3].dxgcr, 1);
403 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS);
404 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS);
406 clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
407 clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
409 setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST);
410 setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST);
412 setbits_le32(&pctl->dfistcfg0, 1 << 2);
415 static int data_training(const struct chan_info *chan, int channel,
416 struct rk3188_sdram_params *sdram_params)
422 u32 step[2] = { PIR_QSTRN, PIR_RVTRN };
423 struct rk3288_ddr_publ *publ = chan->publ;
424 struct rk3288_ddr_pctl *pctl = chan->pctl;
426 /* disable auto refresh */
427 writel(0, &pctl->trefi);
429 if (sdram_params->base.dramtype != LPDDR3)
430 setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
431 rank = sdram_params->ch[channel].rank | 1;
432 for (j = 0; j < ARRAY_SIZE(step); j++) {
434 * trigger QSTRN and RVTRN
435 * clear DTDONE status
437 setbits_le32(&publ->pir, PIR_CLRSR);
440 setbits_le32(&publ->pir,
441 PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP |
444 /* wait echo byte DTDONE */
445 while ((readl(&publ->datx8[0].dxgsr[0]) & rank)
448 while ((readl(&publ->datx8[1].dxgsr[0]) & rank)
451 if (!(readl(&pctl->ppcfg) & 1)) {
452 while ((readl(&publ->datx8[2].dxgsr[0])
455 while ((readl(&publ->datx8[3].dxgsr[0])
459 if (readl(&publ->pgsr) &
460 (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) {
465 /* send some auto refresh to complement the lost while DTT */
466 for (i = 0; i < (rank > 1 ? 8 : 4); i++)
467 send_command(pctl, rank, REF_CMD, 0);
469 if (sdram_params->base.dramtype != LPDDR3)
470 clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT);
472 /* resume auto refresh */
473 writel(sdram_params->pctl_timing.trefi, &pctl->trefi);
478 static void move_to_access_state(const struct chan_info *chan)
480 struct rk3288_ddr_publ *publ = chan->publ;
481 struct rk3288_ddr_pctl *pctl = chan->pctl;
485 state = readl(&pctl->stat) & PCTL_STAT_MSK;
489 if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) &
493 writel(WAKEUP_STATE, &pctl->sctl);
494 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS)
497 while ((readl(&publ->pgsr) & PGSR_DLDONE)
502 writel(CFG_STATE, &pctl->sctl);
503 while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG)
507 writel(GO_STATE, &pctl->sctl);
508 while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG)
519 static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum,
520 struct rk3188_sdram_params *sdram_params)
522 struct rk3288_ddr_publ *publ = chan->publ;
524 if (sdram_params->ch[chnum].bk == 3)
525 clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT,
528 clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT);
530 writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf);
533 static void dram_all_config(const struct dram_info *dram,
534 struct rk3188_sdram_params *sdram_params)
539 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
540 sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
541 for (chan = 0; chan < sdram_params->num_channels; chan++) {
542 const struct rk3288_sdram_channel *info =
543 &sdram_params->ch[chan];
545 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan);
546 sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan);
547 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan);
548 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan);
549 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan);
550 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan);
551 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan);
552 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan);
553 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan);
555 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params);
557 if (sdram_params->ch[0].rank == 2)
558 ddr_rank_2_row15en(dram->grf, 0);
560 ddr_rank_2_row15en(dram->grf, 1);
562 writel(sys_reg, &dram->pmu->sys_reg[2]);
565 static int sdram_rank_bw_detect(struct dram_info *dram, int channel,
566 struct rk3188_sdram_params *sdram_params)
569 int need_trainig = 0;
570 const struct chan_info *chan = &dram->chan[channel];
571 struct rk3288_ddr_publ *publ = chan->publ;
573 ddr_rank_2_row15en(dram->grf, 0);
575 if (data_training(chan, channel, sdram_params) < 0) {
576 printf("first data training fail!\n");
577 reg = readl(&publ->datx8[0].dxgsr[0]);
578 /* Check the result for rank 0 */
579 if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) {
580 printf("data training fail!\n");
584 /* Check the result for rank 1 */
585 if (reg & DQS_GATE_TRAINING_ERROR_RANK1) {
586 sdram_params->ch[channel].rank = 1;
587 clrsetbits_le32(&publ->pgcr, 0xF << 18,
588 sdram_params->ch[channel].rank << 18);
591 reg = readl(&publ->datx8[2].dxgsr[0]);
592 if (reg & (1 << 4)) {
593 sdram_params->ch[channel].bw = 1;
594 set_bandwidth_ratio(chan, channel,
595 sdram_params->ch[channel].bw,
600 /* Assume the Die bit width are the same with the chip bit width */
601 sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw;
604 (data_training(chan, channel, sdram_params) < 0)) {
605 if (sdram_params->base.dramtype == LPDDR3) {
606 ddr_phy_ctl_reset(dram->cru, channel, 1);
608 ddr_phy_ctl_reset(dram->cru, channel, 0);
611 printf("2nd data training failed!");
619 * Detect ram columns and rows.
620 * @dram: dram info struct
621 * @channel: channel number to handle
622 * @sdram_params: sdram parameters, function will fill in col and row values
624 * Returns 0 or negative on error.
626 static int sdram_col_row_detect(struct dram_info *dram, int channel,
627 struct rk3188_sdram_params *sdram_params)
631 const struct chan_info *chan = &dram->chan[channel];
632 struct rk3288_ddr_pctl *pctl = chan->pctl;
633 struct rk3288_ddr_publ *publ = chan->publ;
637 for (col = 11; col >= 9; col--) {
638 writel(0, CONFIG_SYS_SDRAM_BASE);
639 addr = CONFIG_SYS_SDRAM_BASE +
640 (1 << (col + sdram_params->ch[channel].bw - 1));
641 writel(TEST_PATTEN, addr);
642 if ((readl(addr) == TEST_PATTEN) &&
643 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
647 printf("Col detect error\n");
651 sdram_params->ch[channel].col = col;
654 ddr_rank_2_row15en(dram->grf, 1);
655 move_to_config_state(publ, pctl);
656 writel(1, &chan->msch->ddrconf);
657 move_to_access_state(chan);
658 /* Detect row, max 15,min13 in rk3188*/
659 for (row = 16; row >= 13; row--) {
660 writel(0, CONFIG_SYS_SDRAM_BASE);
661 addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
662 writel(TEST_PATTEN, addr);
663 if ((readl(addr) == TEST_PATTEN) &&
664 (readl(CONFIG_SYS_SDRAM_BASE) == 0))
668 printf("Row detect error\n");
671 sdram_params->ch[channel].cs1_row = row;
672 sdram_params->ch[channel].row_3_4 = 0;
673 debug("chn %d col %d, row %d\n", channel, col, row);
674 sdram_params->ch[channel].cs0_row = row;
681 static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params)
683 int i, tmp, size, row, ret = 0;
685 row = sdram_params->ch[0].cs0_row;
687 * RK3188 share the rank and row bit15, we use same ddr config for 15bit
692 tmp = sdram_params->ch[0].col - 9;
693 tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1;
694 tmp |= ((row - 13) << 4);
695 size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]);
696 for (i = 0; i < size; i++)
697 if (tmp == ddrconf_table[i])
700 printf("niu config not found\n");
703 debug("niu config %d\n", i);
704 sdram_params->base.ddrconfig = i;
710 static int sdram_init(struct dram_info *dram,
711 struct rk3188_sdram_params *sdram_params)
717 if ((sdram_params->base.dramtype == DDR3 &&
718 sdram_params->base.ddr_freq > 800000000)) {
719 printf("SDRAM frequency is too high!");
723 ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq);
725 printf("Could not set DDR clock\n");
729 for (channel = 0; channel < 1; channel++) {
730 const struct chan_info *chan = &dram->chan[channel];
731 struct rk3288_ddr_pctl *pctl = chan->pctl;
732 struct rk3288_ddr_publ *publ = chan->publ;
734 phy_pctrl_reset(dram->cru, publ, channel);
735 phy_dll_bypass_set(publ, sdram_params->base.ddr_freq);
737 dfi_cfg(pctl, sdram_params->base.dramtype);
739 pctl_cfg(channel, pctl, sdram_params, dram->grf);
741 phy_cfg(chan, channel, sdram_params);
745 writel(POWER_UP_START, &pctl->powctl);
746 while (!(readl(&pctl->powstat) & POWER_UP_DONE))
749 memory_init(publ, sdram_params->base.dramtype);
750 move_to_config_state(publ, pctl);
752 /* Using 32bit bus width for detect */
753 sdram_params->ch[channel].bw = 2;
754 set_bandwidth_ratio(chan, channel,
755 sdram_params->ch[channel].bw, dram->grf);
757 * set cs, using n=3 for detect
762 sdram_params->ch[channel].rank = 2,
763 clrsetbits_le32(&publ->pgcr, 0xF << 18,
764 (sdram_params->ch[channel].rank | 1) << 18);
766 /* DS=40ohm,ODT=155ohm */
767 zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
768 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
769 0x19 << PD_OUTPUT_SHIFT;
770 writel(zqcr, &publ->zq1cr[0]);
771 writel(zqcr, &publ->zq0cr[0]);
773 /* Detect the rank and bit-width with data-training */
774 writel(1, &chan->msch->ddrconf);
775 sdram_rank_bw_detect(dram, channel, sdram_params);
777 if (sdram_params->base.dramtype == LPDDR3) {
779 writel(0, &pctl->mrrcfg0);
780 for (i = 0; i < 17; i++)
781 send_command_op(pctl, 1, MRR_CMD, i, 0);
783 writel(4, &chan->msch->ddrconf);
784 move_to_access_state(chan);
785 /* DDR3 and LPDDR3 are always 8 bank, no need detect */
786 sdram_params->ch[channel].bk = 3;
787 /* Detect Col and Row number*/
788 ret = sdram_col_row_detect(dram, channel, sdram_params);
792 /* Find NIU DDR configuration */
793 ret = sdram_get_niu_config(sdram_params);
797 dram_all_config(dram, sdram_params);
798 debug("%s done\n", __func__);
802 printf("DRAM init failed!\n");
806 static int setup_sdram(struct udevice *dev)
808 struct dram_info *priv = dev_get_priv(dev);
809 struct rk3188_sdram_params *params = dev_get_platdata(dev);
811 return sdram_init(priv, params);
814 static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
816 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
817 struct rk3188_sdram_params *params = dev_get_platdata(dev);
820 /* rk3188 supports only one-channel */
821 params->num_channels = 1;
822 ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
823 (u32 *)¶ms->pctl_timing,
824 sizeof(params->pctl_timing) / sizeof(u32));
826 printf("%s: Cannot read rockchip,pctl-timing\n", __func__);
829 ret = dev_read_u32_array(dev, "rockchip,phy-timing",
830 (u32 *)¶ms->phy_timing,
831 sizeof(params->phy_timing) / sizeof(u32));
833 printf("%s: Cannot read rockchip,phy-timing\n", __func__);
836 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
837 (u32 *)¶ms->base,
838 sizeof(params->base) / sizeof(u32));
840 printf("%s: Cannot read rockchip,sdram-params\n", __func__);
843 ret = regmap_init_mem(dev_ofnode(dev), ¶ms->map);
850 #endif /* CONFIG_SPL_BUILD */
852 #if CONFIG_IS_ENABLED(OF_PLATDATA)
853 static int conv_of_platdata(struct udevice *dev)
855 struct rk3188_sdram_params *plat = dev_get_platdata(dev);
856 struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
859 memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing,
860 sizeof(plat->pctl_timing));
861 memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing,
862 sizeof(plat->phy_timing));
863 memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
864 /* rk3188 supports dual-channel, set default channel num to 2 */
865 plat->num_channels = 1;
866 ret = regmap_init_mem_platdata(dev, of_plat->reg,
867 ARRAY_SIZE(of_plat->reg) / 2,
876 static int rk3188_dmc_probe(struct udevice *dev)
878 #ifdef CONFIG_SPL_BUILD
879 struct rk3188_sdram_params *plat = dev_get_platdata(dev);
881 struct udevice *dev_clk;
884 struct dram_info *priv = dev_get_priv(dev);
886 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
888 #ifdef CONFIG_SPL_BUILD
889 #if CONFIG_IS_ENABLED(OF_PLATDATA)
890 ret = conv_of_platdata(dev);
894 map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC);
897 priv->chan[0].msch = regmap_get_range(map, 0);
899 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
901 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
902 priv->chan[0].publ = regmap_get_range(plat->map, 1);
904 ret = rockchip_get_clk(&dev_clk);
907 priv->ddr_clk.id = CLK_DDR;
908 ret = clk_request(dev_clk, &priv->ddr_clk);
912 priv->cru = rockchip_get_cru();
913 if (IS_ERR(priv->cru))
914 return PTR_ERR(priv->cru);
915 ret = setup_sdram(dev);
919 priv->info.base = CONFIG_SYS_SDRAM_BASE;
920 priv->info.size = rockchip_sdram_size(
921 (phys_addr_t)&priv->pmu->sys_reg[2]);
927 static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info)
929 struct dram_info *priv = dev_get_priv(dev);
936 static struct ram_ops rk3188_dmc_ops = {
937 .get_info = rk3188_dmc_get_info,
940 static const struct udevice_id rk3188_dmc_ids[] = {
941 { .compatible = "rockchip,rk3188-dmc" },
945 U_BOOT_DRIVER(dmc_rk3188) = {
946 .name = "rockchip_rk3188_dmc",
948 .of_match = rk3188_dmc_ids,
949 .ops = &rk3188_dmc_ops,
950 #ifdef CONFIG_SPL_BUILD
951 .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata,
953 .probe = rk3188_dmc_probe,
954 .priv_auto_alloc_size = sizeof(struct dram_info),
955 #ifdef CONFIG_SPL_BUILD
956 .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params),