1 // SPDX-License-Identifier: GPL-2.0
3 * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
9 #include <asm/arch-rockchip/sdram.h>
10 #include <asm/arch-rockchip/sdram_pctl_px30.h>
16 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num)
18 writel((rank << 4) | (1 << 0), pctl_base + DDR_PCTL2_MRCTRL0);
19 writel((mr_num << 8), pctl_base + DDR_PCTL2_MRCTRL1);
20 setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
21 while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
23 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
30 * note: be careful of keep mr original val
32 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
35 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
37 if (dramtype == DDR3 || dramtype == DDR4) {
38 writel((mr_num << 12) | (rank << 4) | (0 << 0),
39 pctl_base + DDR_PCTL2_MRCTRL0);
40 writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
42 writel((rank << 4) | (0 << 0),
43 pctl_base + DDR_PCTL2_MRCTRL0);
44 writel((mr_num << 8) | (arg & 0xff),
45 pctl_base + DDR_PCTL2_MRCTRL1);
48 setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
49 while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
51 while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
58 * rank : 1:cs0, 2:cs1, 3:cs0&cs1
59 * vrefrate: 4500: 45%,
61 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
67 if (dramtype != DDR4 || vrefrate < 4500 ||
71 tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
72 tccd_l = (tccd_l - 4) << 10;
74 if (vrefrate > 7500) {
76 value = ((vrefrate - 6000) / 65) | tccd_l;
79 value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
82 dis_auto_zq = pctl_dis_zqcs_aref(pctl_base);
84 /* enable vrefdq calibratin */
85 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);
86 udelay(1);/* tvrefdqe */
87 /* write vrefdq value */
88 pctl_write_mr(pctl_base, rank, 6, value | (1 << 7), dramtype);
89 udelay(1);/* tvref_time */
90 pctl_write_mr(pctl_base, rank, 6, value | (0 << 7), dramtype);
91 udelay(1);/* tvrefdqx */
93 pctl_rest_zqcs_aref(pctl_base, dis_auto_zq);
98 static int upctl2_update_ref_reg(void __iomem *pctl_base)
102 ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
103 writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
108 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base)
113 if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
116 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
119 /* disable auto refresh */
120 setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
122 upctl2_update_ref_reg(pctl_base);
127 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq)
131 clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
133 /* restore auto refresh */
134 clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
136 upctl2_update_ref_reg(pctl_base);
139 u32 pctl_remodify_sdram_params(struct ddr_pctl_regs *pctl_regs,
140 struct sdram_cap_info *cap_info,
143 u32 tmp = 0, tmp_adr = 0, i;
145 for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) {
146 if (pctl_regs->pctl[i][0] == 0) {
147 tmp = pctl_regs->pctl[i][1];/* MSTR */
152 tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
154 switch (cap_info->dbw) {
168 * If DDR3 or DDR4 MSTR.active_ranks=1,
169 * it will gate memory clock when enter power down.
170 * Force set active_ranks to 3 to workaround it.
172 if (cap_info->rank == 2 || dram_type == DDR3 ||
178 tmp |= (2 - cap_info->bw) << 12;
180 pctl_regs->pctl[tmp_adr][1] = tmp;
185 int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
186 u32 sr_idle, u32 pd_idle)
190 for (i = 0; pctl_regs->pctl[i][0] != 0xFFFFFFFF; i++) {
191 writel(pctl_regs->pctl[i][1],
192 pctl_base + pctl_regs->pctl[i][0]);
194 clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
196 ((sr_idle & 0xff) << 16) | (pd_idle & 0x1f));
198 clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
202 setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);