1 // SPDX-License-Identifier: GPL-2.0+
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
11 #include <dt-bindings/memory/mpc83xx-sdram.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 /* Masks for the CS config register */
16 static const u32 CSCONFIG_ENABLE = 0x80000000;
18 static const u32 BANK_BITS_2;
19 static const u32 BANK_BITS_3 = 0x00004000;
21 static const u32 ROW_BITS_12;
22 static const u32 ROW_BITS_13 = 0x00000100;
23 static const u32 ROW_BITS_14 = 0x00000200;
25 static const u32 COL_BITS_8;
26 static const u32 COL_BITS_9 = 0x00000001;
27 static const u32 COL_BITS_10 = 0x00000002;
28 static const u32 COL_BITS_11 = 0x00000003;
30 /* Shifts for the DDR SDRAM Timing Configuration 3 register */
31 static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15);
33 /* Shifts for the DDR SDRAM Timing Configuration 0 register */
34 static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1);
35 static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3);
36 static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5);
37 static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7);
38 static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11);
39 static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15);
40 static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23);
41 static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31);
43 /* Shifts for the DDR SDRAM Timing Configuration 1 register */
44 static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3);
45 static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7);
46 static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11);
47 static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15);
48 static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19);
49 static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23);
50 static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27);
51 static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31);
53 /* Shifts for the DDR SDRAM Timing Configuration 2 register */
54 static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8);
55 static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21);
56 static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3);
57 static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12);
58 static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18);
59 static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25);
60 static const uint TIMING_CFG2_FOUR_ACT_SHIFT;
62 /* Shifts for the DDR SDRAM Control Configuration register */
63 static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1);
64 static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2);
65 static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3);
66 static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7);
67 static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10);
68 static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12);
69 static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14);
70 static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16);
71 static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23);
72 static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27);
73 static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28);
74 static const uint SDRAM_CFG_BI_SHIFT = (31 - 31);
76 /* Shifts for the DDR SDRAM Control Configuration 2 register */
77 static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0);
78 static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2);
79 static const uint SDRAM_CFG2_DQS_CFG = (31 - 5);
80 static const uint SDRAM_CFG2_ODT_CFG = (31 - 10);
81 static const uint SDRAM_CFG2_NUM_PR = (31 - 19);
83 /* Shifts for the DDR SDRAM Mode register */
84 static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15);
85 static const uint SDRAM_MODE_SD_SHIFT = (31 - 31);
87 /* Shifts for the DDR SDRAM Mode 2 register */
88 static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15);
89 static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31);
91 /* Shifts for the DDR SDRAM Interval Configuration register */
92 static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15);
93 static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31);
95 /* Mask for the DDR SDRAM Mode Control register */
96 static const u32 SDRAM_CFG_MEM_EN = 0x80000000;
100 struct udevice *ram_ctrl;
103 /* Current assumption: There is only one RAM controller */
104 ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl);
106 debug("%s: uclass_first_device_err failed: %d\n",
111 /* FIXME(mario.six@gdsys.cc): Set gd->ram_size? */
116 phys_size_t get_effective_memsize(void)
118 if (!IS_ENABLED(CONFIG_VERY_BIG_RAM))
121 /* Limit stack to what we can reasonable map */
122 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
123 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
127 * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers
128 * @total_size: The total size of all RAM modules associated with this RAM
129 * controller in bytes
131 struct mpc83xx_sdram_priv {
136 * mpc83xx_sdram_static_init() - Statically initialize a RAM module.
137 * @node: Device tree node associated with ths module in question
138 * @cs: The chip select to use for this RAM module
139 * @mapaddr: The address where the RAM module should be mapped
140 * @size: The size of the RAM module to be mapped in bytes
142 * Return: 0 if OK, -ve on error
144 static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
146 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
148 u32 msize_log2 = __ilog2(msize);
149 u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits,
151 u32 bank_bits_mask, row_bits_mask, col_bits_mask;
153 /* Configure the DDR local access window */
154 out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000);
155 out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1));
157 out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24);
159 auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0);
160 switch (auto_precharge) {
161 case AUTO_PRECHARGE_ENABLE:
162 case AUTO_PRECHARGE_DISABLE:
165 debug("%s: auto_precharge value %d invalid.\n",
166 ofnode_get_name(node), auto_precharge);
170 odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
171 switch (odt_rd_cfg) {
172 case ODT_RD_ONLY_OTHER_DIMM:
173 if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
174 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
175 debug("%s: odt_rd_cfg value %d invalid.\n",
176 ofnode_get_name(node), odt_rd_cfg);
181 case ODT_RD_ONLY_CURRENT:
182 case ODT_RD_ONLY_OTHER_CS:
183 if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
184 !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
185 !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
186 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
187 debug("%s: odt_rd_cfg value %d invalid.\n",
188 ofnode_get_name(node), odt_rd_cfg);
192 /* Only MPC832x knows this value */
196 debug("%s: odt_rd_cfg value %d invalid.\n",
197 ofnode_get_name(node), odt_rd_cfg);
201 odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
202 switch (odt_wr_cfg) {
203 case ODT_WR_ONLY_OTHER_DIMM:
204 if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
205 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
206 debug("%s: odt_wr_cfg value %d invalid.\n",
207 ofnode_get_name(node), odt_wr_cfg);
212 case ODT_WR_ONLY_CURRENT:
213 case ODT_WR_ONLY_OTHER_CS:
214 if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
215 !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
216 !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
217 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
218 debug("%s: odt_wr_cfg value %d invalid.\n",
219 ofnode_get_name(node), odt_wr_cfg);
223 /* MPC832x only knows this value */
227 debug("%s: odt_wr_cfg value %d invalid.\n",
228 ofnode_get_name(node), odt_wr_cfg);
232 bank_bits = ofnode_read_u32_default(node, "bank_bits", 0);
235 bank_bits_mask = BANK_BITS_2;
238 bank_bits_mask = BANK_BITS_3;
241 debug("%s: bank_bits value %d invalid.\n",
242 ofnode_get_name(node), bank_bits);
246 row_bits = ofnode_read_u32_default(node, "row_bits", 0);
249 row_bits_mask = ROW_BITS_12;
252 row_bits_mask = ROW_BITS_13;
255 row_bits_mask = ROW_BITS_14;
258 debug("%s: row_bits value %d invalid.\n",
259 ofnode_get_name(node), row_bits);
263 col_bits = ofnode_read_u32_default(node, "col_bits", 0);
266 col_bits_mask = COL_BITS_8;
269 col_bits_mask = COL_BITS_9;
272 col_bits_mask = COL_BITS_10;
275 col_bits_mask = COL_BITS_11;
278 debug("%s: col_bits value %d invalid.\n",
279 ofnode_get_name(node), col_bits);
283 /* Write CS config value */
284 out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge |
285 odt_rd_cfg | odt_wr_cfg |
286 bank_bits_mask | row_bits_mask |
292 * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash.
293 * @node: Device tree node associated with ths module in question
294 * @cs: The chip select to use for this RAM module
295 * @mapaddr: The address where the RAM module should be mapped
296 * @size: The size of the RAM module to be mapped in bytes
298 * Return: 0 if OK, -ve on error
300 static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
302 /* TODO(mario.six@gdsys.cc): Implement */
306 static int mpc83xx_sdram_ofdata_to_platdata(struct udevice *dev)
311 static int mpc83xx_sdram_probe(struct udevice *dev)
313 struct mpc83xx_sdram_priv *priv = dev_get_priv(dev);
314 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
317 /* DDR control driver register values */
318 u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr;
320 /* DDR SDRAM Clock Control register values */
322 /* DDR SDRAM Timing Configuration 3 register values */
323 u32 ext_refresh_rec, ext_refresh_rec_mask;
324 /* DDR SDRAM Timing Configuration 0 register values */
325 u32 read_to_write, write_to_read, read_to_read, write_to_write,
326 active_powerdown_exit, precharge_powerdown_exit,
327 odt_powerdown_exit, mode_reg_set_cycle;
329 /* DDR SDRAM Timing Configuration 1 register values */
330 u32 precharge_to_activate, activate_to_precharge,
331 activate_to_readwrite, mcas_latency, refresh_recovery,
332 last_data_to_precharge, activate_to_activate,
333 last_write_data_to_read;
335 /* DDR SDRAM Timing Configuration 2 register values */
336 u32 additive_latency, mcas_to_preamble_override, write_latency,
337 read_to_precharge, write_cmd_to_write_data,
338 minimum_cke_pulse_width, four_activates_window;
340 /* DDR SDRAM Control Configuration register values */
341 u32 self_refresh, ecc, registered_dram, sdram_type,
342 dynamic_power_management, databus_width, nc_auto_precharge,
343 timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength,
344 bypass_initialization;
346 /* DDR SDRAM Control Configuration 2 register values */
347 u32 force_self_refresh, dll_reset, dqs_config, odt_config,
350 /* DDR SDRAM Mode Configuration register values */
353 /* DDR SDRAM Mode Configuration 2 register values */
354 u32 esdmode2, esdmode3;
356 /* DDR SDRAM Interval Configuration register values */
357 u32 refresh_interval, precharge_interval;
360 priv->total_size = 0;
362 /* Disable both banks initially (might be re-enabled in loop below) */
363 out_be32(&im->ddr.cs_config[0], 0);
364 out_be32(&im->ddr.cs_config[1], 0);
366 dso = dev_read_u32_default(dev, "driver_software_override", 0);
368 debug("%s: driver_software_override value %d invalid.\n",
373 pz_override = dev_read_u32_default(dev, "p_impedance_override", 0);
375 switch (pz_override) {
376 case DSO_P_IMPEDANCE_HIGHEST_Z:
377 case DSO_P_IMPEDANCE_MUCH_HIGHER_Z:
378 case DSO_P_IMPEDANCE_HIGHER_Z:
379 case DSO_P_IMPEDANCE_NOMINAL:
380 case DSO_P_IMPEDANCE_LOWER_Z:
383 debug("%s: p_impedance_override value %d invalid.\n",
384 dev->name, pz_override);
388 nz_override = dev_read_u32_default(dev, "n_impedance_override", 0);
390 switch (nz_override) {
391 case DSO_N_IMPEDANCE_HIGHEST_Z:
392 case DSO_N_IMPEDANCE_MUCH_HIGHER_Z:
393 case DSO_N_IMPEDANCE_HIGHER_Z:
394 case DSO_N_IMPEDANCE_NOMINAL:
395 case DSO_N_IMPEDANCE_LOWER_Z:
398 debug("%s: n_impedance_override value %d invalid.\n",
399 dev->name, nz_override);
403 odt_term = dev_read_u32_default(dev, "odt_termination_value", 0);
405 debug("%s: odt_termination_value value %d invalid.\n",
406 dev->name, odt_term);
410 ddr_type = dev_read_u32_default(dev, "ddr_type", 0);
412 debug("%s: ddr_type value %d invalid.\n",
413 dev->name, ddr_type);
417 mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0);
419 debug("%s: mvref_sel value %d invalid.\n",
420 dev->name, mvref_sel);
424 m_odr = dev_read_u32_default(dev, "m_odr", 0);
426 debug("%s: m_odr value %d invalid.\n",
431 ddrcdr = dso << (31 - 1) |
432 pz_override << (31 - 5) |
433 nz_override << (31 - 9) |
434 odt_term << (31 - 12) |
435 ddr_type << (31 - 13) |
436 mvref_sel << (31 - 29) |
437 m_odr << (31 - 30) | 1;
439 /* Configure the DDR control driver register */
440 out_be32(&im->sysconf.ddrcdr, ddrcdr);
442 dev_for_each_subnode(subnode, dev) {
446 /* CS, map address, size -> three values */
447 ofnode_read_u32_array(subnode, "reg", val, 3);
454 debug("%s: chip select value %d invalid.\n",
459 /* TODO(mario.six@gdsys.cc): Sanity check for size. */
461 if (ofnode_read_bool(subnode, "read-spd"))
462 ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size);
464 ret = mpc83xx_sdram_static_init(subnode, cs, addr,
467 debug("%s: RAM init failed.\n", dev->name);
473 * TODO(mario.six@gdsys.cc): This should only occur for static
477 clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0);
478 switch (clock_adjust) {
479 case CLOCK_ADJUST_025:
480 case CLOCK_ADJUST_05:
481 case CLOCK_ADJUST_075:
485 debug("%s: clock_adjust value %d invalid.\n",
486 dev->name, clock_adjust);
490 /* Configure the DDR SDRAM Clock Control register */
491 out_be32(&im->ddr.sdram_clk_cntl, clock_adjust);
493 ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0);
494 switch (ext_refresh_rec) {
496 ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT;
499 ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT;
502 ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT;
505 ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT;
508 ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT;
511 ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT;
514 ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT;
517 ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT;
520 debug("%s: ext_refresh_rec value %d invalid.\n",
521 dev->name, ext_refresh_rec);
525 /* Configure the DDR SDRAM Timing Configuration 3 register */
526 out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask);
528 read_to_write = dev_read_u32_default(dev, "read_to_write", 0);
529 if (read_to_write > 3) {
530 debug("%s: read_to_write value %d invalid.\n",
531 dev->name, read_to_write);
535 write_to_read = dev_read_u32_default(dev, "write_to_read", 0);
536 if (write_to_read > 3) {
537 debug("%s: write_to_read value %d invalid.\n",
538 dev->name, write_to_read);
542 read_to_read = dev_read_u32_default(dev, "read_to_read", 0);
543 if (read_to_read > 3) {
544 debug("%s: read_to_read value %d invalid.\n",
545 dev->name, read_to_read);
549 write_to_write = dev_read_u32_default(dev, "write_to_write", 0);
550 if (write_to_write > 3) {
551 debug("%s: write_to_write value %d invalid.\n",
552 dev->name, write_to_write);
556 active_powerdown_exit =
557 dev_read_u32_default(dev, "active_powerdown_exit", 0);
558 if (active_powerdown_exit > 7) {
559 debug("%s: active_powerdown_exit value %d invalid.\n",
560 dev->name, active_powerdown_exit);
564 precharge_powerdown_exit =
565 dev_read_u32_default(dev, "precharge_powerdown_exit", 0);
566 if (precharge_powerdown_exit > 7) {
567 debug("%s: precharge_powerdown_exit value %d invalid.\n",
568 dev->name, precharge_powerdown_exit);
572 odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0);
573 if (odt_powerdown_exit > 15) {
574 debug("%s: odt_powerdown_exit value %d invalid.\n",
575 dev->name, odt_powerdown_exit);
579 mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0);
580 if (mode_reg_set_cycle > 15) {
581 debug("%s: mode_reg_set_cycle value %d invalid.\n",
582 dev->name, mode_reg_set_cycle);
586 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT |
587 write_to_read << TIMING_CFG0_WRT_SHIFT |
588 read_to_read << TIMING_CFG0_RRT_SHIFT |
589 write_to_write << TIMING_CFG0_WWT_SHIFT |
590 active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT |
591 precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT |
592 odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT |
593 mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT;
595 out_be32(&im->ddr.timing_cfg_0, timing_cfg_0);
597 precharge_to_activate =
598 dev_read_u32_default(dev, "precharge_to_activate", 0);
599 if (precharge_to_activate > 7 || precharge_to_activate == 0) {
600 debug("%s: precharge_to_activate value %d invalid.\n",
601 dev->name, precharge_to_activate);
605 activate_to_precharge =
606 dev_read_u32_default(dev, "activate_to_precharge", 0);
607 if (activate_to_precharge > 19) {
608 debug("%s: activate_to_precharge value %d invalid.\n",
609 dev->name, activate_to_precharge);
613 activate_to_readwrite =
614 dev_read_u32_default(dev, "activate_to_readwrite", 0);
615 if (activate_to_readwrite > 7 || activate_to_readwrite == 0) {
616 debug("%s: activate_to_readwrite value %d invalid.\n",
617 dev->name, activate_to_readwrite);
621 mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0);
622 switch (mcas_latency) {
625 if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) {
626 debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n",
644 debug("%s: mcas_latency value %d invalid.\n",
645 dev->name, mcas_latency);
649 refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0);
650 if (refresh_recovery > 23 || refresh_recovery < 8) {
651 debug("%s: refresh_recovery value %d invalid.\n",
652 dev->name, refresh_recovery);
656 last_data_to_precharge =
657 dev_read_u32_default(dev, "last_data_to_precharge", 0);
658 if (last_data_to_precharge > 7 || last_data_to_precharge == 0) {
659 debug("%s: last_data_to_precharge value %d invalid.\n",
660 dev->name, last_data_to_precharge);
664 activate_to_activate =
665 dev_read_u32_default(dev, "activate_to_activate", 0);
666 if (activate_to_activate > 7 || activate_to_activate == 0) {
667 debug("%s: activate_to_activate value %d invalid.\n",
668 dev->name, activate_to_activate);
672 last_write_data_to_read =
673 dev_read_u32_default(dev, "last_write_data_to_read", 0);
674 if (last_write_data_to_read > 7 || last_write_data_to_read == 0) {
675 debug("%s: last_write_data_to_read value %d invalid.\n",
676 dev->name, last_write_data_to_read);
680 timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT |
681 (activate_to_precharge > 15 ?
682 activate_to_precharge - 16 :
683 activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT |
684 activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT |
685 mcas_latency << TIMING_CFG1_CASLAT_SHIFT |
686 (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT |
687 last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT |
688 activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT |
689 last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT;
691 /* Configure the DDR SDRAM Timing Configuration 1 register */
692 out_be32(&im->ddr.timing_cfg_1, timing_cfg_1);
694 additive_latency = dev_read_u32_default(dev, "additive_latency", 0);
695 if (additive_latency > 5) {
696 debug("%s: additive_latency value %d invalid.\n",
697 dev->name, additive_latency);
701 mcas_to_preamble_override =
702 dev_read_u32_default(dev, "mcas_to_preamble_override", 0);
703 switch (mcas_to_preamble_override) {
704 case READ_LAT_PLUS_1:
706 case READ_LAT_PLUS_1_4:
707 case READ_LAT_PLUS_1_2:
708 case READ_LAT_PLUS_3_4:
709 case READ_LAT_PLUS_5_4:
710 case READ_LAT_PLUS_3_2:
711 case READ_LAT_PLUS_7_4:
712 case READ_LAT_PLUS_2:
713 case READ_LAT_PLUS_9_4:
714 case READ_LAT_PLUS_5_2:
715 case READ_LAT_PLUS_11_4:
716 case READ_LAT_PLUS_3:
717 case READ_LAT_PLUS_13_4:
718 case READ_LAT_PLUS_7_2:
719 case READ_LAT_PLUS_15_4:
720 case READ_LAT_PLUS_4:
721 case READ_LAT_PLUS_17_4:
722 case READ_LAT_PLUS_9_2:
723 case READ_LAT_PLUS_19_4:
726 debug("%s: mcas_to_preamble_override value %d invalid.\n",
727 dev->name, mcas_to_preamble_override);
731 write_latency = dev_read_u32_default(dev, "write_latency", 0);
732 if (write_latency > 7 || write_latency == 0) {
733 debug("%s: write_latency value %d invalid.\n",
734 dev->name, write_latency);
738 read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0);
739 if (read_to_precharge > 4 || read_to_precharge == 0) {
740 debug("%s: read_to_precharge value %d invalid.\n",
741 dev->name, read_to_precharge);
745 write_cmd_to_write_data =
746 dev_read_u32_default(dev, "write_cmd_to_write_data", 0);
747 switch (write_cmd_to_write_data) {
749 case CLOCK_DELAY_1_4:
750 case CLOCK_DELAY_1_2:
751 case CLOCK_DELAY_3_4:
753 case CLOCK_DELAY_5_4:
754 case CLOCK_DELAY_3_2:
757 debug("%s: write_cmd_to_write_data value %d invalid.\n",
758 dev->name, write_cmd_to_write_data);
762 minimum_cke_pulse_width =
763 dev_read_u32_default(dev, "minimum_cke_pulse_width", 0);
764 if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) {
765 debug("%s: minimum_cke_pulse_width value %d invalid.\n",
766 dev->name, minimum_cke_pulse_width);
770 four_activates_window =
771 dev_read_u32_default(dev, "four_activates_window", 0);
772 if (four_activates_window > 20 || four_activates_window == 0) {
773 debug("%s: four_activates_window value %d invalid.\n",
774 dev->name, four_activates_window);
778 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT |
779 mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT |
780 write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT |
781 read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT |
782 write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT |
783 minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT |
784 four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT;
786 out_be32(&im->ddr.timing_cfg_2, timing_cfg_2);
788 self_refresh = dev_read_u32_default(dev, "self_refresh", 0);
789 switch (self_refresh) {
794 debug("%s: self_refresh value %d invalid.\n",
795 dev->name, self_refresh);
799 ecc = dev_read_u32_default(dev, "ecc", 0);
805 debug("%s: ecc value %d invalid.\n", dev->name, ecc);
809 registered_dram = dev_read_u32_default(dev, "registered_dram", 0);
810 switch (registered_dram) {
815 debug("%s: registered_dram value %d invalid.\n",
816 dev->name, registered_dram);
820 sdram_type = dev_read_u32_default(dev, "sdram_type", 0);
821 switch (sdram_type) {
826 debug("%s: sdram_type value %d invalid.\n",
827 dev->name, sdram_type);
831 dynamic_power_management =
832 dev_read_u32_default(dev, "dynamic_power_management", 0);
833 switch (dynamic_power_management) {
834 case DYN_PWR_DISABLE:
838 debug("%s: dynamic_power_management value %d invalid.\n",
839 dev->name, dynamic_power_management);
843 databus_width = dev_read_u32_default(dev, "databus_width", 0);
844 switch (databus_width) {
845 case DATA_BUS_WIDTH_16:
846 case DATA_BUS_WIDTH_32:
849 debug("%s: databus_width value %d invalid.\n",
850 dev->name, databus_width);
854 nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0);
855 switch (nc_auto_precharge) {
860 debug("%s: nc_auto_precharge value %d invalid.\n",
861 dev->name, nc_auto_precharge);
865 timing_2t = dev_read_u32_default(dev, "timing_2t", 0);
871 debug("%s: timing_2t value %d invalid.\n",
872 dev->name, timing_2t);
876 bank_interleaving_ctrl =
877 dev_read_u32_default(dev, "bank_interleaving_ctrl", 0);
878 switch (bank_interleaving_ctrl) {
879 case INTERLEAVE_NONE:
880 case INTERLEAVE_1_AND_2:
883 debug("%s: bank_interleaving_ctrl value %d invalid.\n",
884 dev->name, bank_interleaving_ctrl);
888 precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0);
889 switch (precharge_bit_8) {
890 case PRECHARGE_MA_10:
894 debug("%s: precharge_bit_8 value %d invalid.\n",
895 dev->name, precharge_bit_8);
899 half_strength = dev_read_u32_default(dev, "half_strength", 0);
900 switch (half_strength) {
905 debug("%s: half_strength value %d invalid.\n",
906 dev->name, half_strength);
910 bypass_initialization =
911 dev_read_u32_default(dev, "bypass_initialization", 0);
912 switch (bypass_initialization) {
913 case INITIALIZATION_DONT_BYPASS:
914 case INITIALIZATION_BYPASS:
917 debug("%s: bypass_initialization value %d invalid.\n",
918 dev->name, bypass_initialization);
922 sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT |
923 ecc << SDRAM_CFG_ECC_EN_SHIFT |
924 registered_dram << SDRAM_CFG_RD_EN_SHIFT |
925 sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT |
926 dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT |
927 databus_width << SDRAM_CFG_DBW_SHIFT |
928 nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT |
929 timing_2t << SDRAM_CFG_2T_EN_SHIFT |
930 bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT |
931 precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT |
932 half_strength << SDRAM_CFG_HSE_SHIFT |
933 bypass_initialization << SDRAM_CFG_BI_SHIFT;
935 out_be32(&im->ddr.sdram_cfg, sdram_cfg);
937 force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0);
938 switch (force_self_refresh) {
943 debug("%s: force_self_refresh value %d invalid.\n",
944 dev->name, force_self_refresh);
948 dll_reset = dev_read_u32_default(dev, "dll_reset", 0);
950 case DLL_RESET_ENABLE:
951 case DLL_RESET_DISABLE:
954 debug("%s: dll_reset value %d invalid.\n",
955 dev->name, dll_reset);
959 dqs_config = dev_read_u32_default(dev, "dqs_config", 0);
960 switch (dqs_config) {
964 debug("%s: dqs_config value %d invalid.\n",
965 dev->name, dqs_config);
969 odt_config = dev_read_u32_default(dev, "odt_config", 0);
970 switch (odt_config) {
971 case ODT_ASSERT_NEVER:
972 case ODT_ASSERT_WRITES:
973 case ODT_ASSERT_READS:
974 case ODT_ASSERT_ALWAYS:
977 debug("%s: odt_config value %d invalid.\n",
978 dev->name, odt_config);
982 posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0);
983 if (posted_refreshes > 8 || posted_refreshes == 0) {
984 debug("%s: posted_refreshes value %d invalid.\n",
985 dev->name, posted_refreshes);
989 sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT |
990 dll_reset << SDRAM_CFG2_DLL_RST_DIS |
991 dqs_config << SDRAM_CFG2_DQS_CFG |
992 odt_config << SDRAM_CFG2_ODT_CFG |
993 posted_refreshes << SDRAM_CFG2_NUM_PR;
995 out_be32(&im->ddr.sdram_cfg2, sdram_cfg2);
997 sdmode = dev_read_u32_default(dev, "sdmode", 0);
998 if (sdmode > 0xFFFF) {
999 debug("%s: sdmode value %d invalid.\n",
1004 esdmode = dev_read_u32_default(dev, "esdmode", 0);
1005 if (esdmode > 0xFFFF) {
1006 debug("%s: esdmode value %d invalid.\n", dev->name, esdmode);
1010 sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT |
1011 esdmode << SDRAM_MODE_ESD_SHIFT;
1013 out_be32(&im->ddr.sdram_mode, sdram_mode);
1015 esdmode2 = dev_read_u32_default(dev, "esdmode2", 0);
1016 if (esdmode2 > 0xFFFF) {
1017 debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2);
1021 esdmode3 = dev_read_u32_default(dev, "esdmode3", 0);
1022 if (esdmode3 > 0xFFFF) {
1023 debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3);
1027 sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT |
1028 esdmode3 << SDRAM_MODE2_ESD3_SHIFT;
1030 out_be32(&im->ddr.sdram_mode2, sdram_mode2);
1032 refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0);
1033 if (refresh_interval > 0xFFFF) {
1034 debug("%s: refresh_interval value %d invalid.\n",
1035 dev->name, refresh_interval);
1039 precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0);
1040 if (precharge_interval > 0x3FFF) {
1041 debug("%s: precharge_interval value %d invalid.\n",
1042 dev->name, precharge_interval);
1046 sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT |
1047 precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT;
1049 out_be32(&im->ddr.sdram_interval, sdram_interval);
1052 /* Enable DDR controller */
1053 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
1056 dev_for_each_subnode(subnode, dev) {
1060 /* CS, map address, size -> three values */
1061 ofnode_read_u32_array(subnode, "reg", val, 3);
1066 priv->total_size += get_ram_size((long int *)addr, size);
1069 gd->ram_size = priv->total_size;
1074 static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info)
1076 /* TODO(mario.six@gdsys.cc): Implement */
1080 static struct ram_ops mpc83xx_sdram_ops = {
1081 .get_info = mpc83xx_sdram_get_info,
1084 static const struct udevice_id mpc83xx_sdram_ids[] = {
1085 { .compatible = "fsl,mpc83xx-mem-controller" },
1089 U_BOOT_DRIVER(mpc83xx_sdram) = {
1090 .name = "mpc83xx_sdram",
1092 .of_match = mpc83xx_sdram_ids,
1093 .ops = &mpc83xx_sdram_ops,
1094 .ofdata_to_platdata = mpc83xx_sdram_ofdata_to_platdata,
1095 .probe = mpc83xx_sdram_probe,
1096 .priv_auto_alloc_size = sizeof(struct mpc83xx_sdram_priv),