drivers/ram/k3-am654-ddrss.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Texas Instruments' AM654 DDRSS driver
   4  *
   5  * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
   6  *      Lokesh Vutla <lokeshvutla@ti.com>
   7  */
   8
   9 #include <common.h>
  10 #include <clk.h>
  11 #include <dm.h>
  12 #include <ram.h>
  13 #include <asm/io.h>
  14 #include <power-domain.h>
  15 #include <dm.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <dm/device_compat.h>
  18 #include <power/regulator.h>
  19 #include "k3-am654-ddrss.h"
  20
  21 #define LDELAY 10000
  22
  23 /* DDRSS PHY configuration register fixed values */
  24 #define DDRSS_DDRPHY_RANKIDR_RANK0      0
  25
  26 /**
  27  * struct am654_ddrss_desc - Description of ddrss integration.
  28  * @dev:                DDRSS device pointer
  29  * @ddrss_ss_cfg:       DDRSS wrapper logic region base address
  30  * @ddrss_ctl_cfg:      DDRSS controller region base address
  31  * @ddrss_phy_cfg:      DDRSS PHY region base address
  32  * @ddrss_clk:          DDRSS clock description
  33  * @vtt_supply:         VTT Supply regulator
  34  * @ddrss_pwrdmn:       DDRSS power domain description
  35  * @params:             SDRAM configuration parameters
  36  */
  37 struct am654_ddrss_desc {
  38         struct udevice *dev;
  39         void __iomem *ddrss_ss_cfg;
  40         void __iomem *ddrss_ctl_cfg;
  41         void __iomem *ddrss_phy_cfg;
  42         struct clk ddrss_clk;
  43         struct udevice *vtt_supply;
  44         struct power_domain ddrcfg_pwrdmn;
  45         struct power_domain ddrdata_pwrdmn;
  46         struct ddrss_params params;
  47 };
  48
  49 static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
  50 {
  51         return readl(addr + offset);
  52 }
  53
  54 static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
  55                                 u32 data)
  56 {
  57         debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
  58         writel(data, addr + offset);
  59 }
  60
  61 #define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
  62 #define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
  63
  64 static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
  65 {
  66         return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
  67 }
  68
  69 /**
  70  * am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
  71  *
  72  * After detecting the DDR type this function will pause until the
  73  * initialization is complete. Each DDR type has mask of multiple bits.
  74  * The size of the field depends on the DDR Type. If the initialization
  75  * does not complete and error will be returned and will cause the boot to halt.
  76  *
  77  */
  78 static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
  79 {
  80         u32 val, mask;
  81
  82         val = am654_ddrss_get_type(ddrss);
  83
  84         switch (val) {
  85         case DDR_TYPE_LPDDR4:
  86         case DDR_TYPE_DDR4:
  87                 mask = DDR4_STAT_MODE_MASK;
  88                 break;
  89         case DDR_TYPE_DDR3:
  90                 mask = DDR3_STAT_MODE_MASK;
  91                 break;
  92         default:
  93                 printf("Unsupported DDR type 0x%x\n", val);
  94                 return -EINVAL;
  95         }
  96
  97         if (!wait_on_value(mask, DDR_MODE_NORMAL,
  98                            ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
  99                 return -ETIMEDOUT;
 100
 101         return 0;
 102 }
 103
 104 /**
 105  * am654_ddrss_ctrl_configuration() - Configure Controller specific registers
 106  * @dev:                corresponding ddrss device
 107  */
 108 static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
 109 {
 110         struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
 111         struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
 112         struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
 113         struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
 114         struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
 115         u32 val;
 116
 117         debug("%s: DDR controller register configuration started\n", __func__);
 118
 119         ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
 120         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
 121         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
 122
 123         ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
 124         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
 125         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
 126         ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
 127
 128         ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
 129         ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
 130         ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
 131         ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
 132         ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
 133         ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
 134         ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
 135
 136         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
 137         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
 138         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
 139         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
 140         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
 141         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
 142         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
 143         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
 144         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
 145         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
 146         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
 147         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG14, tmg->ddrctl_dramtmg14);
 148         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
 149         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
 150
 151         ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
 152         ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
 153
 154         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
 155         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
 156         ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
 157         ddrss_ctl_writel(DDRSS_DDRCTL_DFIMISC, reg->ddrctl_dfimisc);
 158
 159         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
 160         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
 161         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
 162         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
 163         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
 164         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
 165         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
 166         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
 167         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
 168         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
 169         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
 170         ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
 171
 172         ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
 173         ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
 174
 175         /* Disable refreshes */
 176         val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
 177         val |= 0x01;
 178         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
 179
 180         debug("%s: DDR controller configuration completed\n", __func__);
 181 }
 182
 183 #define ddrss_phy_writel(off, val)                                      \
 184         do {                                                            \
 185                 ddrss_writel(ddrss->ddrss_phy_cfg, off, val);           \
 186                 sdelay(10);     /* Delay at least 20 clock cycles */    \
 187         } while (0)
 188
 189 #define ddrss_phy_readl(off)                                            \
 190         ({                                                              \
 191                 u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off);       \
 192                 sdelay(10);     /* Delay at least 20 clock cycles */    \
 193                 val;                                                    \
 194         })
 195
 196 /**
 197  * am654_ddrss_phy_configuration() - Configure PHY specific registers
 198  * @ddrss:              corresponding ddrss device
 199  */
 200 static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
 201 {
 202         struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
 203         struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
 204         struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
 205         struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
 206         struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
 207
 208         debug("%s: DDR phy register configuration started\n", __func__);
 209
 210         ddrss_phy_writel(DDRSS_DDRPHY_PGCR0, cfg->ddrphy_pgcr0);
 211         ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
 212         ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
 213         ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
 214         ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
 215
 216         ddrss_phy_writel(DDRSS_DDRPHY_PTR2, tmg->ddrphy_ptr2);
 217         ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
 218         ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
 219         ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
 220         ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
 221
 222         ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
 223
 224         ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
 225         ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
 226
 227         ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
 228
 229         ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
 230         ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
 231         ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
 232         ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
 233         ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
 234         ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
 235         ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
 236
 237         ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
 238         ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
 239         ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
 240
 241         ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
 242         ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
 243         ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
 244         ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
 245         ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
 246         ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
 247         ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
 248         ddrss_phy_writel(DDRSS_DDRPHY_MR11, ctrl->ddrphy_mr11);
 249         ddrss_phy_writel(DDRSS_DDRPHY_MR12, ctrl->ddrphy_mr12);
 250         ddrss_phy_writel(DDRSS_DDRPHY_MR13, ctrl->ddrphy_mr13);
 251         ddrss_phy_writel(DDRSS_DDRPHY_MR14, ctrl->ddrphy_mr14);
 252         ddrss_phy_writel(DDRSS_DDRPHY_MR22, ctrl->ddrphy_mr22);
 253
 254         ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
 255
 256         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
 257         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
 258         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
 259
 260         ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
 261         ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
 262
 263         ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR0, ioctl->ddrphy_aciocr0);
 264         ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR3, ioctl->ddrphy_aciocr3);
 265         ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
 266         ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
 267
 268         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
 269         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
 270         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
 271         ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
 272
 273         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
 274         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
 275         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
 276         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
 277
 278         ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
 279         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
 280         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
 281         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
 282         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
 283
 284         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
 285
 286         ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
 287         ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
 288         ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
 289         ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
 290         ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
 291
 292         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
 293         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
 294         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
 295
 296         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
 297         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
 298         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
 299
 300         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, cfg->ddrphy_dx8sl0dqsctl);
 301         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, cfg->ddrphy_dx8sl1dqsctl);
 302         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, cfg->ddrphy_dx8sl2dqsctl);
 303
 304         debug("%s: DDR phy register configuration completed\n", __func__);
 305 }
 306
 307 static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
 308                                       u32 init_value, u32 sts_mask,
 309                                       u32 err_mask)
 310 {
 311         int ret;
 312
 313         ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
 314
 315         sdelay(5);      /* Delay at least 10 clock cycles */
 316
 317         if (!wait_on_value(sts_mask, sts_mask,
 318                            ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
 319                 return -ETIMEDOUT;
 320
 321         sdelay(16);     /* Delay at least 32 clock cycles */
 322
 323         ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
 324         debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
 325         if (ret & err_mask)
 326                 return -EINVAL;
 327
 328         return 0;
 329 }
 330
 331 int write_leveling(struct am654_ddrss_desc *ddrss)
 332 {
 333         int ret;
 334
 335         debug("%s: Write leveling started\n", __func__);
 336
 337         ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
 338                                          PGSR0_WLERR_MASK);
 339         if (ret) {
 340                 if (ret == -ETIMEDOUT)
 341                         printf("%s: ERROR: Write leveling timedout\n",
 342                                __func__);
 343                 else
 344                         printf("%s:ERROR: Write leveling failed\n", __func__);
 345                 return ret;
 346         }
 347
 348         debug("%s: Write leveling completed\n", __func__);
 349         return 0;
 350 }
 351
 352 int read_dqs_training(struct am654_ddrss_desc *ddrss)
 353 {
 354         int ret;
 355
 356         debug("%s: Read DQS training started\n", __func__);
 357
 358         ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
 359                                          PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
 360         if (ret) {
 361                 if (ret == -ETIMEDOUT)
 362                         printf("%s: ERROR: Read DQS timedout\n", __func__);
 363                 else
 364                         printf("%s:ERROR: Read DQS Gate training failed\n",
 365                                __func__);
 366                 return ret;
 367         }
 368
 369         debug("%s: Read DQS training completed\n", __func__);
 370         return 0;
 371 }
 372
 373 int dqs2dq_training(struct am654_ddrss_desc *ddrss)
 374 {
 375         int ret;
 376
 377         debug("%s: DQS2DQ training started\n", __func__);
 378
 379         ret = __phy_builtin_init_routine(ddrss, PIR_DQS2DQ_MASK,
 380                                          PGSR0_DQS2DQDONE_MASK,
 381                                          PGSR0_DQS2DQERR_MASK);
 382         if (ret) {
 383                 if (ret == -ETIMEDOUT)
 384                         printf("%s: ERROR: DQS2DQ training timedout\n",
 385                                __func__);
 386                 else
 387                         printf("%s:ERROR: DQS2DQ training failed\n",
 388                                __func__);
 389                 return ret;
 390         }
 391
 392         debug("%s: DQS2DQ training completed\n", __func__);
 393         return 0;
 394 }
 395
 396 int write_leveling_adjustment(struct am654_ddrss_desc *ddrss)
 397 {
 398         int ret;
 399
 400         debug("%s: Write Leveling adjustment\n", __func__);
 401         ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
 402                                          PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
 403         if (ret) {
 404                 if (ret == -ETIMEDOUT)
 405                         printf("%s:ERROR: Write Leveling adjustment timedout\n",
 406                                __func__);
 407                 else
 408                         printf("%s: ERROR: Write Leveling adjustment failed\n",
 409                                __func__);
 410                 return ret;
 411         }
 412         return 0;
 413 }
 414
 415 int rest_training(struct am654_ddrss_desc *ddrss)
 416 {
 417         int ret;
 418
 419         debug("%s: Rest of the training started\n", __func__);
 420
 421         debug("%s: Read Deskew adjustment\n", __func__);
 422         ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
 423                                          PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
 424         if (ret) {
 425                 if (ret == -ETIMEDOUT)
 426                         printf("%s: ERROR: Read Deskew timedout\n", __func__);
 427                 else
 428                         printf("%s: ERROR: Read Deskew failed\n", __func__);
 429                 return ret;
 430         }
 431
 432         debug("%s: Write Deskew adjustment\n", __func__);
 433         ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
 434                                          PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
 435         if (ret) {
 436                 if (ret == -ETIMEDOUT)
 437                         printf("%s: ERROR: Write Deskew timedout\n", __func__);
 438                 else
 439                         printf("%s: ERROR: Write Deskew failed\n", __func__);
 440                 return ret;
 441         }
 442
 443         debug("%s: Read Eye training\n", __func__);
 444         ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
 445                                          PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
 446         if (ret) {
 447                 if (ret == -ETIMEDOUT)
 448                         printf("%s: ERROR: Read Eye training timedout\n",
 449                                __func__);
 450                 else
 451                         printf("%s: ERROR: Read Eye training failed\n",
 452                                __func__);
 453                 return ret;
 454         }
 455
 456         debug("%s: Write Eye training\n", __func__);
 457         ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
 458                                          PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
 459         if (ret) {
 460                 if (ret == -ETIMEDOUT)
 461                         printf("%s: ERROR: Write Eye training timedout\n",
 462                                __func__);
 463                 else
 464                         printf("%s: ERROR: Write Eye training failed\n",
 465                                __func__);
 466                 return ret;
 467         }
 468         return 0;
 469 }
 470
 471 int VREF_training(struct am654_ddrss_desc *ddrss)
 472 {
 473         int ret;
 474         debug("%s: VREF training\n", __func__);
 475         ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
 476                                          PGSR0_VERR_MASK);
 477         if (ret) {
 478                 if (ret == -ETIMEDOUT)
 479                         printf("%s: ERROR: VREF training timedout\n", __func__);
 480                 else
 481                         printf("%s: ERROR: VREF training failed\n", __func__);
 482                 return ret;
 483         }
 484         return 0;
 485 }
 486
 487 int enable_dqs_pd(struct am654_ddrss_desc *ddrss)
 488 {
 489         u32 val;
 490
 491         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
 492         val &= ~0xFF;
 493         val |= 0xF7;
 494         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
 495
 496         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
 497         val &= ~0xFF;
 498         val |= 0xF7;
 499         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
 500
 501         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
 502         val &= ~0xFF;
 503         val |= 0xF7;
 504         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
 505
 506         sdelay(16);
 507         return 0;
 508 }
 509
 510 int disable_dqs_pd(struct am654_ddrss_desc *ddrss)
 511 {
 512         u32 val;
 513
 514         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL0DQSCTL);
 515         val &= ~0xFF;
 516         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DQSCTL, val);
 517
 518         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL1DQSCTL);
 519         val &= ~0xFF;
 520         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DQSCTL, val);
 521
 522         val = ddrss_phy_readl(DDRSS_DDRPHY_DX8SL2DQSCTL);
 523         val &= ~0xFF;
 524         ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DQSCTL, val);
 525
 526         sdelay(16);
 527         return 0;
 528 }
 529
 530 int cleanup_training(struct am654_ddrss_desc *ddrss)
 531 {
 532         u32 val;
 533         u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
 534
 535         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
 536         dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
 537         dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
 538         dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
 539         dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
 540
 541         rddly = dgsl0;
 542         if (dgsl1 < rddly)
 543                 rddly = dgsl1;
 544         if (dgsl2 < rddly)
 545                 rddly = dgsl2;
 546         if (dgsl3 < rddly)
 547                 rddly = dgsl3;
 548
 549         rddly += 5;
 550
 551         /* Update rddly based on dgsl values */
 552         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
 553         val |= (rddly << 20);
 554         ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
 555
 556         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
 557         val |= (rddly << 20);
 558         ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
 559
 560         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
 561         val |= (rddly << 20);
 562         ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
 563
 564         val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
 565         val |= (rddly << 20);
 566         ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
 567
 568         /*
 569          * Add system latency derived from training back into rd2wr and wr2rd
 570          * rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
 571          * wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
 572          */
 573
 574         /* Select rank 0 */
 575         ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
 576
 577         dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
 578         dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
 579         dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
 580         dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
 581
 582         /* Find maximum value across all bytes */
 583         rd2wr_wr2rd = dgsl0;
 584         if (dgsl1 > rd2wr_wr2rd)
 585                 rd2wr_wr2rd = dgsl1;
 586         if (dgsl2 > rd2wr_wr2rd)
 587                 rd2wr_wr2rd = dgsl2;
 588         if (dgsl3 > rd2wr_wr2rd)
 589                 rd2wr_wr2rd = dgsl3;
 590
 591         rd2wr_wr2rd >>= 1;
 592
 593         /* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
 594         /* Clear VSWCTL.sw_done */
 595         ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
 596                          ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
 597         /* Adjust rd2wr */
 598         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
 599                          ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
 600                          (rd2wr_wr2rd << 8));
 601         /* Adjust wr2rd */
 602         ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
 603                          ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
 604                          rd2wr_wr2rd);
 605         /* Set VSWCTL.sw_done */
 606         ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
 607                          ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
 608         /* Wait until settings are applied */
 609         while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
 610                 /* Do nothing */
 611         };
 612
 613         debug("%s: Rest of the training completed\n", __func__);
 614         return 0;
 615 }
 616
 617 /**
 618  * am654_ddrss_init() - Initialization sequence for enabling the SDRAM
 619  *                      device attached to ddrss.
 620  * @dev:                corresponding ddrss device
 621  *
 622  * Does all the initialization sequence that is required to get attached
 623  * ddr in a working state. After this point, ddr should be accessible.
 624  * Return: 0 if all went ok, else corresponding error message.
 625  */
 626 static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
 627 {
 628         int ret;
 629         u32 val;
 630         struct ddrss_ss_reg_params *reg = &ddrss->params.ss_reg;
 631
 632         debug("Starting DDR initialization...\n");
 633
 634         debug("%s(ddrss=%p)\n", __func__, ddrss);
 635
 636         ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG,
 637                      reg->ddrss_v2h_ctl_reg);
 638
 639         am654_ddrss_ctrl_configuration(ddrss);
 640
 641         /* Release the reset to the controller */
 642         clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
 643                      SS_CTL_REG_CTL_ARST_MASK);
 644
 645         am654_ddrss_phy_configuration(ddrss);
 646
 647         debug("Starting DDR training...\n");
 648         ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
 649         if (ret) {
 650                 dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
 651                 return ret;
 652         }
 653
 654         ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 655                                          PGSR0_DRAM_INIT_MASK, 0);
 656         if (ret) {
 657                 dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
 658                 return ret;
 659         }
 660
 661         ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 662         if (ret) {
 663                 printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 664                        __func__);
 665                 return ret;
 666         }
 667
 668         val = am654_ddrss_get_type(ddrss);
 669
 670         switch (val) {
 671         case DDR_TYPE_LPDDR4:
 672
 673                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 674                                                  PGSR0_DRAM_INIT_MASK, 0);
 675                 if (ret) {
 676                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 677                                 ret);
 678                         return ret;
 679                 }
 680
 681                 /* must perform DRAM_INIT twice for LPDDR4 */
 682                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 683                                                  PGSR0_DRAM_INIT_MASK, 0);
 684                 if (ret) {
 685                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 686                                 ret);
 687                         return ret;
 688                 }
 689
 690                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 691                 if (ret) {
 692                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 693                                __func__);
 694                         return ret;
 695                 }
 696
 697                 ret = write_leveling(ddrss);
 698                 if (ret)
 699                         return ret;
 700
 701                 ret = enable_dqs_pd(ddrss);
 702                 if (ret)
 703                         return ret;
 704
 705                 ret = read_dqs_training(ddrss);
 706                 if (ret)
 707                         return ret;
 708
 709                 ret = disable_dqs_pd(ddrss);
 710                 if (ret)
 711                         return ret;
 712
 713                 ret = dqs2dq_training(ddrss);
 714                 if (ret)
 715                         return ret;
 716
 717                 ret = write_leveling_adjustment(ddrss);
 718                 if (ret)
 719                         return ret;
 720
 721                 ret = rest_training(ddrss);
 722                 if (ret)
 723                         return ret;
 724
 725                 ret = VREF_training(ddrss);
 726                 if (ret)
 727                         return ret;
 728
 729                 debug("LPDDR4 training complete\n");
 730                 break;
 731
 732         case DDR_TYPE_DDR4:
 733
 734                 debug("Starting DDR4 training\n");
 735
 736                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 737                                                  PGSR0_DRAM_INIT_MASK, 0);
 738                 if (ret) {
 739                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 740                                 ret);
 741                         return ret;
 742                 }
 743
 744                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 745                 if (ret) {
 746                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 747                                __func__);
 748                         return ret;
 749                 }
 750
 751                 ret = write_leveling(ddrss);
 752                 if (ret)
 753                         return ret;
 754
 755                 ret = read_dqs_training(ddrss);
 756                 if (ret)
 757                         return ret;
 758
 759                 ret = write_leveling_adjustment(ddrss);
 760                 if (ret)
 761                         return ret;
 762
 763                 ret = rest_training(ddrss);
 764                 if (ret)
 765                         return ret;
 766
 767                 ret = VREF_training(ddrss);
 768                 if (ret)
 769                         return ret;
 770                 debug("DDR4 training complete\n");
 771                 break;
 772
 773         case DDR_TYPE_DDR3:
 774
 775                 debug("Starting DDR3 training\n");
 776
 777                 ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
 778                                                  PGSR0_DRAM_INIT_MASK, 0);
 779                 if (ret) {
 780                         dev_err(ddrss->dev, "DRAM initialization failed %d\n",
 781                                 ret);
 782                         return ret;
 783                 }
 784
 785                 ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
 786                 if (ret) {
 787                         printf("%s: ERROR: DRAM Wait for init complete timedout\n",
 788                                __func__);
 789                         return ret;
 790                 }
 791
 792                 ret = write_leveling(ddrss);
 793                 if (ret)
 794                         return ret;
 795
 796                 ret = enable_dqs_pd(ddrss);
 797                 if (ret)
 798                         return ret;
 799
 800                 ret = read_dqs_training(ddrss);
 801                 if (ret)
 802                         return ret;
 803
 804                 ret = disable_dqs_pd(ddrss);
 805                 if (ret)
 806                         return ret;
 807
 808                 ret = write_leveling_adjustment(ddrss);
 809                 if (ret)
 810                         return ret;
 811
 812                 ret = rest_training(ddrss);
 813                 if (ret)
 814                         return ret;
 815
 816                 debug("DDR3 training complete\n");
 817                 break;
 818         default:
 819                 printf("%s: ERROR: Unsupported DDR type\n", __func__);
 820                 return -EINVAL;
 821         }
 822
 823         ret = cleanup_training(ddrss);
 824         if (ret)
 825                 return ret;
 826
 827         /* Enabling refreshes after training is done */
 828         ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
 829                          ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
 830
 831         /* Disable PUBMODE after training is done */
 832         ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
 833                          ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
 834
 835         debug("Completed DDR training\n");
 836
 837         return 0;
 838 }
 839
 840 /**
 841  * am654_ddrss_power_on() - Enable power and clocks for ddrss
 842  * @dev:        corresponding ddrss device
 843  *
 844  * Tries to enable all the corresponding clocks to the ddrss and sets it
 845  * to the right frequency and then power on the ddrss.
 846  * Return: 0 if all went ok, else corresponding error message.
 847  */
 848 static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
 849 {
 850         int ret;
 851
 852         debug("%s(ddrss=%p)\n", __func__, ddrss);
 853
 854         ret = clk_enable(&ddrss->ddrss_clk);
 855         if (ret) {
 856                 dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
 857                 return ret;
 858         }
 859
 860         ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
 861         if (ret) {
 862                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 863                 return ret;
 864         }
 865
 866         ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
 867         if (ret) {
 868                 dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
 869                 return ret;
 870         }
 871
 872         /* VTT enable */
 873 #if CONFIG_IS_ENABLED(DM_REGULATOR)
 874         device_get_supply_regulator(ddrss->dev, "vtt-supply",
 875                                     &ddrss->vtt_supply);
 876         ret = regulator_set_value(ddrss->vtt_supply, 3300000);
 877         if (ret)
 878                 return ret;
 879         debug("VTT regulator enabled\n");
 880 #endif
 881
 882         return 0;
 883 }
 884
 885 /**
 886  * am654_ddrss_ofdata_to_priv() - generate private data from device tree
 887  * @dev:        corresponding ddrss device
 888  *
 889  * Return: 0 if all went ok, else corresponding error message.
 890  */
 891 static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
 892 {
 893         struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
 894         phys_addr_t reg;
 895         int ret;
 896
 897         debug("%s(dev=%p)\n", __func__, dev);
 898
 899         ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
 900         if (ret) {
 901                 dev_err(dev, "clk_get failed: %d\n", ret);
 902                 return ret;
 903         }
 904
 905         ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 906         if (ret) {
 907                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 908                 return ret;
 909         }
 910
 911         ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
 912         if (ret) {
 913                 dev_err(dev, "power_domain_get() failed: %d\n", ret);
 914                 return ret;
 915         }
 916
 917         reg = devfdt_get_addr_name(dev, "ss");
 918         if (reg == FDT_ADDR_T_NONE) {
 919                 dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 920                 return -EINVAL;
 921         }
 922         ddrss->ddrss_ss_cfg = (void *)reg;
 923
 924         reg = devfdt_get_addr_name(dev, "ctl");
 925         if (reg == FDT_ADDR_T_NONE) {
 926                 dev_err(dev, "No reg property for Controller region\n");
 927                 return -EINVAL;
 928         }
 929         ddrss->ddrss_ctl_cfg = (void *)reg;
 930
 931         reg = devfdt_get_addr_name(dev, "phy");
 932         if (reg == FDT_ADDR_T_NONE) {
 933                 dev_err(dev, "No reg property for PHY region\n");
 934                 return -EINVAL;
 935         }
 936         ddrss->ddrss_phy_cfg = (void *)reg;
 937
 938         ret = dev_read_u32_array(dev, "ti,ss-reg",
 939                                  (u32 *)&ddrss->params.ss_reg,
 940                                  sizeof(ddrss->params.ss_reg) / sizeof(u32));
 941         if (ret) {
 942                 dev_err(dev, "Cannot read ti,ss-reg params\n");
 943                 return ret;
 944         }
 945
 946         ret = dev_read_u32_array(dev, "ti,ctl-reg",
 947                                  (u32 *)&ddrss->params.ctl_reg,
 948                                  sizeof(ddrss->params.ctl_reg) / sizeof(u32));
 949         if (ret) {
 950                 dev_err(dev, "Cannot read ti,ctl-reg params\n");
 951                 return ret;
 952         }
 953
 954         ret = dev_read_u32_array(dev, "ti,ctl-crc",
 955                                  (u32 *)&ddrss->params.ctl_crc,
 956                                  sizeof(ddrss->params.ctl_crc) / sizeof(u32));
 957         if (ret) {
 958                 dev_err(dev, "Cannot read ti,ctl-crc params\n");
 959                 return ret;
 960         }
 961
 962         ret = dev_read_u32_array(dev, "ti,ctl-ecc",
 963                                  (u32 *)&ddrss->params.ctl_ecc,
 964                                  sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
 965         if (ret) {
 966                 dev_err(dev, "Cannot read ti,ctl-ecc params\n");
 967                 return ret;
 968         }
 969
 970         ret = dev_read_u32_array(dev, "ti,ctl-map",
 971                                  (u32 *)&ddrss->params.ctl_map,
 972                                  sizeof(ddrss->params.ctl_map) / sizeof(u32));
 973         if (ret) {
 974                 dev_err(dev, "Cannot read ti,ctl-map params\n");
 975                 return ret;
 976         }
 977
 978         ret = dev_read_u32_array(dev, "ti,ctl-pwr",
 979                                  (u32 *)&ddrss->params.ctl_pwr,
 980                                  sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
 981         if (ret) {
 982                 dev_err(dev, "Cannot read ti,ctl-pwr params\n");
 983                 return ret;
 984         }
 985
 986         ret = dev_read_u32_array(dev, "ti,ctl-timing",
 987                                  (u32 *)&ddrss->params.ctl_timing,
 988                                  sizeof(ddrss->params.ctl_timing) /
 989                                  sizeof(u32));
 990         if (ret) {
 991                 dev_err(dev, "Cannot read ti,ctl-timing params\n");
 992                 return ret;
 993         }
 994
 995         ret = dev_read_u32_array(dev, "ti,phy-cfg",
 996                                  (u32 *)&ddrss->params.phy_cfg,
 997                                  sizeof(ddrss->params.phy_cfg) / sizeof(u32));
 998         if (ret) {
 999                 dev_err(dev, "Cannot read ti,phy-cfg params\n");
1000                 return ret;
1001         }
1002
1003         ret = dev_read_u32_array(dev, "ti,phy-ctl",
1004                                  (u32 *)&ddrss->params.phy_ctrl,
1005                                  sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
1006         if (ret) {
1007                 dev_err(dev, "Cannot read ti,phy-ctl params\n");
1008                 return ret;
1009         }
1010
1011         ret = dev_read_u32_array(dev, "ti,phy-ioctl",
1012                                  (u32 *)&ddrss->params.phy_ioctl,
1013                                  sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
1014         if (ret) {
1015                 dev_err(dev, "Cannot read ti,phy-ioctl params\n");
1016                 return ret;
1017         }
1018
1019         ret = dev_read_u32_array(dev, "ti,phy-timing",
1020                                  (u32 *)&ddrss->params.phy_timing,
1021                                  sizeof(ddrss->params.phy_timing) /
1022                                  sizeof(u32));
1023         if (ret) {
1024                 dev_err(dev, "Cannot read ti,phy-timing params\n");
1025                 return ret;
1026         }
1027
1028         ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
1029                                  sizeof(ddrss->params.phy_zq) / sizeof(u32));
1030         if (ret) {
1031                 dev_err(dev, "Cannot read ti,phy-zq params\n");
1032                 return ret;
1033         }
1034
1035         return ret;
1036 }
1037
1038 /**
1039  * am654_ddrss_probe() - Basic probe
1040  * @dev:        corresponding ddrss device
1041  *
1042  * Return: 0 if all went ok, else corresponding error message
1043  */
1044 static int am654_ddrss_probe(struct udevice *dev)
1045 {
1046         struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
1047         int ret;
1048
1049         debug("%s(dev=%p)\n", __func__, dev);
1050
1051         ret = am654_ddrss_ofdata_to_priv(dev);
1052         if (ret)
1053                 return ret;
1054
1055         ddrss->dev = dev;
1056         ret = am654_ddrss_power_on(ddrss);
1057         if (ret)
1058                 return ret;
1059
1060         ret = am654_ddrss_init(ddrss);
1061
1062         return ret;
1063 }
1064
1065 static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
1066 {
1067         return 0;
1068 }
1069
1070 static struct ram_ops am654_ddrss_ops = {
1071         .get_info = am654_ddrss_get_info,
1072 };
1073
1074 static const struct udevice_id am654_ddrss_ids[] = {
1075         { .compatible = "ti,am654-ddrss" },
1076         { }
1077 };
1078
1079 U_BOOT_DRIVER(am654_ddrss) = {
1080         .name = "am654_ddrss",
1081         .id = UCLASS_RAM,
1082         .of_match = am654_ddrss_ids,
1083         .ops = &am654_ddrss_ops,
1084         .probe = am654_ddrss_probe,
1085         .priv_auto_alloc_size = sizeof(struct am654_ddrss_desc),
1086 };